CN110024113B - 集成电路封装结构及方法 - Google Patents

集成电路封装结构及方法 Download PDF

Info

Publication number
CN110024113B
CN110024113B CN201680090828.8A CN201680090828A CN110024113B CN 110024113 B CN110024113 B CN 110024113B CN 201680090828 A CN201680090828 A CN 201680090828A CN 110024113 B CN110024113 B CN 110024113B
Authority
CN
China
Prior art keywords
chip
fine
substrate
additional
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680090828.8A
Other languages
English (en)
Other versions
CN110024113A (zh
Inventor
胡川
刘俊军
郭跃进
爱德华·鲁道夫·普莱克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Xiuyuan Electronic Technology Co ltd
Original Assignee
Shenzhen Xiuyuan Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Xiuyuan Electronic Technology Co ltd filed Critical Shenzhen Xiuyuan Electronic Technology Co ltd
Publication of CN110024113A publication Critical patent/CN110024113A/zh
Application granted granted Critical
Publication of CN110024113B publication Critical patent/CN110024113B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/115—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种集成电路封装结构及方法，其中集成电路封装结构包括：基板(100)，所述基板(100)设有电路层(110)以及精细连线(210)；芯片(400)，所述芯片(400)设有精细引脚(420)、以及芯片引脚(410)；所述基板(100)设有至少两个所述芯片(400)，至少一个所述芯片(400)的所述芯片引脚(410)与所述电路层(110)电连接，所述电路层(110)上设有绝缘补丁(200)，所述绝缘补丁(200)上设有精细连线(210)，所述芯片(400)的精细引脚(420)与所述精细连线(210)电连接、至少两个所述芯片(400)通过所述精细连线(210)直接电连接。传输速度快、提高芯片性能。

Description

集成电路封装结构及方法
技术领域
本发明属于电子领域，具体涉及一种集成电路封装结构及方法。
背景技术
传统的集成电路***，需要将芯片单独封装后，再与其它电子元件等一起安装于电路板上。芯片之间、芯片和其它电子元件之间的数据通讯需要通过电路板内部的电路。芯片之间、芯片和其它电子元件之间必须留有足够空间，整个***的几何尺寸也因而受到约束，不能充分小型化，因为每个芯片都要单独封装以后，经常需要通过以键合或者倒装的方式连接到基板的电路端口上，再接入到电路板上，各种材料使用量大，工艺复杂，生产成本高；而且使用大量特性各异的材料，也容易在各材料界面诱发多种热机械应力的问题。并且，受制于制作工艺，芯片之间的通讯速度受限，严重制约集成电路的整体性能。
发明内容
基于此，本发明在于克服现有技术的缺陷，提供一种集成电路封装结构及方法，以提高芯片间数据传输带宽和速度、提高***性能。
其技术方案如下：
一种集成电路封装结构，包括：基板，所述基板设有电路层以及精细连线；芯片，所述芯片设有精细引脚、以及芯片引脚；所述基板设有至少两个所述芯片，至少一个所述芯片的所述芯片引脚与所述电路层电连接，所述电路层上设有绝缘补丁，所述绝缘补丁上设有精细连线，所述芯片的精细引脚与所述精细连线电连接、至少两个所述芯片通过所述精细连线直接电连接。
在其中一个实施例中，所述芯片引脚与所述精细引脚之间设有连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电通道，所述精细引脚通过所述精细导电通道与所述精细引脚电连接。
在其中一个实施例中，所述精细连线的宽度为0.1微米至2微米、或1微米至5微米。
在其中一个实施例中，在所述芯片的上设有散热装置。
在其中一个实施例中，还包括有封装层，所述芯片、所述精细连线、以及所述绝缘补丁位于所述封装层与所述基板之间，所述封装层将所述芯片以及所述绝缘补丁封装与所述基板。
在其中一个实施例中，所述基板为柔性电路板，或所述基板包括至少两层层叠设置的柔性电路板。
在其中一个实施例中，所述芯片位于所述基板的顶面，所述基板底面或/和所述基板内设有所述附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，所述附加通孔的第二开口为操作窗口，所述附加通孔内设有附加导电层，所述附加导电层将所述芯片引脚和所述附加引脚电连接。
在其中一个实施例中，所述芯片引脚为至少两个，所述导电层为与所述芯片引脚相应的至少两个，所述基板的底面设有外接端口，所述外接端口与至少一个所述导电层电连接。
在其中一个实施例中，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述芯片引脚和所述电路引脚电连接。
在其中一个实施例中，所述绝缘补丁所占区域的面积小于所述电路层所占区域的面积。
一种集成电路封装方法，包括：所述基板设有电路层，在所述基板设置绝缘补丁，在所述绝缘补丁上制作精细连线，将至少两个所述芯片设置于所述基板，所述芯片设有精细引脚、以及芯片引脚，将所述芯片引脚与所述电路层电连接，将所述精细引脚与所述精细连线电连接，使至少两个所述芯片通过所述精细连线直接连接。
在其中一个实施例中，包括：所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述连接通孔的第一开口对接；通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接；或者，所述电路层设有电路引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作连接通孔，使所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
在其中一个实施例中，包括：所述基板底面或/和所述基板内设有所述附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述附加通孔的第一开口对接；通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，使所述附加导电层将所述芯片引脚与所述附加引脚电连接；或者，所述附加电路层设有附加引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作附加通孔，使所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，通过所述附加通孔的第二开口在所述附加通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
在其中一个实施例中，还包括：在所述基板设置封装层，所述芯片、所述绝缘补丁、以及所述精细引脚位于所述封装层与所述基板之间，所述封装层将所述芯片、所述绝缘补丁、以及所述精细引脚包裹封装。
在其中一个实施例中，在所述基板上设置导体层，在所述导体层上设置所述绝缘补丁，在所述绝缘补丁上设置导体膜，所述导体层的厚度大于所述导体膜的厚度，在所述导体层和导体膜上设置抗蚀剂，所述抗蚀剂设有连线图案，采用化学蚀刻方法，按照所述连线图案将所述导体层蚀刻成所述电路层、将所述导体膜蚀刻成所述精细连线。
在其中一个实施例中，在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在所述连线槽内生长出所述精细连线。
在其中一个实施例中，在载体上制作绝缘补丁，在所述绝缘补丁上制作所述精细连线，将所述绝缘补丁连同所述精细连线转移至所述基板，将所述精细连线固定于所述基板。
在其中一个实施例中，所述芯片与所述精细引脚之间设置连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电颗粒；所述芯片引脚与所述精细引脚之间的间距小于或等于所述精细导电颗粒的高度，所述芯片安放于所述基板，所述精细导电颗粒的一端与所述精细引脚电连接、另一端与所述精细连线电连接；所述芯片引脚与所述精细连线之间的间距大于所述精细导电颗粒的高度，所述芯片引脚和所述精细连线不能通过所述导电颗粒电连接。
本发明的有益效果在于：
1、集成电路封装结构包括：基板，基板设有电路层以及精细连线；芯片，芯片设有精细引脚、以及芯片引脚；基板设有至少两个芯片，至少一个芯片的芯片引脚与电路层电连接，电路层上设有绝缘补丁，绝缘补丁上设有精细连线，芯片的精细引脚与精细连线电连接、至少两个芯片通过精细连线直接电连接。
芯片与电路层电连接，芯片可以与电路层上连接的其他电子元器件进行通讯或能量交换，芯片与芯片之间通过精细连线直接连接，减少受电路层上连接的其他电子元件的干扰，并且精细连线细小，在同样空间内可形成更多数量的连线，可以提供更高带宽的数据通讯能力，芯片之间可以获得更多的数据通道，传输速度快、带宽大。绝缘补丁将精细连线与电路层绝缘隔开，避免电路层对精细连线产生干扰。对要求高速度、款带宽的两个芯片之间的通讯，采用精细连线的方式，提高芯片之间的传输性能，对不要求高速度、宽带宽的两个芯片之间的通讯或者芯片与其他元器件之间的通讯可以通过电路层连接，降低制作成本。另一方面，采用设置绝缘补丁的方式，在基板上制作电路层、在预定位置设置绝缘补丁和精细连线等几项工艺可以批量流水作业，降低生产成本。
2、精细引脚与精细连线之间设有连接介质，连接介质包括绝缘介质、以及分布于绝缘介质内的至少一个精细导电通道，绝缘介质将芯片与精细引脚隔开，只在精细引脚与精细连线的位置将，避免干扰，精细引脚通过精细导电通道与精细引脚电连接。精细导电通道的形式包括但不限于：在绝缘介质中设置导电颗粒或焊块构成精细导电通道；绝缘介质设有精细导电孔，在精细导电孔内设置导电材料层构成精细导电通道；在芯片上的精细引脚或/绝缘补丁上的精细连线上设置导电性的凸点，导电性凸点构成精细导电通道。
3、精细连线的宽度为0.1微米至2微米、或1微米至5微米。精细连线的宽度，指的是精细连线横截面在绝缘补丁上的边长，精细连线的宽度小于电路层的连线的宽度，精细连线的宽度越小，可实现的连线密度越大，在同样大小的空间里可以设有越多的通讯连线数量，利于提高数据传输速度和带宽。
4、在芯片的上设有散热装置。由于芯片之间的通讯采用高带宽高速度的精细连线，芯片运算速率高、发热也增大，在芯片上加装散热装置，有利于芯片散热，保障工作性能。另一方面，绝缘补丁可能(如采用导热率高的材料则不存在此问题)会增加芯片向基板方向散热的难度，热阻抗增大，而且在芯片上(背相基板的一面)加装散热装置，有利于芯片从背面散热，不只依靠从基板的散热通道，这样，芯片就可以在更高的运算速度下正常工作。这种结构上的设计，一方面提高芯片之间的数据通讯带宽和速度、一方面保证芯片可以在更高的运算速度下正常工作，可以大幅提高***整体的运算性能。
5、集成电路封装结构还包括有封装层，芯片、精细连线、以及绝缘补丁位于封装层与基板之间，封装层将芯片以及绝缘补丁封装于基板。封装层可以保护芯片、绝缘补丁、精细连线不被损坏，减少外部环境因素对芯片性能的影响和干扰，保障芯片的工作性能。在有更多后续工序的情况下，固化后的封装层也提供了平整的表面和机械支撑性能，能够翻转***整体后在基板上进行后续制成工艺。
6、基板为柔性电路板，或基板包括至少两层层叠设置的柔性电路板。使用多层电路板及其内含的多层电路层，可以提供更多布线的可能，提高芯片的性能，使用柔性轻薄的电路板，降低***整体的重量、减小体积和厚度尺寸，通过采用本发明的集成电路封装结构和方法，可以使***整体在封装集成之后仍然具有足够的柔性，可以用于可穿戴产品。并且，采用绝缘补丁的方式，精细连线本身的厚度很小，绝缘补丁只要满足将精细连线与电路层绝缘就可以，不需要很厚的厚度，使得柔性电路板在集成芯片后仍然很薄、具备柔性。精细连线的厚度是指精细连线的横截面垂直于绝缘补丁的边长，绝缘补丁的厚度是指绝缘补丁的横截面垂直于基板的边长。
7、芯片位于基板的顶面，基板底面或/和基板内设有附加电路层，附加电路层设有附加引脚，基板设有附加通孔，附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚对接，附加通孔的第二开口为操作窗口，附加通孔内设有附加导电层，附加导电层将芯片引脚和附加引脚电连接。
所述附加电路层具有附加引脚，可以预先在基板制作好附加电路层，也可以在集成电路封装时再在基板上制作附加电路层，附加引脚可以是附加电路层直接引出的连接部，也可以是和所述连接部电连接的扩展引脚，只要通过附加引脚能够和附加电路层电连接均可。将芯片安放于所述基板，可以将芯片固定于基板上，也可以不固定。芯片与基板相对设置，所述芯片朝向所述基板的一面具有芯片引脚，芯片的芯片引脚包括但不限于芯片内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚能够和芯片电连接均可。在所述基板上制作附加通孔，使所述芯片引脚与所述附加通孔的第一开口对接，通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，所述附加导电层将所述芯片引脚与所述附加引脚电连接；芯片引脚位于基板的顶面，通过附加通孔的第二开口，可以从基板的底面将芯片与附加电路层电连接，以避免芯片从上方将芯片引脚遮挡；
其中，附加通孔与芯片引脚对接，附加引脚至少部分位于附加通孔的第一开口附近、或深入附加通孔内，使得附加导电层可以与芯片引脚电连接；附加引脚和附加通孔对接，附加引脚至少部分位于附加通孔的第一开口附近、或第二开口附近、或附加通孔内壁的附近，使得附加导电层可以与附加引脚电连接；芯片可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片可以通过附加通孔、附加导电层固定于所述基板，也可以是，芯片通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板。
如此，可以降低集成电路封装的成本、节约封装时间，进一步的，可以在很大面积的大面板上同时安装多个芯片，大面板上的批量处理进一步减低成本、节约封装时间。并且，可以降低基板和芯片构成的***整体的厚度，甚至基板和芯片之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板与芯片设置其他材料)；导电附加通孔的制作可以选择使用不需要加热焊接的工艺流程，因此可以避免高温热循环时各种热机械应力分布对超薄芯片和柔性电路板的机构和性能的损伤。这对使用超薄、柔性的电路板的封装工艺很有帮助。另一方面，在传统的引线键合封装技术中，采用导线来实现芯片与基板上电路层的电连接，而导线要相互避开，于是占用空间较大，本发明通过在基板上开设附加通孔的方式实现芯片与附加电路层的电连接，附加导电层设于附加通孔内，不占用额外空间，可以缩小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)基板底面或/和基板内设有附加电路层，附加电路层设有附加引脚，基板设有附加通孔，附加通孔与附加引脚对接；将芯片安放于基板的顶面，使芯片的芯片引脚与附加通孔的第一开口对接；通过附加通孔的第二开口在附加通孔内制作附加导电层，使附加导电层将芯片引脚与附加引脚电连接；
或者(2)，附加电路层设有附加引脚，将芯片安放于基板的顶面，使芯片的芯片引脚朝向基板，在基板上制作附加通孔，使附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚对接，通过附加通孔的第二开口在附加通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接。
8、芯片引脚为至少两个，导电层为与芯片引脚相应的至少两个，基板的底面设有外接端口，外接端口与至少一个导电层电连接。外接端口可以与另外的电子元件进行连接，扩展整个集成电路的功能，也可以用于连接电源，由电源直接对芯片供电。
9、基板设有连接通孔，连接通孔与电路引脚对接、并且连接通孔的第一开口与芯片引脚对接，连接通孔的第二开口为操作窗口，连接通孔内设有导电层，导电层将芯片引脚和电路引脚电连接。
所述电路层具有电路引脚，可以预先在基板制作好电路层，也可以在集成电路封装时再在基板上制作电路层，电路引脚可以是电路层直接引出的连接部，也可以是和所述连接部电连接的扩展引脚，只要通过电路引脚能够和电路层电连接均可。将芯片安放于所述基板，可以将芯片固定于基板上，也可以不固定。芯片与基板相对设置，所述芯片朝向所述基板的一面具有芯片引脚，芯片的芯片引脚包括但不限于芯片内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚能够和芯片电连接均可。在所述基板上制作连接通孔，使所述芯片引脚与所述连接通孔的第一开口对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，所述导电层将所述芯片引脚与所述电路引脚电连接；芯片引脚位于基板的顶面，通过连接通孔的第二开口，可以从基板的底面将芯片与电路层电连接，避免芯片将芯片引脚挡住；
其中，连接通孔与芯片引脚对接，电路引脚至少部分位于连接通孔的第一开口附近、或深入连接通孔内，使得导电层可以与芯片引脚电连接；电路引脚和连接通孔对接，电路引脚至少部分位于连接通孔的第一开口附近、或第二开口附近、或连接通孔内壁的附近，使得导电层可以与电路引脚电连接；芯片可以是芯片或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片可以通过连接通孔、导电层固定于所述基板，也可以是，芯片通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板。
如此，可以降低集成电路封装的成本、节约封装时间，进一步的，可以在很大面积的大面板上同时安装多个芯片，大面板上的批量处理进一步减低成本、节约封装时间。并且，降低基板和芯片构成的整体的厚度，甚至基板和芯片之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板与芯片设置其他材料)；不需要进行加热焊接的步骤，特别是针对超薄的基板、柔性电路板的封装，避免高温下基板发生翘曲、降低性能。另一方面，传统的电子封装采用导线实现芯片与基板电路层的电连接，而导线占用巨大空间，本发明通过在基板上开设连接通孔的方式实现芯片与电路层的电连接，导电层设于连接通孔内，不占用额外空间，可以小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)电路层设有电路引脚，基板设有连接通孔，连接通孔与电路引脚对接；将芯片安放于基板的顶面，使芯片的芯片引脚与连接通孔的第一开口对接；通过连接通孔的第二开口在连接通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接；
或者(2)，电路层设有电路引脚，将芯片安放于基板的顶面，使芯片的芯片引脚朝向基板，在基板上制作连接通孔，使连接通孔与电路引脚对接、并且连接通孔的第一开口与芯片引脚对接，通过连接通孔的第二开口在连接通孔内制作导电层，使导电层将芯片引脚与电路引脚电连接。
10、绝缘补丁所占区域的面积小于电路层所占区域的面积。绝缘补丁、以及其上的精细连线构成一个精细连接区域，根据需要，可以在两个芯片之间设置一个或两个以上的精细连接区域，也可以一个芯片通过两个以上的精细连接区域同时与另外两个以上的芯片电连接；并且，设置精细连接区域不需要对原有电路层做出改动，精细连接区域运用灵活，按需设置，降低成本。
11、集成电路封装方法，还包括：在基板上设置导体层，在导体层上设置绝缘补丁，在绝缘补丁上设置导体膜，导体层的厚度大于导体膜的厚度，在导体层和导体膜上设置抗蚀剂，抗蚀剂设有连线图案，采用化学蚀刻方法，按照连线图案将导体层蚀刻成电路层、将导体膜蚀刻成精细连线。可以统一在导体层和导体膜上都设置好抗蚀剂后，统一进行化学蚀刻，按照连线图案将电路层和精细连线统一成型，节约步骤、提高效率、降低生产成本，并且可以对多基板上的所有电路层、导体膜同时进行，利于批量生产，进一步降低成本。此外，导体膜的厚度与精细连线的厚度相当，导体层的厚度于电路层的厚度相当，例如当精细连线的厚度小于电路层的厚度时，导体膜的厚度小于导体层的厚度。
16、在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在在所述连线槽内和光刻胶表面制作导体膜，剥离光刻胶，在所述连线槽内形成所述精细连线。采用晶体生长的方式可以获得更精细的精细连线、获得更多的连接点，进一步提高芯片功能。晶体生长的方式是指将导电材料附着于连线槽内形成精细连线的方式，包括但不限于：电镀、溅镀、蒸镀。
17、在载体上制作绝缘补丁，在绝缘补丁上制作精细连线，将绝缘补丁连同精细连线转移至基板，将精细连线固定于基板。这种制作方式，可以完全分离精细连线和一般连线的制作工艺，可以回避不同线宽线距的连线混合制作时的各种困难，譬如，为达到不同的成线精度，可能需要不同的抗蚀膜材料和厚度；因为需要在一次光刻和蚀刻过程中同时实现较宽的一般连线和较细的精细连线，需要在不同高度上同时成像光刻不同精度的图案，可能因此一般连线的制作也须使用更昂贵的光刻设备，也可能影响产能效率。此外，采用单独制作绝缘补丁后再转移粘贴至基板的方式，不需要对原有的电路层做改动，便于对旧的集成电路进行改造升级。可以直接将精细连线固定于基板；也可以是，将精细连线固定于绝缘补丁，将绝缘补丁固定于基板，通过绝缘补丁将精细连线固定于基板。
18、在芯片与精细引脚之间设置连接介质，连接介质包括绝缘介质、以及分布于绝缘介质内的至少一个精细导电颗粒；精细连线与精细引脚之间的间距小于或等于精细导电颗粒的高度，芯片安放于基板时，精细导电颗粒的一端与精细引脚电连接、另一端与精细连线电连接，精细引脚和精细连线通过精细导电颗粒电连接；芯片引脚与精细连线之间的间距大于精细导电颗粒的高度，芯片引脚和精细连线不能通过导电颗粒电连接。
封装时，将绝缘介质设置在芯片与精细引脚之间，将芯片挤向绝缘补丁达到预设位置，由于精细引脚与精细连线之间的间距小于或等于精细导电颗粒的高度，精细导电颗粒受挤压，一端与精细引脚电连接、另一端与精细连线电连接，从而将精细引脚和精细连线电连接；芯片引脚与精细连线之间的间距大于精细导电颗粒的高度，在芯片引脚与精细连线之间的精细导电颗粒不能同时接触芯片引脚和精细连线，所以精细导电颗粒不能将芯片引脚和精细连线电连接。
精细引脚与精细连线之间设有连接介质，还包括以下情况：除了精细引脚所处区域附近，芯片的其他部分与精细连线之间也设有连接介质，芯片引脚与电路层之间的间距大于精细导电颗粒的高度，在芯片引脚与电路层之间的精细导电颗粒不能同时接触芯片引脚和精细连线，所以精细导电颗粒不能将芯片引脚和精细连线电连接。
还可以是，连接介质具有粘贴属性，可以将芯片粘贴于基板上，封装时，将绝缘介质设置在芯片与精细引脚之间，将芯片挤向绝缘补丁达到预设位置，芯片给粘贴于基板、同时精细引脚和精细连线的电连接，制作工艺简单、效率高。
附图说明
图1为本发明实施例集成电路封装结构及方法示意图一；
图2为本发明实施例集成电路封装结构及方法示意图二；
图3为本发明实施例集成电路封装结构及方法示意图三；
图4为本发明实施例集成电路封装结构及方法示意图四；
图5为本发明实施例集成电路封装结构及方法示意图五；
图6为本发明实施例集成电路封装结构示意图一；
图7为本发明实施例集成电路封装结构示意图二。
附图标记说明：
100、基板，101、导体层，102、附加导体层，110、电路层，120、附加电路层，130、连接通孔，140、外接端口，200、绝缘补丁，201、导体膜，210、精细连线，300、抗蚀剂，400、芯片，410、芯片引脚，420、精细引脚，500、导电层，610、精细导电颗粒，620、绝缘介质。
具体实施方式
下面对本发明作进一步详细说明，但本发明的实施方式不限于此。
实施例一
如图5所示，并参照图1至4，集成电路封装结构包括：基板100，基板100设有电路层110以及精细连线210；芯片400，芯片400设有精细引脚420、以及芯片引脚410；基板100设有至少两个芯片400，至少一个芯片400的芯片引脚410与电路层110电连接，电路层110上设有绝缘补丁200，绝缘补丁200上设有精细连线210，芯片400的精细引脚420与精细连线210电连接、至少两个芯片400通过精细连线210直接电连接。芯片400与电路层110电连接，芯片400可以与电路层110上连接的其他电子元器件进行通讯或能量交换，芯片400与芯片400通过精细连线210直接连接，不受电路层110的干扰、不受电路层110上连接的其他电子元件的干扰，并且精细连线210细小，芯片400之间可以获得跟多的数据传输通道，传输速度快、带宽大。绝缘补丁200将精细连线210与电路层110绝缘隔开，避免电路层110对精细连线210产生干扰。对要求高速度、款带宽的两个芯片400之间的通讯，采用精细连线210的方式，提高芯片400之间的传输性能，对不要求高速度、款带宽的两个芯片400之间的通讯，可以通过电路层110连接，降低制作成本。另一方面，采用设置绝缘补丁200的方式，可以统一制作电路层110，统一在预定位置设置绝缘补丁200和精细连线210，可以批量流水作业，降低生产成本。
如图5所示，精细引脚420设于芯片400的边沿附近，绝缘补丁200、精细连线210横跨两个芯片400之间。绝缘补丁200所占区域的面积小于电路层110所占区域的面积。绝缘补丁200、以及其上的精细连线210构成一个精细连接区域，根据需要，可以在两个芯片400之间设置一个或两个以上的精细连接区域，也可以一个芯片400通过两个以上的精细连接区域同时与另外两个以上的芯片400电连接；并且，设置精细连接区域不需要对原有电路层110做出改动，精细连接区域运用灵活，按需设置，降低成本。绝缘补丁200所占区域的面积可以参照图5所示从上往下俯视时，绝缘补丁200在基板100上占据的面积、电路层110在基板100上占据的面积。
精细连线210的宽度，指的是精细连线210横截面在绝缘补丁200上的边长，精细连线210的宽度小于电路层110的连线的宽度，精细连线210的宽度越小，在同样的空间可以获得越多的连接点，有利于提高数据传输速度和带宽。本实施例中，精细连线210的宽度为0.1微米至2微米、或1微米至5微米，可以根据需要选择。优选的，精细连线210的宽度可以选择为0.1微米、0.2微米、0.5微米、0.7微米、1微米、1.2微米、1.5微米、1.7微米、2微米、2.5微米、3微米、3.5微米、4微米、4.5微米、或5微米。
如图5所示，芯片引脚410与精细引脚420之间设有连接介质，连接介质包括绝缘介质620、以及分布于绝缘介质620内的至少一个精细导电通道，绝缘介质620使芯片400与精细引脚420绝缘地隔开，避免干扰，精细引脚420通过精细导电通道与精细引脚420电连接。精细导电通道的形式包括但不限于：在绝缘介质620中设置导电颗粒或焊块构成精细导电通道；绝缘介质620设有精细导电孔，在精细导电孔的内壁上设置导电材料层构成精细导电通道，例如硅通孔；在精细引脚420或/和精细连线210上设置导电性的凸点，导电性，导电性的凸点构成精细导电通道。
集成电路封装结构还包括有封装层，封装层未在图中示出，芯片400、精细连线210、以及绝缘补丁200位于封装层与基板100之间，封装层将芯片400以及绝缘补丁200封装与基板100。封装层可以保护芯片400、绝缘补丁200、精细连线210不被损坏，减少外部环境因素对芯片性能的影响和干扰，保障芯片400的工作性能。
芯片400上设有散热装置。使用绝缘补丁可能会增加芯片400向基板方向散热的难度，热阻抗增大，而且芯片400之间的通讯采用高带宽高速度的精细连线，芯片400运算速率高、发热也增大，在芯片400上(背向基板的一面)加装散热装置，有利于芯片400从背面的散热装置方向散热，不只依靠从基板100方向的散热通道，这样，芯片400就可以在更高的运算速度下正常工作。这种结构上的设计，一方面提高芯片400之间的数据通讯带宽和速度、一方面保证芯片400可以在更高的运算速度下正常工作，从而大幅提高***整体的运算性能。散热装置也被封装层封装于基板100上，散热装置的顶面可以从封装层中露出散热，也可以不露出。
如图7所示，基板100设有连接通孔130，连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，连接通孔130的第二开口为操作窗口，连接通孔130内设有导电层500，导电层500将芯片引脚410和电路引脚电连接。电路层110具有电路引脚，可以预先在基板100制作好电路层110，也可以在集成电路封装时再在基板100上制作电路层110，电路引脚可以是电路层110直接引出的连接部，也可以是和连接部电连接的扩展引脚，只要通过电路引脚能够和电路层110电连接均可。将芯片400安放于基板100，可以将芯片400固定于基板100上，也可以不固定。芯片400与基板100相对设置，芯片400朝向基板100的一面具有芯片引脚410，芯片400的芯片引脚410包括但不限于芯片400内部引出的连接部、与连接部电连接的扩展脚，只要通过芯片引脚410能够和芯片400电连接均可。在基板100上制作连接通孔130，使芯片引脚410与连接通孔130的第一开口对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，导电层500将芯片引脚410与电路引脚电连接；芯片引脚410位于基板100的顶面，通过连接通孔130的第二开口，可以从基板100的底面将芯片400与电路层110电连接，避免芯片400将芯片引脚410挡住；其中，连接通孔130与芯片引脚410对接，电路引脚至少部分位于连接通孔130的第一开口附近、或深入连接通孔130内，使得导电层500可以与芯片引脚410电连接；电路引脚和连接通孔130对接，电路引脚至少部分位于连接通孔130的第一开口附近、或第二开口附近、或连接通孔130内壁的附近，使得导电层500可以与电路引脚电连接；芯片400可以是芯片400或者电子元件(包括但不限于电阻、电容)或者其他电子器件(包括但不限于天线)。芯片400可以通过连接通孔130、导电层500固定于基板100，也可以是，芯片400通过其他方式(包括但不限于粘贴、模压塑料包封)固定于基板100。如此，可以降低集成电路封装的成本、节约封装时间，进一步地，可以在很大面积的大面板上同时安装多个芯片400，大面板上的批量处理进一步减低成本、节约封装时间。并且，降低基板100和芯片400构成的整体的厚度，甚至基板100和芯片400之间不需要预留间隙(原则上无需预留间隙，但是根据需要可以在基板100与芯片400设置其他材料)；连接通孔130的制作可以选择使用不需要加热焊接的工艺流程，因此可以避免高温热循环时各种热机械应力分布对超薄芯片和柔性电路板的机构和性能的损伤。这对使用超薄、柔性的电路板的封装工艺很有帮助。另一方面，在传统的引线键合封装技术中，采用导线来实现芯片400与基板100上电路的电连接，而导线要相互避开，于是占用空间较大，本发明通过在基板100上开设连接通孔130的方式实现芯片与附加电路层120的电连接，导电层500设于连接通孔130内，不占用额外空间，可以缩小封装后整体的体积，特别是，对于超薄电路板能很好的保持轻薄的特性，对于柔性电路板，能很好保持其柔性。
优选的，包括但不限于下述两种制作方法：
(1)电路层110设有电路引脚，基板100设有连接通孔130，连接通孔130与电路引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与连接通孔130的第一开口对接；通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接；
或者(2)，电路层110设有电路引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作连接通孔130，使连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
本实施例中，如图7所示，连接通孔130同时也是附加通孔，基板100底面和基板100内设有分别附加电路层120，附加电路层120设有附加引脚，附加通孔(连接通孔130)与附加引脚对接、并且附加通孔(连接通孔130)的第一开口与芯片引脚410对接，附加通孔(连接通孔130)的第二开口为操作窗口，附加通孔(连接通孔130)内设有附加导电层500，附加导电层500将芯片引脚410和附加引脚电连接。并且，在所述基板100的底面设置外接端口140，使所述外接端口140与至少一个所述导电层500电连接。外接端口140可以与另外的电子元件进行连接，扩展整个集成电路的功能，也可以用于连接电源，由电源直接对芯片400供电。
基板100可以是普通线路板、也可以是柔性电路板，还可以是基板100包括至少两层层叠设置的柔性电路板。使用多层电路板及其内含的多层电路，可以提供更多布线的可能，提高芯片400的使用性能；使用柔性轻薄的电路板，降低***整体的重量、减小体积和厚度尺寸，在适当的***设计和封装层材料的选择下，可以使***整体在封装集成之后仍然具有足够的柔性，可以用于可穿戴产品。并且，采用绝缘补丁200的方式，精细连线210本身的厚度很小，绝缘补丁200只要满足将精细连线210与基板100其它区域绝缘就可以，也不需要很厚的厚度，这有助于***整体保持柔性和薄度。精细连线210的厚度是指精细连线210的横截面垂直于绝缘补丁200的边长，绝缘补丁200的厚度是指绝缘补丁200的横截面垂直于基板100的边长。精细连线210的厚度是指精细连线210的横截面垂直于绝缘补丁200的边长，绝缘补丁200的厚度是指绝缘补丁200的横截面垂直于基板100的边长。
本实施例中，集成电路封装方法主要包括：基板100预设有电路层110，在基板100设置绝缘补丁200，在绝缘补丁200上制作精细连线210，将至少两个芯片400设置于基板100，芯片400设有精细引脚420、以及芯片引脚410，将芯片引脚410与电路层110电连接，将精细引脚420与精细连线210电连接，使至少两个芯片400通过精细连线210直接连接。
当通过连接通孔130的方式进行连接时，还包括步骤：电路层110预设有电路引脚，基板100预设有连接通孔130，连接通孔130与电路引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与连接通孔130的第一开口对接；通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接；或者，电路层110预设有电路引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作连接通孔130，使连接通孔130与电路引脚对接、并且连接通孔130的第一开口与芯片引脚410对接，通过连接通孔130的第二开口在连接通孔130内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
当通过附加通孔的方式进行连接时，还包括步骤：基板100底面或/和基板100内预设有附加电路层120，附加电路层120预设有附加引脚，基板100预设有附加通孔，附加通孔与附加引脚对接；将芯片400安放于基板100的顶面，使芯片400的芯片引脚410与附加通孔的第一开口对接；通过附加通孔的第二开口在附加通孔内制作附加导电层500，使附加导电层500将芯片引脚410与附加引脚电连接；或者，附加电路层120预设有附加引脚，将芯片400安放于基板100的顶面，使芯片400的芯片引脚410朝向基板100，在基板100上制作附加通孔，使附加通孔与附加引脚对接、并且附加通孔的第一开口与芯片引脚410对接，通过附加通孔的第二开口在附加通孔内制作导电层500，使导电层500将芯片引脚410与电路引脚电连接。
集成电路封装方法还包括将芯片400封装：在基板100设置封装层，芯片400、绝缘补丁200、以及精细连线210位于封装层与基板100之间，封装层将芯片400、绝缘补丁200、以及精细连线210包裹封装。封装后，将基板100、芯片400、封装层、绝缘补丁200、精细连线210等组成的***整体进行裁剪，根据预设的功能、大小等参数裁剪为若干小的***单元，这样统一在基板100上安装芯片400并封装好，之后再裁剪为合适大小的***单元，可以大幅提高生产效率，降低成本。
实施例二
实施例二与实施例一的区别在于：
如图1至5所示，在基板100上不预设电路层110，而在制作精细连线210时同时制作电路层110，具体制作方法为：在基板100上设置导体层101、附加导体层102，在导体层101上设置绝缘补丁200，在绝缘补丁200上设置导体膜201，导体层101的厚度远大于导体膜201的厚度，在导体层101、附加导体层102和导体膜201上设置抗蚀剂300，在抗蚀剂300中设置连线图案，采用化学蚀刻方法，按照连线图案将导体层101蚀刻成电路层110、将导体膜201蚀刻成精细连线210。可以统一在导体层101、附加导体层102和导体膜201上都设置好抗蚀剂300后，统一进行化学蚀刻，按照连线图案将电路层110、附加电路层120和精细连线210统一成型，节约步骤、提高效率、降低生产成本，并且可以对多基板100上的所有电路层110、附加导体层102、以及导体膜201同时进行，利于批量生产，进一步降低成本。此外，导体膜201的厚度与精细连线210的厚度相当，导体层101的厚度与电路层110的厚度相当，例如当精细连线210的厚度远小于电路层110的厚度时，导体膜201的厚度需要远小于导体层101的厚度。
实施例三
实施例三与实施例一的区别在于：
绝缘补丁200、精细连线210的制作方法为：基板100上预设电路层110，在电路层110上设置绝缘补丁200，在绝缘补丁200上设置光刻胶，在所述光刻胶制作连线槽，在所述连线槽内和光刻胶表面生长导体膜，剥离光刻胶，就在所述连线槽内形成所述精细连线210。
实施例四
实施例四与实施例一的区别在于：
绝缘补丁200、精细连线210的制作方法为：在载体上制作可剥离层、绝缘补丁200，在绝缘补丁200上制作精细连线210，将绝缘补丁200连同精细连线210转移至基板100，将精细连线210固定于基板100。例如，可以将绝缘补丁200、精细连线210翻转至另一个载体上，另一载体将将绝缘补丁200、精细连线210再次翻转至基板上，使精细连线210朝上，将精细连线210和其下的绝缘补丁200一起固定于基板100。
实施例五
实施例五与实施例一的区别在于：
如图6所示，实现将精细引脚420和精细连线210电连接的方法为：在芯片400与精细引脚420之间设置连接介质，连接介质包括绝缘介质620、以及分布于绝缘介质620内的至少一个精细导电颗粒610，精细导电颗粒610相互之间被绝缘介质620保持绝缘，芯片引脚410与精细引脚420之间的间距小于或等于精细导电颗粒610的高度，所述芯片400上精细引脚420与所述绝缘补丁200上的精细连线210之间间距小，精细导电颗粒610分布密度高，芯片400安放于基板100，精细导电颗粒610的一端与精细引脚420电连接、另一端与精细连线210电连接，形成至少一条由精细导电颗粒610构成的导电通道；芯片引脚410与电路层110之间的间距大于精细导电颗粒610的高度，所述芯片引脚410与电路层110之间的间距大，精细导电颗粒610分布密度低，芯片引脚410和电路层110不能通过导电颗粒电连接，不能形成任何由所述精细导电颗粒610构成的导电通道，所述芯片引脚410和所述电路层110之间保持电绝缘。将绝缘介质620设置在芯片400与精细引脚420之间，将芯片400挤向绝缘补丁200达到预设位置，由于芯片引脚410与精细引脚420之间的间距小于或等于精细导电颗粒610的高度，精细导电颗粒610受挤压，一端与精细引脚420电连接、另一端与精细连线210电连接，从而将精细引脚420和精细连线210电连接；芯片引脚410与电路层110之间的间距大于精细导电颗粒610的高度，在芯片引脚410与电路层110之间的精细导电颗粒610不能同时接触芯片引脚410和精细连线210，所以精细导电颗粒610不能将芯片引脚410和精细连线210电连接。这种连接方式，将芯片400安放于绝缘补丁200的过程就实现了精细引脚420和精细连线210的电连接，工艺简单、效率高。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

1.一种集成电路封装方法，其特征在于，包括：基板设有电路层，在所述基板设置绝缘补丁，在所述绝缘补丁上制作精细连线，将至少两个芯片设置于所述基板，所述芯片设有精细引脚、以及芯片引脚，将所述芯片引脚与所述电路层电连接，将所述精细引脚与所述精细连线电连接，使至少两个芯片通过所述精细连线直接连接；
所述芯片与所述精细连线之间设置连接介质，所述连接介质包括绝缘介质、以及分布于所述绝缘介质内的至少一个精细导电颗粒；所述精细引脚与所述精细连线之间的间距小于或等于所述精细导电颗粒的高度，所述精细导电颗粒的一端与所述精细引脚电连接、另一端与所述精细连线电连接；所述芯片引脚与所述精细连线之间的间距大于所述精细导电颗粒的高度，所述芯片引脚和所述精细连线不能通过所述导电颗粒电连接。
2.根据权利要求1所述的集成电路封装方法，其特征在于，包括： 所述电路层设有电路引脚，所述基板设有连接通孔，所述连接通孔与所述电路引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述连接通孔的第一开口对接；通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接； 或者，所述电路层设有电路引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作连接通孔，使所述连接通孔与所述电路引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，通过所述连接通孔的第二开口在所述连接通孔内制作导电层，使所述导电层将所述芯片引脚与所述电路引脚电连接。
3.根据权利要求2所述的集成电路封装方法，其特征在于，包括： 所述基板底面或/和所述基板内设有附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接；将芯片安放于所述基板的顶面，使所述芯片的芯片引脚与所述附加通孔的第一开口 对接；通过所述附加通孔的第二开口在所述附加通孔内制作附加导电层，使所述附加导电层将所述芯片引脚与所述附加引脚电连接； 或者，所述附加电路层设有附加引脚，将所述芯片安放于所述基板的顶面，使所述芯片的芯片引脚朝向所述基板，在所述基板上制作附加通孔，使所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，通过所述附加通孔的第二开口在所述附加通孔内制作导电层，使所述导电层将所述芯片引脚与所述附加引脚电连接。
4.根据权利要求2所述的集成电路封装方法，其特征在于，还包括：在所述基板设置封装层，所述芯片、所述绝缘补丁、以及所述精细引脚位于所述封装层与所述基板之间，所述封装层将所述芯片、所述绝缘补丁、以及所述精细引脚包裹封装。
5.根据权利要求2至4任一项所述的集成电路封装方法，其特征在于，在所述基板上设置导体层，在所述导体层上设置所述绝缘补丁，在所述绝缘补丁上设置导体膜，所述导体层的厚度大于所述导体膜的厚度，在所述导体层和导体膜上设置抗蚀剂，所述抗蚀剂设有连线图案，采用化学蚀刻方法，按照所述连线图案将所述导体层蚀刻成所述电路层、将所述导体膜蚀刻成所述精细连线。
6.根据权利要求2至4任一项所述的集成电路封装方法，其特征他在于，在所述基板上设有所述电路层，在所述电路层上设置所述绝缘补丁，在所述绝缘补丁上设置光刻胶，在所述光刻胶制作连线槽，采用晶体生长的方式在在所述连线槽内和光刻胶表面制作导体膜，剥离光刻胶，在所述连线槽内形成所述精细连线。
7.根据权利要求2至4任一项所述的集成电路封装方法，其特征他在于，在载体上制作绝缘补丁，在所述绝缘补丁上制作所述精细连线，将所述绝缘补丁连同所述精细连线转移至所述基板，将所述精细连线固定于所述基板。
8.一种集成电路封装结构，由权利要求1至7任一项所述的方法制备而成，其特征在于，包括： 基板，所述基板设有电路层以及精细连线； 芯片，所述芯片设有精细引脚、以及芯片引脚； 所述基板设有至少两个所述芯片，至少一个所述芯片的所述芯片引脚与所述电路层电连接，所述电路层上设有绝缘补丁，所述绝缘补丁上设有精细连线，所述芯片的精细引脚与所述精细连线电连接、至少两个所述芯片通过所述精细连线直接电连接；
在至少两个所述芯片与所述精细连线之间设置连接介质，所述连接介质包括绝缘介质以及分布于绝缘介质内的至少一个精细导电颗粒，所述精细导电颗粒的一端与所述精细引脚电连接、另一端与所述精细连线电连接。
9.根据权利要求8所述的集成电路封装结构，其特征在于，所述精细连线的宽度为0.1微米至5微米。
10.根据权利要求8所述的集成电路封装结构，其特征在于，在所述芯片的上设有散热装置。
11.根据权利要求8所述的集成电路封装结构，其特征在于，还包括有封装层，所述芯片、所述精细连线、以及所述绝缘补丁位于所述封装层与所述基板之间，所述封装层将所述芯片以及所述绝缘补丁封装与所述基板。
12.根据权利要求8所述的集成电路封装结构，其特征在于，所述基板为柔性电路板，或所述基板包括至少两层层叠设置的柔性电路板。
13.根据权利要求8至12任一项所述的集成电路封装结构，其特征在于，所述芯片位于所述基板的顶面，所述基板底面或/和所述基板内设有附加电路层，所述附加电路层设有附加引脚，所述基板设有附加通孔，所述附加通孔与所述附加引脚对接、并且所述附加通孔的第一开口与所述芯片引脚对接，所述附加通孔的第二开口为操作窗口，所述附加通孔内设有附加导电层，所述附加导电层将所述芯片引脚和所述附加引脚电连接。
14.根据权利要求13所述的集成电路封装结构，其特征在于，所述芯片引 脚为至少两个，所述附加导电层为与所述芯片引脚相应的至少两个，所述基板的底面设有外接端口，所述外接端口与至少一个所述附加导电层电连接。
15.根据权利要求8至12任一项所述的集成电路封装结构，其特征在于，所述基板设有连接通孔，所述电路层设有电路引脚，所述连接通孔与所述芯片引脚对接、并且所述连接通孔的第一开口与所述芯片引脚对接，所述连接通孔的第二开口为操作窗口，所述连接通孔内设有导电层，所述导电层将所述芯片引脚和所述电路引脚电连接。
16.根据权利要求8至12任一项所述的集成电路封装结构，其特征在于，所述绝缘补丁所占区域的面积小于所述电路层所占区域的面积。
CN201680090828.8A 2016-11-30 2016-11-30 集成电路封装结构及方法 Active CN110024113B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/107834 WO2018098650A1 (zh) 2016-11-30 2016-11-30 集成电路封装结构及方法

Publications (2)

Publication Number Publication Date
CN110024113A CN110024113A (zh) 2019-07-16
CN110024113B true CN110024113B (zh) 2023-11-24

Family

ID=62241104

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680090828.8A Active CN110024113B (zh) 2016-11-30 2016-11-30 集成电路封装结构及方法

Country Status (3)

Country Link
US (1) US11183458B2 (zh)
CN (1) CN110024113B (zh)
WO (1) WO2018098650A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108933154B (zh) * 2017-05-26 2021-04-27 京东方科技集团股份有限公司 有机发光二极管显示基板的制备方法、显示基板及显示装置
US11197384B1 (en) * 2020-06-29 2021-12-07 Quanta Computer Inc. Tool-less latch system for a node sled

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101199242A (zh) * 2005-06-16 2008-06-11 伊姆贝拉电子有限公司 电路板结构的制造方法和电路板结构
CN202210519U (zh) * 2011-10-08 2012-05-02 高庄 提高单位面积引脚量的芯片尺寸封装csp集成电路芯片
JP2012124333A (ja) * 2010-12-08 2012-06-28 Sharp Corp 半導体装置および半導体装置の製造方法
CN103369811A (zh) * 2012-03-30 2013-10-23 揖斐电株式会社 电路板及其制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831355B2 (en) * 2002-12-04 2004-12-14 Minilogic Device Corporation Ltd. Flip-chip sub-assembly, methods of making same and device including same
JP3879853B2 (ja) * 2003-10-10 2007-02-14 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
CN104471708B (zh) * 2012-02-08 2017-05-24 吉林克斯公司 具有多个***件的堆叠裸片组件
US8704364B2 (en) 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
US8946900B2 (en) * 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
US20140131854A1 (en) * 2012-11-13 2014-05-15 Lsi Corporation Multi-chip module connection by way of bridging blocks
US9236366B2 (en) * 2012-12-20 2016-01-12 Intel Corporation High density organic bridge device and method
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9070644B2 (en) * 2013-03-15 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9646894B2 (en) * 2013-03-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging mechanisms for dies with different sizes of connectors
US9595496B2 (en) * 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US10037946B2 (en) * 2016-02-05 2018-07-31 Dyi-chung Hu Package structure having embedded bonding film and manufacturing method thereof
KR102632563B1 (ko) * 2016-08-05 2024-02-02 삼성전자주식회사 반도체 패키지
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
WO2019132970A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Microelectronic assemblies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101199242A (zh) * 2005-06-16 2008-06-11 伊姆贝拉电子有限公司 电路板结构的制造方法和电路板结构
JP2012124333A (ja) * 2010-12-08 2012-06-28 Sharp Corp 半導体装置および半導体装置の製造方法
CN202210519U (zh) * 2011-10-08 2012-05-02 高庄 提高单位面积引脚量的芯片尺寸封装csp集成电路芯片
CN103369811A (zh) * 2012-03-30 2013-10-23 揖斐电株式会社 电路板及其制造方法

Also Published As

Publication number Publication date
US20190287909A1 (en) 2019-09-19
CN110024113A (zh) 2019-07-16
WO2018098650A1 (zh) 2018-06-07
US11183458B2 (en) 2021-11-23

Similar Documents

Publication Publication Date Title
US10658312B2 (en) Embedded millimeter-wave phased array module
CN105655310B (zh) 封装结构、电子设备及封装方法
CN104170076B (zh) 用于毫米波半导体裸片的电子封装
US10879197B2 (en) Package structure and method of fabricating package structure
US20060145328A1 (en) Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same
US20070053167A1 (en) Electronic circuit module and manufacturing method thereof
CN104900782A (zh) 具有隔离件的散热增益型线路板制作方法
TW201230263A (en) Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US20190348395A1 (en) Thin bonded interposer package
CN109937614B (zh) 芯片连线方法及结构
KR20100051270A (ko) 표면 장착가능한 집적회로 패키징 수단
US11587916B2 (en) Package structure and manufacturing method thereof
CN112349693B (zh) 一种采用bga接口的宽带射频***级封装结构
JP2002289995A (ja) 金属基板およびその製造方法
CN110024113B (zh) 集成电路封装结构及方法
US20140001647A1 (en) Flip-chip electronic device and production method thereof
CN103219317B (zh) 集成电路封装以及用于制造集成电路封装的方法
CN107845610B (zh) 基板结构及其制作方法
CN105140189B (zh) 板级扇出型芯片封装器件及其制备方法
CN217387150U (zh) 半导体封装结构
US20110075376A1 (en) Module substrate radiating heat from electronic component by intermediate heat transfer film and a method for manufacturing the same
WO2018098648A1 (zh) 集成电路封装方法以及集成封装电路
CN113937078A (zh) 内埋式组件结构及其制造方法
CN220569634U (zh) 高导热嵌埋结构
WO2018098651A1 (zh) 集成电路***及封装方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant