WO2024060639A1 - 一种封装体及其制备方法 - Google Patents

一种封装体及其制备方法 Download PDF

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Publication number
WO2024060639A1
WO2024060639A1 PCT/CN2023/093329 CN2023093329W WO2024060639A1 WO 2024060639 A1 WO2024060639 A1 WO 2024060639A1 CN 2023093329 W CN2023093329 W CN 2023093329W WO 2024060639 A1 WO2024060639 A1 WO 2024060639A1
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WO
WIPO (PCT)
Prior art keywords
layer
carrier board
plastic sealing
plastic
package
Prior art date
Application number
PCT/CN2023/093329
Other languages
English (en)
French (fr)
Inventor
钟仕杰
雷云
宋关强
李俞虹
江京
Original Assignee
天芯互联科技有限公司
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Filing date
Publication date
Application filed by 天芯互联科技有限公司 filed Critical 天芯互联科技有限公司
Publication of WO2024060639A1 publication Critical patent/WO2024060639A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

Definitions

  • This application is applied to the technical field of packages, especially a package and its preparation method.
  • Packaging technology is used to install the casing for semiconductor integrated circuit chips, and plays the role of placing, fixing, sealing, protecting electronic devices and enhancing electrothermal performance. It is also a bridge that communicates the internal circuits and external circuits of electronic devices.
  • This application provides a package and a preparation method thereof to solve the problem of insufficient space utilization of the package.
  • the present application provides a method for preparing a package, which includes: obtaining a processing board, which includes a carrier board with pads formed on opposite sides and affixed on opposite sides of the carrier board.
  • the first plastic encapsulation layer is set together; on the side of each first plastic encapsulation layer away from the carrier board, connectors connected to the corresponding pads are prepared, and the preset positions of each first plastic encapsulation layer are depth-controlled until the connectors are exposed cross-section to form a depth control groove; wherein the preset position partially overlaps with the connector; install the chip upright in the corresponding depth control groove, and connect the side of the chip to the connector; place each first plastic sealing layer away from the loader A second plastic sealing layer is formed on one side of the board, and the carrier board is divided into boards to obtain at least two packages.
  • the step of obtaining a processing board which includes a carrier board with pads formed on opposite sides, and a first plastic sealing layer that is attached to the opposite sides of the carrier board includes: obtaining a board with pads formed on both opposite sides.
  • a carrier board for the soldering pad perform double-sided plastic sealing on opposite sides of the carrier board for the first time to form first plastic sealing layers on opposite sides of the carrier board to obtain a processed board.
  • the welding pads include a first welding pad and a second welding pad; the first double-sided plastic sealing is performed on the opposite sides of the carrier board to form first plastic sealing layers on the opposite sides of the carrier board respectively, thereby obtaining the processing quality of the board.
  • the step include: mounting the component on the second pad.
  • the step of preparing connectors for connecting corresponding pads on the side of each first plastic packaging layer away from the carrier board includes: drilling each first plastic packaging layer based on the position of each first pad to obtain each exposed first plastic packaging layer. A blind hole of a pad; metallize each blind hole until a connector is obtained that is snugly arranged with the side of each first plastic sealing layer away from the carrier board; wherein each end of the connector extends along the corresponding blind hole Connect to the corresponding first pad.
  • the step of metallizing each blind hole until obtaining a connecting piece that is snugly arranged with the side of each first plastic sealing layer away from the carrier includes: electroplating, sputtering or evaporating the opposite sides of the processed plate. , until each blind hole is filled and a connecting piece is formed on the side of each first plastic sealing layer away from the carrier board.
  • the step of electroplating, sputtering or evaporating the opposite sides of the processed board until each blind hole is filled and forming a connector on the side of each first plastic sealing layer away from the carrier board includes: Electroplating, sputtering or evaporation is performed on the opposite sides until each blind hole is filled and the first plastic sealing layer is away from the carrier board. An electroplated metal layer is formed on one side; the electroplated metal layer is used as a connector; or the electroplated metal layer is etched to form a connector.
  • the step of forming a second plastic sealing layer on the side of each first plastic sealing layer away from the carrier board, and dividing the carrier board to obtain at least two packages includes: performing a third process on the opposite sides of the processed plate.
  • a second plastic seal layer is formed on the side of each first plastic seal layer away from the carrier board; the reinforcing sheet and the solder mask layer are sequentially pressed on the side of each second plastic seal layer away from the carrier board;
  • the carrier board is divided into boards to obtain at least two packages.
  • the carrier board includes a substrate and pads formed on opposite sides of the substrate; the substrate of the carrier board includes a conductive layer, a first dielectric layer and a conductive layer that are sequentially stacked and arranged in close contact; or the substrate of the carrier board includes a second dielectric layer , a conductive layer, a first dielectric layer, a conductive layer and a second dielectric layer; wherein a conductive hole is formed on each second dielectric layer to connect the pad of the carrier board and the corresponding conductive layer.
  • the step of dividing the carrier board to obtain at least two packages includes: removing the first dielectric layer to divide the carrier board; and etching the exposed conductive layer to obtain at least two packages.
  • the step of controlling the depth of the preset positions of each first plastic sealing layer until the cross section of the exposed connector to form a depth control groove includes: mechanically, laser or chemically controlling the preset positions of each first plastic sealing layer. Set the position for depth control until the cross section of the exposed connector is reached to form a depth control groove.
  • this application also provides a package body, including: a plastic sealing layer, a controlled depth groove is formed inside the plastic sealing layer, and a pad is formed on one side of the plastic sealing layer; a chip, the chip is accommodated upright in the controlled depth groove. Inside; the connector, one end of the connector is connected to the corresponding pad, and the other end of the connector is connected to the side of the chip to lead the electrical signal of the chip out of the package.
  • a first welding pad and a second welding pad are formed on one side of the plastic sealing layer; one end of the connector is connected to the corresponding first welding pad, and the other end of the connector is connected to the side of the chip; the second welding pad is close to the plastic sealing layer There are components installed on one side.
  • the components include one or more of chips, resistive components, power supplies, and switches.
  • a second dielectric layer is formed on one side of the plastic sealing layer, a conductive circuit is formed on the side of the second dielectric layer away from the plastic sealing layer, and a conductive hole is formed on the second dielectric layer; the conductive circuit passes through the corresponding conductive hole and the corresponding First pad or second pad connection.
  • a reinforcing sheet is attached to the side of the plastic sealing layer away from the conductive circuit.
  • solder resist layer is attached to the side of the reinforcing sheet away from the conductive circuit.
  • the plastic sealing layer includes one or more of epoxy resin, polyimide, bismaleimide triazine, and ceramic base.
  • the preparation method of the package of the present application prepares connectors on the first plastic sealing layer on both sides of the processing plate and performs local depth control based on the position of the connectors to form a depth control groove, thereby erecting the chip.
  • the ground is installed in the depth-controlled groove, and the pads on the side of the chip can be directly connected to the connectors exposed through the depth-controlled groove, thereby enabling the upright installation of the chip.
  • the upright installation of the chip can simplify the connection path of the connectors. , improve the space utilization of the package, improve the limitations of system-level packaging and board-level packaging, and expand the application scenarios of the package.
  • connector preparation, chip mounting and plastic sealing are carried out through a double-sided carrier board, so the packages can be prepared separately on opposite sides of the carrier board, which can increase the output of package preparation and thereby improve the efficiency of package preparation.
  • Figure 1 is a schematic flow diagram of an embodiment of a method for preparing a package provided by the present application
  • Figure 2 is a schematic flow diagram of another embodiment of a method for preparing a package provided by the present application
  • Figure 3 is a schematic structural diagram of an implementation of the carrier board in the embodiment of Figure 2;
  • Figure 4 is a schematic structural diagram of another embodiment of the carrier board in the embodiment of Figure 2;
  • FIG. 5 is a schematic structural diagram of an embodiment of processing the plate in step S21 of the embodiment of Figure 2;
  • Figure 6 is a schematic structural diagram of an embodiment of processing the plate in step S22 of the embodiment of Figure 2;
  • FIG. 7 is a schematic structural diagram of an embodiment of processing the plate in step S23 of the embodiment of Figure 2;
  • Figure 8 is a schematic structural diagram of an embodiment of processing the plate in step S24 of the embodiment of Figure 2;
  • Figure 9 is a schematic structural diagram of an embodiment of the package provided by this application.
  • Figure 10 is a schematic structural diagram of another embodiment of the package provided by this application.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for preparing a package provided by the present application.
  • Step S11 obtaining a processed board, wherein the processed board includes a carrier board with solder pads formed on two opposite sides and a first plastic packaging layer bonded to two opposite sides of the carrier board.
  • the processed panel is obtained, wherein the processed panel includes a carrier plate and two layers of first plastic sealing layers, and the two layers of first plastic sealing layers are respectively arranged in contact with the opposite sides of the carrier plate, that is, the carrier plate is provided with the two layers of first plastic sealing layers. Between the layers, welding pads are also formed on the opposite sides of the carrier board. When the first plastic sealing layer is placed in contact with the carrier board, it also covers the welding pads on the corresponding sides.
  • the number of pads on each side of the first molding layer may include multiple.
  • the pads on one side of the carrier board can be used to prepare one package or multiple packages, and one package or multiple packages correspond to different numbers of pads on one side of the carrier board.
  • the specific number can be based on actual needs. Settings are not limited here.
  • the first molding layer may specifically include one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic base. No limitation is made here.
  • the carrier board is used to support the preparation of the package, and its material itself may include a glass plate, a metal plate, a plastic plate, etc., which is not limited here.
  • Step S12 Prepare connectors for connecting corresponding pads on the side of each first plastic layer away from the carrier board, and control the depth of the preset positions of each first plastic layer until the cross-section of the exposed connector is formed. Depth control groove; wherein, the preset position partially overlaps the connecting piece.
  • connectors connected to corresponding pads are respectively prepared on the side of each first plastic packaging layer of the processed panels away from the carrier board.
  • the first plastic packaging layer can be drilled from the side away from the carrier board until the pad is exposed, and then the holes are metallized until a connection to the corresponding pad is formed. Connectors.
  • the depth of the first plastic packaging layer can also be controlled from the side of each first plastic packaging layer away from the carrier board until the pad is exposed, and then wires or metal parts are welded on the pad for connection. .
  • the method of preparing the connector is not limited here.
  • depth control is performed on the preset positions of each first plastic sealing layer until the cross section of the connector is exposed to form a depth control groove; wherein, the preset position partially overlaps with the connector.
  • the depth control groove is opened on the connector, that is, the depth is controlled locally based on the position of the connector until the cross section of the connector is exposed to form a depth control groove.
  • the depth-controlled groove is used to install chips.
  • this step can prepare multiple depth-controlled grooves on opposite sides of the carrier board. groove.
  • the depth control method in this step can be carried out by laser depth control or mechanical depth control, which is not limited here.
  • Step S13 Install the chip upright in the corresponding depth control groove, and connect the side of the chip to the connector.
  • the chip is installed upright in the corresponding depth control groove.
  • a chip is installed in each depth control groove. Since the pad of the chip is provided on its side, it is installed upright in the depth control groove. In the slot, the pads on the side of the chip can be directly connected to the connectors exposed through the depth-controlled slot, so that the chip can be installed upright, and the upright installation of the chip can simplify the connection path of the connectors and improve the durability of the package. Space utilization.
  • the pad on the side of the chip can be welded to the connector exposed through the depth control groove to achieve direct connection.
  • the pads on the side of the chip and the connectors exposed through the depth control groove can be directly connected through conductive adhesive bonding. No limitation is made here.
  • Step S14 Form a second plastic sealing layer on the side of each first plastic sealing layer away from the carrier board, and separate the carrier board to obtain at least two packages.
  • a second plastic sealing layer is formed on the side of each first plastic sealing layer away from the carrier board, so that the connector and the chip are plastically sealed.
  • the carrier board in this embodiment is a double-sided carrier board, and connector preparation, chip mounting, and plastic packaging are performed on each carrier board. Therefore, packages are prepared on opposite sides of the carrier board. Therefore, at least two packages are obtained by dividing the carrier board. Among them, the carrier board can also be used to prepare batch packages. After dividing the boards, the two separated boards are cut respectively to obtain multiple independent packages.
  • the output of package preparation can be increased, thereby improving the efficiency of package preparation.
  • the above-mentioned package can also expand the size of the system-level package to exceed 100*300mm to meet more application needs.
  • the package preparation method of this embodiment prepares connectors on the first plastic sealing layer on both sides of the processing plate, and performs local depth control based on the position of the connectors to form a depth control groove, thereby erecting the chip.
  • the ground is installed in the depth-controlled groove, and the pads on the side of the chip can be directly connected to the connectors exposed through the depth-controlled groove, thereby enabling the upright installation of the chip.
  • the upright installation of the chip can simplify the connection path of the connectors. , improve the space utilization of the package, improve the limitations of system-level packaging and board-level packaging, and expand the application scenarios of the package.
  • connector preparation, chip mounting and plastic sealing are carried out through a double-sided carrier board, so the packages can be prepared separately on opposite sides of the carrier board, which can increase the output of package preparation and thereby improve the efficiency of package preparation.
  • FIG. 2 is a schematic flowchart of another embodiment of a method for preparing a package provided by the present application.
  • Step S21 Obtain a carrier board with soldering pads formed on opposite sides of the carrier board; perform a first double-sided plastic sealing on the opposite sides of the carrier board to form first plastic sealing layers on opposite sides of the carrier board to obtain a processed board pieces.
  • a carrier having pads formed on opposite sides is obtained.
  • the carrier includes a substrate and pads formed on opposite sides of the substrate.
  • the number of pads on each side of the substrate can be multiple, for example: 4, 8, 11, etc., which can be set based on actual needs.
  • the substrate of the carrier board includes a conductive layer, a first dielectric layer and a conductive layer that are stacked in sequence and arranged in close contact with each other.
  • FIG. 3 is a schematic structural diagram of an implementation of the carrier board in the embodiment of FIG. 2 .
  • the carrier 100 of this embodiment includes a substrate 110 and pads 113 formed on two opposite sides of the substrate 110 .
  • the substrate 110 includes a conductive layer 112, a first dielectric layer 111 and a conductive layer 112 that are stacked in sequence and adhered to each other.
  • the number of pads 113 on each side of the substrate 110 may be multiple.
  • the carrier board 100 of this embodiment can facilitate the miniaturization and lightweight of the package.
  • the substrate of the carrier board includes a second dielectric layer, a conductive layer, a first dielectric layer, a conductive layer and a second dielectric layer; wherein conductive holes are formed on each second dielectric layer to connect The pads of the carrier board and the corresponding conductive layers.
  • FIG. 4 is a schematic structural diagram of another implementation of the carrier board in the embodiment of FIG. 2 .
  • the carrier board 200 of this embodiment includes a substrate 210 and pads 213 formed on opposite sides of the substrate 210 .
  • the substrate 210 of the carrier 200 includes a second dielectric layer 214, a conductive layer 212, a first dielectric layer 211, a conductive layer 212 and a second dielectric layer 214; wherein, a plurality of conductive holes 215 are formed on each second dielectric layer 214. to connect the pad 213 of the carrier board 200 and the corresponding conductive layer 212 .
  • the conductive structure inside the carrier board 200 of this embodiment is in an "I-shaped” or “Z-shaped” shape, which can enhance the structural stability of the package and improve the reliability of the package.
  • the pads on the carrier board may include a first pad and a second pad, where the first pad refers to the rear
  • the second pad is used to prepare connectors to connect the chip's pads; the second pad refers to the pad that is subsequently used to install components.
  • the number of the first pads and the second pads on the carrier board is determined based on the number of chips and components, and is not limited here.
  • the component before the first plastic packaging, can be installed on the second pad.
  • the pad of the component can be soldered to the corresponding second pad, or it can be The components are connected to the corresponding second pads by wire bonding.
  • Components can include any active/passive components such as chips, resistive components, power supplies, switches, etc. The specific type and quantity can be set based on actual needs.
  • the first double-sided plastic sealing is performed on the opposite sides of the carrier board at the same time to form a first plastic seal layer on the opposite sides of the carrier board to obtain a processed board.
  • the first plastic seal layer fills the space between the components and the pads. gap.
  • the first plastic sealing in this step is double-sided plastic sealing
  • force is applied to both sides of the carrier at the same time during the plastic sealing, so that the pads and the conductive layer on the carrier are subjected to balanced force during the plastic sealing process, thereby reducing the warping problem caused by the packaging body manufacturing process and improving the structural stability and reliability of the packaging body.
  • FIG. 5 is a schematic structural diagram of an embodiment of processing the plate in step S21 of the embodiment of FIG. 2 .
  • the bonding pad 213 is divided into a first bonding pad 241 and a second bonding pad 242 .
  • the number of the first bonding pads 241 and the second bonding pads 242 can also be other numbers, which are not limited here.
  • a component 220 is installed on the side of each second pad 242 away from the carrier board 200. Specifically, the component 220 can be soldered to the corresponding second pad 242 through solder paste.
  • the opposite sides of the carrier board 200 are also provided with first plastic sealing layers 230 respectively.
  • the first plastic sealing layers 230 respectively wrap the components 220 and the bonding pads 213 on the corresponding sides, and fill the space between the components 220 and the bonding pads 213. gap.
  • Step S22 Drill holes in each first plastic sealing layer based on the position of each first bonding pad to obtain blind holes that expose each first bonding pad; metallize each blind hole until a hole is obtained that is far away from each first plastic sealing layer.
  • One side of the carrier board fits the provided connector.
  • Drill holes in each first plastic encapsulation layer based on the position of each first bonding pad to obtain blind holes that expose each first bonding pad respectively. Laser drilling can be used when drilling.
  • each blind hole until a connector is obtained that is snugly arranged with the side of each first plastic sealing layer away from the carrier board.
  • the opposite sides of the processed board can be electroplated, sputtered or evaporated until the blind holes are filled and an electroplated metal layer is formed on the side of each first plastic layer away from the carrier board.
  • the electroplated metal layer can be etched to remove unwanted portions to form connections.
  • the electroplated metal layer can also be directly used as a connector to improve the heat dissipation efficiency of the package by increasing the area of the connector.
  • the middle part of the connector is attached to the side of each first plastic layer away from the carrier board, and each end thereof extends along the corresponding blind hole to the corresponding first pad for connection.
  • one connecting piece may include at least two ends, and at least one connecting piece may be provided on a side of each first plastic sealing layer away from the carrier board.
  • FIG. 6 is a schematic structural diagram of an embodiment of processing the plate in step S22 of the embodiment of FIG. 2 .
  • the processing plate 202 of this embodiment has blind holes 251 respectively prepared on the two first plastic sealing layers 230 , wherein each blind hole 251 exposes a corresponding first pad 241 .
  • a connector 260 is also disposed on the side of each first plastic layer 230 away from the first pad 241. Each end of the connector 260 extends along the corresponding blind hole 251 to the corresponding first pad 241 for connection.
  • Step S23 Control the depth of the preset positions of each first plastic sealing layer until the cross-section of the exposed connector is exposed to form a depth-control groove; install the chip upright in the corresponding depth-control groove, and connect the side of the chip to the depth-control groove. parts connection.
  • the preset positions of each first plastic sealing layer are respectively depth-controlled until the cross-section of the exposed connector is formed to form a depth-controlled groove, wherein the preset positions partially overlap with the connector.
  • the depth of the depth-controlled groove can be controlled mechanically, laserly or chemically.
  • the depth control groove is opened on the connector, that is, the depth is controlled locally based on the position of the connector until the cross section of the connector is exposed to form a depth control groove.
  • the groove wall of the depth control groove is formed by the connecting piece and the first plastic sealing layer.
  • the depth-controlled grooves are used to install chips.
  • one side of the carrier is used to prepare multiple packages and/or multiple chips need to be installed on one package, multiple depth-controlled grooves are prepared on opposite sides of the carrier in this step.
  • the chip After the chip is installed, the chip can be electrically connected to the connector, the first pad, the conductive layer, the second pad and the components in sequence.
  • FIG. 7 is a schematic structural diagram of an embodiment of processing the plate in step S23 of the embodiment of FIG. 2 .
  • the processing plate 203 of this embodiment has at least one depth control groove (not labeled in the figure) opened on each first plastic sealing layer 230 , and the chip 270 is installed upright in the depth control groove.
  • the inner wall of the depth control groove is composed of the connector 260 and the first plastic sealing layer 230.
  • the pad of the chip 270 is formed on the side of the chip 270 and is connected to the connector 260 on the inner wall of the depth control groove.
  • the chip 270 may be provided with pads on both opposite sides thereof, so as to be connected to the two sides of the connector 260 controlled for deep disconnection respectively.
  • the chip 270 may be provided with pads on only one side, which are connected to one side of the connector 260 that is controlled for deep disconnection.
  • the chip 270 can be welded and fixed to the connector 260 .
  • the pads on the side of the chip 270 can be directly connected to the connector 260 exposed through the depth control groove, so that the chip 270 can be installed upright, and the chip 270 can be upright.
  • the installation can simplify the connection path of the connector 260 and improve the space utilization of the package.
  • Step S24 Perform a second double-sided plastic sealing on the opposite sides of the processed plate, and form a second plastic sealing layer on the side of each first plastic sealing layer away from the carrier plate; Press in turn Strengthen the sheet and coat the solder mask; separate the carrier board to obtain at least two packages.
  • a second double-sided plastic sealing is performed on the opposite sides of the processing board, and a second plastic sealing layer is formed on the side of each first plastic sealing layer away from the carrier board.
  • the second plastic encapsulation layer covers the chip and the connector.
  • the second molding layer may specifically include one or more of epoxy resin, polyimide, bismaleimide triazine (BT), and ceramic base. No limitation is made here.
  • the second plastic sealing in this step is double-sided plastic sealing, force is applied to both sides of the processed plate at the same time during plastic sealing, so that the connectors on the processed plate are balanced in force during the plastic sealing process, thereby reducing the The problem of warpage caused during the manufacturing process of the package is eliminated, and the structural stability and reliability of the package are improved.
  • the first plastic sealing and the second plastic sealing are both double-sided plastic sealing, which can improve the balance during the production process of the package and reduce the problem of uneven stress during the production process of the package.
  • the first molding layer and the second molding layer can form an integral molding layer.
  • the reinforcement sheets and solder resist layers are sequentially pressed on the side of each second plastic seal layer away from the carrier board to improve the structural rigidity of the package through the reinforcement sheets, enhance structural stability, and pass the solder resist
  • the layer improves the insulation on the surface of the package and reduces short circuits with other devices.
  • the solder mask layer may include insulating substances such as ink.
  • FIG. 8 is a schematic structural diagram of an embodiment of processing the plate in step S24 of the embodiment of FIG. 2 .
  • the processing panel 204 of this embodiment has a second plastic layer 280 attached to the side of each first plastic layer 230 away from the carrier plate 200 , and each second plastic layer 280 covers the corresponding The chip 270 and the connector 260 on the side.
  • the reinforcing sheet 291 is attached to the side of the second plastic sealing layer 280 away from the carrier board 200 , and the solder resist layer 292 is attached to the side of the reinforcing sheet 291 away from the carrier board 200 .
  • the carrier board into at least two packages. Specifically, the first dielectric layer of the carrier board is removed to separate the carrier board, and the exposed conductive layer after the separation is patterned and etched to form conductive lines to obtain at least two packages.
  • the specific shape of the conductive line can be set based on actual conditions and is not limited here.
  • the surface of the package After the surface of the package is coated with a protective layer, it can be put into storage.
  • the carrier board when used to prepare batch packages, after splitting, the carrier board can be cut to obtain multiple independent packages.
  • the package preparation method of this embodiment prepares connectors on the first plastic sealing layer on both sides of the processing plate and performs local depth control based on the position of the connectors to form a depth control groove, thereby placing the chip upright.
  • Installed in the depth-controlled groove the pads on the side of the chip can be directly connected to the connector exposed through the depth-controlled groove, thereby enabling the upright installation of the chip.
  • the upright installation of the chip can simplify the connection path of the connector. Improve the space utilization of the package.
  • connector preparation, chip mounting and plastic sealing are carried out through a double-sided carrier board, so the packages can be prepared separately on opposite sides of the carrier board, which can increase the output of package preparation and thereby improve the efficiency of package preparation.
  • first plastic sealing and the second plastic sealing in this embodiment are both double-sided plastic sealing, which can improve the balance during the production of the package, reduce the problem of uneven stress during the production of the package, and reduce the occurrence of problems during the production of the package. eliminate the warping problem and improve the structural stability and reliability of the package.
  • FIG. 9 is a schematic structural diagram of an embodiment of a package provided by the present application.
  • the package 900 of this embodiment includes a plastic sealing layer 980 , a chip 970 and a connector 960 .
  • a controlled-depth groove (not marked in the figure) is formed inside the plastic sealing layer 980 , and a bonding pad 940 is formed on one side of the plastic sealing layer 980 .
  • the chip 970 is placed upright in the depth control groove.
  • the number of chips 970 and connectors 960 may be one or more, which is not limited here.
  • One end of the connector 960 is connected to the corresponding pad 940 , and the other end of the connector 960 is connected to the side of the chip 970 to lead the electrical signal of the chip 970 out of the package 900 .
  • one end of a connector 960 is connected to the corresponding pad 940 , and the other end of the connector 960 is connected to the pad on the side of the chip 970 .
  • one end of the two connectors 960 is connected to the corresponding pad 940, and the other end of the two connectors 960 is connected to the pads on opposite sides of the chip 970.
  • the package of this embodiment can realize the upright installation of the chip through the cooperative arrangement of the connector and the depth control groove, thereby simplifying the connection path of the connector and improving the space utilization of the package.
  • a first bonding pad 941 and a second bonding pad 942 are formed on one side of the plastic sealing layer 980 , that is, the bonding pad 940 includes the first bonding pad 941 and the second bonding pad 942 .
  • the first bonding pad 941 refers to the bonding pad 940 that is connected to the chip 970 through the connector 960; the second bonding pad 942 refers to the bonding pad 940 used to install the component 920.
  • One end of the connector 960 is connected to the corresponding first pad 941 , and the other end of the connector 960 is connected to the side surface of the chip 970 .
  • the component 920 is installed on the side of the second pad 942 close to the plastic sealing layer 980 .
  • a second dielectric layer 914 is formed on one side of the plastic layer 980 , a conductive circuit 990 is formed on a side of the second dielectric layer 914 away from the plastic layer 980 , and a conductive hole 915 is formed on the second dielectric layer 914 .
  • the conductive trace 990 is connected to the corresponding first pad 941 or the second pad 942 through the corresponding conductive hole 915 .
  • the component 920 can be connected to the outside through the second pad 942, the conductive hole 915 and the conductive line 990 in sequence.
  • the chip 970 can be connected to the outside through the connector 960, the first pad 941, the conductive hole 915 and the conductive line 990 in sequence.
  • the package 900 of this embodiment can be prepared based on the carrier board in the embodiment of FIG. 4 .
  • the package 900 of this embodiment can enhance the structural stability of the package and improve the reliability of the package.
  • the conductive circuit 990 may include an external pad connected to the pad 940 and a circuit connecting the external pads.
  • a reinforcing sheet 991 can be disposed on the side of the plastic encapsulation layer 980 away from the conductive lines 990 to improve the structural rigidity of the package 900 .
  • a solder resist layer 992 can be disposed on the side of the reinforcing sheet 991 away from the conductive trace 990 to enhance the surface insulation of the package 900 .
  • FIG. 10 is a schematic structural diagram of another embodiment of the package provided by the present application.
  • the positions of the reinforcing sheet, solder resist layer, chip 1070, connector 1060, plastic sealing layer 1080, component 1020, soldering pad 1040, first soldering pad 1041, and second soldering pad 1042 of the package 1000 of this embodiment are The connection relationships are the same as those in the previous embodiments. Please refer to the above and will not be described again.
  • one side of the plastic sealing layer 1080 is provided with a conductive line 1015.
  • the conductive line 1015 Connected to at least part of the first pad 1041 and/or the second pad 1042 . Therefore, the component 1020 can be connected to the outside through the second pad 1042 and the conductive line 990 in sequence.
  • the chip 1070 can be connected to the outside through the connector 1060, the first pad 1041 and the conductive line 990 in sequence.
  • the conductive lines 1090 may include external pads connected to the pads 1040 and lines connecting the external pads.
  • the package 1000 of this embodiment is convenient for achieving miniaturization and lightness.
  • the package 1000 of this embodiment can be prepared based on the carrier board in the embodiment of FIG. 3 .

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Abstract

本申请公开了一种封装体及其制备方法，其中，封装体的制备方法包括：获取到加工板件，加工板件包括相对两侧形成有焊盘的载板以及分别在载板的相对两侧贴合设置的第一塑封层；在各第一塑封层远离载板的一侧分别制备连接对应焊盘的连接件，并分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽；其中，预设位置与连接件部分重叠；将芯片直立安装于对应的控深槽内，并使芯片的侧面与连接件连接；在各第一塑封层远离载板的一侧分别形成第二塑封层，并对载板进行分板，以得到至少两个封装体。通过上述方式，本申请能够实现芯片的直立安装，简化连接件的连接路径，提高封装体的空间利用率。

Description

一种封装体及其制备方法 【技术领域】
本申请应用于封装体的技术领域，特别是一种封装体及其制备方法。
【背景技术】
封装技术用于安装半导体集成电路芯片用的外壳，并起着安放、固定、密封、保护电子器件和增强电热性能的作用，而且还是沟通电子器件内部电路与外部电路的桥梁。
目前的封装体对各种元器件的封装存在一定的局限性，导致封装体的空间利用率不足。
【发明内容】
本申请提供了一种封装体及其制备方法，以解决封装体空间利用率不足的问题。
为解决上述技术问题，本申请提供了一种封装体的制备方法，包括：获取到加工板件，加工板件包括相对两侧形成有焊盘的载板以及分别在载板的相对两侧贴合设置的第一塑封层；在各第一塑封层远离载板的一侧分别制备连接对应焊盘的连接件，并分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽；其中，预设位置与连接件部分重叠；将芯片直立安装于对应的控深槽内，并使芯片的侧面与连接件连接；在各第一塑封层远离载板的一侧分别形成第二塑封层，并对载板进行分板，以得到至少两个封装体。
其中，获取到加工板件，加工板件包括相对两侧形成有焊盘的载板以及分别载板的相对两侧贴合设置的第一塑封层的步骤包括：获取到相对两侧均形成有焊盘的载板；对载板的相对两侧进行第一次双面塑封，以在载板的相对两侧分别形成第一塑封层，得到加工板件。
其中，焊盘包括第一焊盘以及第二焊盘；对载板的相对两侧进行第一次双面塑封，以在载板的相对两侧分别形成第一塑封层，得到加工板件的步骤之前，包括：将元器件安装于第二焊盘上。
其中，在各第一塑封层远离载板的一侧分别制备连接对应焊盘的连接件的步骤包括：基于各第一焊盘的位置对各第一塑封层进行钻孔，得到分别裸露各第一焊盘的盲孔；对各盲孔进行金属化，直至得到与各第一塑封层远离载板的一侧贴合设置的连接件；其中，连接件的各端沿着对应的盲孔延伸至对应的第一焊盘进行连接。
其中，对各盲孔进行金属化，直至得到与各第一塑封层远离载板的一侧贴合设置的连接件的步骤包括：对加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各盲孔并在各第一塑封层远离载板的一侧形成连接件。
其中，对加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各盲孔并在各第一塑封层远离载板的一侧形成连接件的步骤包括：对加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各盲孔并在各第一塑封层远离载板的 一侧形成电镀金属层；将电镀金属层作为连接件；或对电镀金属层进行蚀刻，以形成连接件。
其中，在各第一塑封层远离载板的一侧分别形成第二塑封层，并对载板进行分板，以得到至少两个封装体的步骤包括：对加工板件的相对两侧进行第二次双面塑封，以各第一塑封层远离载板的一侧分别形成第二塑封层；在各第二塑封层远离载板的一侧依次压合增强片以及涂覆阻焊层；对载板进行分板，得到至少两个封装体。
其中，载板包括基板以及形成于基板相对两侧的焊盘；载板的基板包括依次层叠且贴合设置的导电层、第一介质层以及导电层；或载板的基板包括第二介质层、导电层、第一介质层、导电层以及第二介质层；其中，各第二介质层上形成有导电孔，以连接载板的焊盘以及对应的导电层。
其中，对载板进行分板，得到至少两个封装体的步骤包括：去除第一介质层，以对载板进行分板；对裸露的导电层进行蚀刻，以得到至少两个封装体。
其中，分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽的步骤包括：通过机械、激光或化学的方式分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽。
为解决上述技术问题，本申请还提供了一种封装体，包括：塑封层，塑封层内部形成有控深槽，塑封层的一侧形成有焊盘；芯片，芯片直立容置于控深槽内；连接件，连接件的一端与对应的焊盘连接，连接件的另一端与芯片的侧面连接，以将芯片的电信号引出封装体。
其中，塑封层的一侧形成有第一焊盘以及第二焊盘；连接件的一端与对应的第一焊盘连接，连接件的另一端与芯片的侧面连接；第二焊盘靠近塑封层的一侧上安装有元器件。
其中，元器件包括芯片、阻容器件、电源、开关中的一个或多个。
其中，塑封层的一侧形成有第二介质层，第二介质层远离塑封层的一侧形成有导电线路，且第二介质层上形成有导电孔；导电线路通过对应的导电孔与对应的第一焊盘或第二焊盘连接。
其中，塑封层远离导电线路的一侧贴合设置有增强片。
其中，增强片远离导电线路的一侧贴合设置有阻焊层。
其中，塑封层包括环氧树脂类、聚酰亚胺类、双马来酰亚胺三嗪类、陶瓷基类中的一种或多种。
为解决上述技术问题，本申请的封装体的制备方法通过在加工板件两侧的第一塑封层上制备连接件并基于连接件的位置进行局部控深以形成控深槽，从而将芯片直立地安装于控深槽内，进而可以直接将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行直接连接，从而能够实现芯片的直立安装，芯片的直立安装能够简化连接件的连接路径，提高封装体的空间利用率，改善***级封装和板级封装的局限性，拓展封装体的应用场景。且通过双面载板进行连接件制备、芯片安装以及塑封，因此在载板的相对两侧能够分别制备得到的封装体，能够提高封装体制备的产量，进而提高封装体制备的效率。
【附图说明】
图1是本申请提供的封装体的制备方法一实施例的流程示意图；
图2是本申请提供的封装体的制备方法另一实施例的流程示意图；
图3是图2实施例中载板一实施方式的结构示意图；
图4是图2实施例中载板另一实施方式的结构示意图；
图5是图2实施例的步骤S21的加工板件一实施方式的结构示意图；
图6是图2实施例的步骤S22的加工板件一实施方式的结构示意图；
图7是图2实施例的步骤S23的加工板件一实施方式的结构示意图；
图8是图2实施例的步骤S24的加工板件一实施方式的结构示意图；
图9是本申请提供的封装体一实施例的结构示意图；
图10是本申请提供的封装体另一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
请参阅图1，图1是本申请提供的封装体的制备方法一实施例的流程示意图。
步骤S11：获取到加工板件，加工板件包括相对两侧形成有焊盘的载板以及分别在载板的相对两侧贴合设置的第一塑封层。
获取到加工板件，其中，加工板件包括载板以及两层第一塑封层，两层第一塑封层分别与载板的相对两侧贴合设置，即载板设置与两层第一塑封层之间，而载板相对两侧上还形成有焊盘，第一塑封层与载板贴合设置时，同样覆盖对应侧的焊盘。
第一塑封层每侧的焊盘的数量可以包括多个。而载板一侧上的焊盘可以用于制备一个封装体或多个封装体，而一个封装体或多个封装体对应在载板一侧上的焊盘数量不同，具体可以基于实际需求进行设置，在此不做限定。
第一塑封层具体可以包括环氧树脂类、聚酰亚胺类、双马来酰亚胺三嗪(Bismaleimide Triazine，BT)类、陶瓷基类中的一种或多种。在此不做限定。
载板用于支撑封装体的制备，其本身的材质可以包括玻璃板、金属板或塑料板等，在此不做限定。
步骤S12：在各第一塑封层远离载板的一侧分别制备连接对应焊盘的连接件，并分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽；其中，预设位置与连接件部分重叠。
获得到加工板件后，在加工板件各第一塑封层远离载板的一侧分别制备连接对应焊盘的连接件。
在一个具体的应用场景中，可以从各第一塑封层远离载板的一侧对第一塑封层进行钻孔，直至裸露焊盘，再通过对孔进行金属化，直至形成连接对应焊盘的连接件。
在另一个具体的应用场景中，也可以从各第一塑封层远离载板的一侧对第一塑封层进行控深，直至裸露焊盘，再在焊盘上焊接导线或金属件来进行连接。制备连接件的方式在此不做限定。
制备得到连接件后，分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽；其中，预设位置与连接件部分重叠。控深槽是开设在连接件上的，也就是，基于连接件的位置进行局部控深，直至裸露连接件的截面，以形成控深槽。
控深槽用于安装芯片，当载板一侧用于制备多个封装体和/或一个封装体上需要安装多个芯片时，本步骤可以在载板的相对两侧分别制备多个控深槽。
本步骤的控深方式可以采用激光镭射控深或机械控深的方式进行，在此不做限定。
步骤S13：将芯片直立安装于对应的控深槽内，并使芯片的侧面与连接件连接。
制备得到控深槽后，将芯片直立安装于对应的控深槽内，每个控深槽内均安装芯片，由于芯片的焊盘设置于其侧面上，因此，将其直立地设置于控深槽内，可以直接将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行直接连接，从而能够实现芯片的直立安装，且芯片的直立安装能够简化连接件的连接路径，提高封装体的空间利用率。
在一个具体的应用场景中，可以将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行焊接，来实现直接连接。在另一个具体的应用场景中，可以将芯片侧面的焊盘与通过控深槽裸露出来的连接件通过导电胶粘结进行直接连接。在此不做限定。
步骤S14：在各第一塑封层远离载板的一侧分别形成第二塑封层，并对载板进行分板，以得到至少两个封装体。
安装芯片后，在各第一塑封层远离载板的一侧分别形成第二塑封层，从而将连接件以及芯片进行塑封。
而本实施例的载板为双面载板，每面载板上均进行了连接件制备、芯片安装以及塑封，因此在载板的相对两侧分别制备得到的封装体。因此，通过对载板进行分板，以得到至少两个封装体。其中，载板也可以进行批量封装体的制备，在分板后，对分板后的两个板件分别进行切割，得到多个独立的封装体。
通过双面载板的设置，能够提高封装体制备的产量，进而提高封装体制备的效率。
上述封装还可以扩大***级封装的尺寸，使其超过100*300mm，满足更多的应用需要。
通过上述步骤，本实施例的封装体的制备方法通过在加工板件两侧的第一塑封层上制备连接件，并基于连接件的位置进行局部控深以形成控深槽，从而将芯片直立地安装于控深槽内，进而可以直接将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行直接连接，从而能够实现芯片的直立安装，芯片的直立安装能够简化连接件的连接路径，提高封装体的空间利用率，改善***级封装和板级封装的局限性，拓展封装体的应用场景。且通过双面载板进行连接件制备、芯片安装以及塑封，因此在载板的相对两侧能够分别制备得到的封装体，能够提高封装体制备的产量，进而提高封装体制备的效率。
请参阅图2，图2是本申请提供的封装体的制备方法另一实施例的流程示意图。
步骤S21：获取到相对两侧均形成有焊盘的载板；对载板的相对两侧进行第一次双面塑封，以在载板的相对两侧分别形成第一塑封层，得到加工板件。
获取到相对两侧均形成有焊盘的载板。其中，载板包括基板以及形成于基板相对两侧的焊盘。基板每侧的焊盘的数量可以为多个，例如：4个、8个、11个等，具体可以基于实际需求进行设置。
在一个具体的应用场景中，载板的基板包括依次层叠且贴合设置的导电层、第一介质层以及导电层。
请参阅图3，图3是图2实施例中载板一实施方式的结构示意图。
本实施方式的载板100包括基板110以及形成于基板110相对两侧的焊盘113。
其中，基板110包括依次层叠且贴合设置的导电层112、第一介质层111以及导电层112。
基板110每侧的焊盘113的数量可以为多个。
本实施方式的载板100能够便于实现封装体的小型化与轻便化。
在另一个具体的应用场景中，载板的基板包括第二介质层、导电层、第一介质层、导电层以及第二介质层；其中，各第二介质层上形成有导电孔，以连接载板的焊盘以及对应的导电层。
请参阅图4，图4是图2实施例中载板另一实施方式的结构示意图。
本实施方式的载板200包括基板210以及形成于基板210相对两侧的焊盘213。
载板200的基板210包括第二介质层214、导电层212、第一介质层211、导电层212以及第二介质层214；其中，各第二介质层214上形成有多个导电孔215，以连接载板200的焊盘213以及对应的导电层212。
本实施方式的载板200内部的导电结构呈“工字型”或“Z字型”，能够增强封装体的结构稳定性，提高封装体的可靠性。
载板上的焊盘可以包括第一焊盘以及第二焊盘，其中，第一焊盘指的是后 续用来制备连接件，以导通芯片的焊盘；第二焊盘指的是后续用来安装元器件的焊盘。其中，载板上第一焊盘以及第二焊盘的数量基于芯片以及元器件的数量进行确定，在此不做限定。
在一个具体的应用场景中，在第一次塑封前，可以将元器件安装于第二焊盘上，具体地，可以将元器件的焊盘焊接在对应的第二焊盘上，也可以通过引线键合的方式将元器件连接在对应的第二焊盘。元器件可以包括芯片、阻容器件、电源、开关等任意有/无源器件，具体种类和数量可以基于实际需求进行设置。
对载板的相对两侧同时进行第一次双面塑封，以在载板的相对两侧分别形成第一塑封层，得到加工板件，第一塑封层填充满元器件与焊盘之间的间隙。
由于本步骤的第一次塑封为双面塑封，则在塑封时，对载板的两侧同时进行施力，从而使得载板上的焊盘以及导电层在塑封过程中受力平衡，进而能够减少封装体制作过程中产生的翘曲的问题，提高封装体的结构稳定性与可靠性。
请参阅图5，图5是图2实施例的步骤S21的加工板件一实施方式的结构示意图。
本实施方式在图4实施方式的基础上，将焊盘213划分为第一焊盘241以及第二焊盘242。其中，本实施方式以第一焊盘241以及第二焊盘242均为2个为例进行说明。在其他实施方式中，第一焊盘241以及第二焊盘242的数量也可以为其他数量，在此不做限定。
各第二焊盘242远离载板200的一侧安装有元器件220，具体地，可以通过锡膏将元器件220焊接在对应的第二焊盘242上。
载板200的相对两侧还分别贴合设置有第一塑封层230，第一塑封层230分别包裹对应侧的元器件220以及焊盘213，并填充满元器件220与焊盘213之间的间隙。
当以图3实施方式的载板为基础进行后续制备时，其结构与基于图4实施方式的载板为基础进行后续制备的结构类似，不再赘述。
步骤S22：基于各第一焊盘的位置对各第一塑封层进行钻孔，得到分别裸露各第一焊盘的盲孔；对各盲孔进行金属化，直至得到与各第一塑封层远离载板的一侧贴合设置的连接件。
基于各第一焊盘的位置对各第一塑封层进行钻孔，得到分别裸露各第一焊盘的盲孔。钻孔时可以采用激光镭射钻孔。
对各盲孔进行金属化，直至得到与各第一塑封层远离载板的一侧贴合设置的连接件。可以对加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各盲孔并在各第一塑封层远离载板的一侧形成电镀金属层，在一个具体的应用场景中，可以对电镀金属层进行蚀刻，去除掉不需要的部分，以形成连接件。在另一个具体的应用场景中，也可以直接将电镀金属层作为连接件，通过增加连接件的面积提高封装体散热效率。
其中，连接件的中部与各第一塑封层远离载板的一侧贴合设置，其各端沿着对应的盲孔延伸至对应的第一焊盘进行连接。其中，一个连接件可以包括至少两端，而各第一塑封层远离载板的一侧可以设置至少一个连接件。
请参阅图6，图6是图2实施例的步骤S22的加工板件一实施方式的结构示意图。
本实施方式的加工板件202在图5实施方式的基础上，在两个第一塑封层230上分别制备出盲孔251，其中，每个盲孔251裸露一个对应的第一焊盘241。各第一塑封层230远离第一焊盘241的一侧上还贴合设置有连接件260，连接件260的各端沿着对应的盲孔251延伸至对应的第一焊盘241进行连接。
步骤S23：分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽；将芯片直立安装于对应的控深槽内，并使芯片的侧面与连接件连接。
分别对各第一塑封层的预设位置进行控深，直至裸露连接件的截面，以形成控深槽，其中，预设位置与连接件部分重叠。其中，控深槽可以通过机械、激光或化学的方式进行控深。
控深槽是开设在连接件上的，也就是，基于连接件的位置进行局部控深，直至裸露连接件的截面，以形成控深槽。控深槽的槽壁由连接件以及第一塑封层形成。
控深槽用于安装芯片，当载板一侧用于制备多个封装体和/或一个封装体上需要安装多个芯片时，本步骤在载板的相对两侧分别制备多个控深槽。
将芯片直立安装于对应的控深槽内，并使芯片的侧面与连接件连接。每个控深槽内均安装芯片，由于芯片的焊盘设置于其侧面上，因此，将其直立地设置于控深槽内，可以直接将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行直接连接，从而能够实现芯片的直立安装，且芯片的直立安装能够简化连接件的连接路径，提高封装体的空间利用率。
芯片安装后，芯片可以依次与连接件、第一焊盘、导电层、第二焊盘以及元器件进行电连接。
请参阅图7，图7是图2实施例的步骤S23的加工板件一实施方式的结构示意图。
本实施方式的加工板件203在图6实施方式的基础上，在各第一塑封层230上开设有至少一个控深槽(图中未标注)，控深槽内直立安装有芯片270。其中，控深槽的内壁由连接件260以及第一塑封层230组成，芯片270的焊盘形成于芯片270的侧面，与控深槽的内壁上的连接件260连接。在本实施方式中芯片270的相对两侧面都可以设置有焊盘，从而分别与被控深断开的连接件260的两面进行连接。在其他实施方式中，芯片270可以仅一面设置焊盘，其与被控深断开的连接件260的一面进行连接。其中，芯片270可以与连接件260焊接固定。
将芯片270直立地设置于控深槽内，可以直接将芯片270侧面的焊盘与通过控深槽裸露出来的连接件260进行直接连接，从而能够实现芯片270的直立安装，且芯片270的直立安装能够简化连接件260的连接路径，提高封装体的空间利用率。
步骤S24：对加工板件的相对两侧进行第二次双面塑封，以各第一塑封层远离载板的一侧分别形成第二塑封层；在各第二塑封层远离载板的一侧依次压合 增强片以及涂覆阻焊层；对载板进行分板，得到至少两个封装体。
芯片安装完成后，对加工板件的相对两侧进行第二次双面塑封，以各第一塑封层远离载板的一侧分别形成第二塑封层。第二塑封层包覆芯片以及连接件。
第二塑封层具体可以包括环氧树脂类、聚酰亚胺类、双马来酰亚胺三嗪(Bismaleimide Triazine，BT)类、陶瓷基类中的一种或多种。在此不做限定。
由于本步骤的第二次塑封为双面塑封，则在塑封时，对加工板件的两侧同时进行施力，从而使得加工板件上的连接件在塑封过程中受力平衡，进而能够减少封装体制作过程中产生的翘曲的问题，提高封装体的结构稳定性与可靠性。本实施例的第一次塑封与第二次塑封均为双面塑封能够提高封装体制作过程中的平衡性，减少封装体制作过程中受力不均的问题。第二次塑封后，第一塑封层与第二塑封层可以形成整体塑封层。
第二次塑封后，在各第二塑封层远离载板的一侧依次压合增强片以及涂覆阻焊层，以通过增强片提高封装体的结构刚性，增强结构稳定性，并通过阻焊层提高封装体表面的绝缘性，减少与其他器件发生短路的情况。阻焊层可以包括油墨等绝缘物质。
请参阅图8，图8是图2实施例的步骤S24的加工板件一实施方式的结构示意图。
本实施方式的加工板件204在图7实施方式的基础上，在各第一塑封层230远离载板200的一侧贴合设置有第二塑封层280，各第二塑封层280包覆对应侧的芯片270以及连接件260。
第二塑封层280远离载板200的一侧贴合设置有增强片291，而增强片291远离载板200的一侧贴合设置有阻焊层292。
对载板进行分板，得到至少两个封装体。具体地，去除载板的第一介质层，以对载板进行分板，并将分板后裸露的导电层进行图形蚀刻，形成导电线路，以得到至少两个封装体。其中，导电线路的具体形状可以基于实际情况进行设置，在此不做限定。
对封装体进行表面涂覆保护层后可以进行入库。
在一个具体的应用场景中，当载板进行批量封装体的制备时，在分板后，可以对载板进行切割，得到多个独立的封装体。
通过上述步骤，本实施例的封装体的制备方法通过在加工板件两侧的第一塑封层上制备连接件并基于连接件的位置进行局部控深以形成控深槽，从而将芯片直立地安装于控深槽内，进而可以直接将芯片侧面的焊盘与通过控深槽裸露出来的连接件进行直接连接，从而能够实现芯片的直立安装，芯片的直立安装能够简化连接件的连接路径，提高封装体的空间利用率。且通过双面载板进行连接件制备、芯片安装以及塑封，因此在载板的相对两侧能够分别制备得到的封装体，能够提高封装体制备的产量，进而提高封装体制备的效率。且本实施例的第一次塑封与第二次塑封均为双面塑封能够提高封装体制作过程中的平衡性，减少封装体制作过程中受力不均的问题，减少封装体制作过程中产生的翘曲的问题，提高封装体的结构稳定性与可靠性。
请参阅图9，图9是本申请提供的封装体一实施例的结构示意图。
本实施例的封装体900包括塑封层980、芯片970以及连接件960。
塑封层980内部形成有控深槽(图中未标注)，塑封层980的一侧形成有焊盘940。芯片970直立容置于控深槽内。芯片970以及连接件960的数量分别可以为一个或多个，在此不做限定。
而连接件960的一端与对应的焊盘940连接，连接件960的另一端与芯片970的侧面连接，以将芯片970的电信号引出封装体900。
当芯片970的一侧形成有焊盘时，一个连接件960的一端与对应的焊盘940连接，连接件960的另一端与芯片970的侧面的焊盘连接。
当芯片970的两侧分别形成有焊盘时，2个连接件960的一端与对应的焊盘940连接，2个连接件960的另一端分别与芯片970的相对两侧的焊盘连接。
通过上述结构，本实施例的封装体通过连接件与控深槽的配合设置能够实现芯片的直立安装，从而简化连接件的连接路径，提高封装体的空间利用率。
在其他实施例中，塑封层980的一侧形成有第一焊盘941以及第二焊盘942，即焊盘940包括第一焊盘941与第二焊盘942。第一焊盘941指的是通过连接件960与芯片970导通的焊盘940；第二焊盘942指的是用来安装元器件920的焊盘940。
连接件960的一端与对应的第一焊盘941连接，连接件960的另一端与芯片970的侧面连接。
第二焊盘942靠近塑封层980的一侧上安装有元器件920。
在其他实施例中，塑封层980的一侧形成有第二介质层914，第二介质层914远离塑封层980的一侧形成有导电线路990，且第二介质层914上形成有导电孔915。
导电线路990通过对应的导电孔915与对应的第一焊盘941或第二焊盘942连接。
则元器件920可以依次通过第二焊盘942、导电孔915以及导电线路990实现对外连接。芯片970可以依次通过连接件960、第一焊盘941、导电孔915以及导电线路990实现对外连接。
本实施例的封装体900可以基于图4实施方式的载板进行制备得到。本实施例的封装体900能够增强封装体的结构稳定性，提高封装体的可靠性。
其中，导电线路990上可以包括与焊盘940连接的外焊盘以及连接外焊盘之间的线路。
在其他实施例中，塑封层980远离导电线路990的一侧可以贴合设置增强片991，以提高封装体900的结构刚性。
在其他实施例中，增强片991远离导电线路990的一侧可以贴合设置阻焊层992，以增强封装体900的表面绝缘性。
请参阅图10，图10是本申请提供的封装体另一实施例的结构示意图。
本实施例的封装体1000的增强片、阻焊层、芯片1070、连接件1060、塑封层1080、元器件1020、焊盘1040、第一焊盘1041、第二焊盘1042之间的位置与连接关系均与前述实施例相同，请参阅前文，不再赘述。
本实施例的塑封层1080的一侧贴合设置有导电线路1015，导电线路1015 与至少部分第一焊盘1041和/或第二焊盘1042连接。从而使得元器件1020可以依次通过第二焊盘1042以及导电线路990实现对外连接。芯片1070可以依次通过连接件1060、第一焊盘1041以及导电线路990实现对外连接。
其中，导电线路1090上可以包括与焊盘1040连接的外焊盘以及连接外焊盘之间的线路。
本实施例的封装体1000便于实现小型化与轻便化。
本实施例的封装体1000可以基于图3实施方式的载板进行制备得到。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (17)

  1. 一种封装体的制备方法，其中，所述封装体的制备方法包括：
    获取到加工板件，所述加工板件包括相对两侧形成有焊盘的载板以及分别在所述载板的相对两侧贴合设置的第一塑封层；
    在各所述第一塑封层远离所述载板的一侧分别制备连接对应所述焊盘的连接件，并分别对各所述第一塑封层的预设位置进行控深，直至裸露所述连接件的截面，以形成控深槽；其中，所述预设位置与所述连接件部分重叠；
    将芯片直立安装于对应的控深槽内，并使所述芯片的侧面与所述连接件连接；
    在各所述第一塑封层远离所述载板的一侧分别形成第二塑封层，并对所述载板进行分板，以得到至少两个封装体。
  2. 根据权利要求1所述的封装体的制备方法，其中，所述获取到加工板件，所述加工板件包括相对两侧形成有焊盘的载板以及分别所述载板的相对两侧贴合设置的第一塑封层的步骤包括：
    获取到相对两侧均形成有焊盘的载板；
    对所述载板的相对两侧进行第一次双面塑封，以在所述载板的相对两侧分别形成第一塑封层，得到所述加工板件。
  3. 根据权利要求2所述的封装体的制备方法，其中，所述焊盘包括第一焊盘以及第二焊盘；
    所述对所述载板的相对两侧进行第一次双面塑封，以在所述载板的相对两侧分别形成第一塑封层，得到所述加工板件的步骤之前，包括：
    将元器件安装于所述第二焊盘上。
  4. 根据权利要求3所述的封装体的制备方法，其中，所述在各所述第一塑封层远离所述载板的一侧分别制备连接对应所述焊盘的连接件的步骤包括：
    基于各第一焊盘的位置对各所述第一塑封层进行钻孔，得到分别裸露各所述第一焊盘的盲孔；
    对各所述盲孔进行金属化，直至得到与各所述第一塑封层远离所述载板的一侧贴合设置的连接件；其中，所述连接件的各端沿着对应的所述盲孔延伸至对应的第一焊盘进行连接。
  5. 根据权利要求4所述的封装体的制备方法，其中，所述对各所述盲孔进行金属化，直至得到与各所述第一塑封层远离所述载板的一侧贴合设置的连接件的步骤包括：
    对所述加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各所述盲孔并在各所述第一塑封层远离所述载板的一侧形成所述连接件。
  6. 根据权利要求5所述的封装体的制备方法，其中，所述对所述加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各所述盲孔并在各所述第一塑封层远离所述载板的一侧形成所述连接件的步骤包括：
    对所述加工板件的相对两侧进行电镀、溅射或蒸镀，直至填充满各所述盲孔并在各所述第一塑封层远离所述载板的一侧形成电镀金属层；
    将所述电镀金属层作为所述连接件；或
    对所述电镀金属层进行蚀刻，以形成所述连接件。
  7. 根据权利要求1所述的封装体的制备方法，其中，所述在各所述第一塑封层远离所述载板的一侧分别形成第二塑封层，并对所述载板进行分板，以得到至少两个封装体的步骤包括：
    对所述加工板件的相对两侧进行第二次双面塑封，以各所述第一塑封层远离所述载板的一侧分别形成第二塑封层；
    在各所述第二塑封层远离所述载板的一侧依次压合增强片以及涂覆阻焊层；
    对所述载板进行分板，得到至少两个封装体。
  8. 根据权利要求1所述的封装体的制备方法，其中，所述载板包括基板以及形成于所述基板相对两侧的焊盘；
    所述载板的基板包括依次层叠且贴合设置的导电层、第一介质层以及导电层；或
    所述载板的基板包括第二介质层、导电层、第一介质层、导电层以及第二介质层；其中，各所述第二介质层上形成有导电孔，以连接所述载板的焊盘以及对应的导电层。
  9. 根据权利要求8所述的封装体的制备方法，其中，所述对所述载板进行分板，得到至少两个封装体的步骤包括：
    去除所述第一介质层，以对所述载板进行分板；
    对裸露的导电层进行蚀刻，以得到至少两个封装体。
  10. 根据权利要求1所述的封装体的制备方法，其中，所述分别对各所述第一塑封层的预设位置进行控深，直至裸露所述连接件的截面，以形成控深槽的步骤包括：
    通过机械、激光或化学的方式分别对各所述第一塑封层的预设位置进行控深，直至裸露所述连接件的截面，以形成所述控深槽。
  11. 一种封装体，其中，所述封装体包括：
    塑封层，所述塑封层内部形成有控深槽，所述塑封层的一侧形成有焊盘；
    芯片，所述芯片直立容置于所述控深槽内；
    连接件，所述连接件的一端与对应的焊盘连接，所述连接件的另一端与所述芯片的侧面连接，以将所述芯片的电信号引出所述封装体。
  12. 根据权利要求11所述的封装体，其中，
    所述塑封层的一侧形成有第一焊盘以及第二焊盘；
    所述连接件的一端与对应的第一焊盘连接，所述连接件的另一端与所述芯片的侧面连接；
    所述第二焊盘靠近所述塑封层的一侧上安装有元器件。
  13. 根据权利要求12所述的封装体，其中，所述元器件包括芯片、阻容器件、电源、开关中的一个或多个。
  14. 根据权利要求12所述的封装体，其中，
    所述塑封层的一侧形成有第二介质层，所述第二介质层远离所述塑封层的 一侧形成有导电线路，且所述第二介质层上形成有导电孔；
    所述导电线路通过对应的所述导电孔与对应的第一焊盘或第二焊盘连接。
  15. 根据权利要求14所述的封装体，其中，
    所述塑封层远离所述导电线路的一侧贴合设置有增强片。
  16. 根据权利要求15所述的封装体，其中，
    所述增强片远离所述导电线路的一侧贴合设置有阻焊层。
  17. 根据权利要求11所述的封装体，其中，
    所述塑封层包括环氧树脂类、聚酰亚胺类、双马来酰亚胺三嗪类、陶瓷基类中的一种或多种。
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