JP5406389B2 - 部品内蔵基板及びその製造方法 - Google Patents
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0154—Polyimide
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
図1は、本発明の第1の実施形態に係る部品内蔵基板の構造を示す断面図である。図1に示すように、第1の実施形態に係る部品内蔵基板1は、第1プリント配線基材10と、第2プリント配線基材20と、第3プリント配線基材30と、第4プリント配線基材40とを熱圧着により一括積層した構造を備えている。
図2、図3及び図5は、部品内蔵基板の製造工程を示すフローチャート、図4は、部品内蔵基板の製造工程における電子部品の製造工程を示すフローチャートである。また、図6、図7及び図9は、部品内蔵基板を製造工程毎に示す断面図、図8は、部品内蔵基板に内蔵される電子部品を製造工程毎に示す断面図である。
図10は、本発明の第2の実施形態に係る部品内蔵基板1Aの構造を示す断面図である。第2の実施形態に係る部品内蔵基板1Aは、第1及び第2プリント配線基材10,20間に、更に第5プリント配線基材50が積層されている点が、第1の実施形態に係る部品内蔵基板1と相違している。
図11は、本発明の第3の実施形態に係る部品内蔵基板1Bの構造を示す断面図である。第3の実施形態に係る部品内蔵基板1Bは、第1及び第2プリント配線基材10,20間に、更に第5プリント配線基材50が積層されている点は第2の実施形態に係る部品内蔵基板1Aと同様であるが、以下の点で第2の実施形態に係る部品内蔵基板1Aと相違している。
図12は、本発明の第4の実施形態に係る部品内蔵基板1Cの構造を示す断面図である。第4の実施形態に係る部品内蔵基板1Cは、第1プリント配線基材10の上に、更に第6及び第7プリント配線基板60,70が積層されている点が、第3の実施形態に係る部品内蔵基板1Bと相違している。
2,3,4 ビアホール
7 マスク材
8 導体層
9 接着層
9a 接着材
10 第1プリント配線基材
11 第1樹脂基材
12 信号用配線
13 放熱用配線
14 信号用ビア
15 放熱用ビア(サーマルビア)
20 第2プリント配線基材
21 第2樹脂基材
22 信号用配線
24 信号用ビア
29 開口部
30 第3プリント配線基材
31 第3樹脂基材
32 信号用配線
34 信号用ビア
40 第4プリント配線基材
41 第4樹脂基材
42 信号用配線
44 信号用ビア
50 第5プリント配線基材
51 第5樹脂基材
52 信号用配線
53 放熱用配線
54 信号用ビア
55 放熱用ビア(サーマルビア)
60 第6プリント配線基材
61 第6樹脂基材
62 信号用配線
63 放熱用配線
64 信号用ビア
65 放熱用ビア(サーマルビア)
70 第7プリント配線基材
71 第7樹脂基材
72 信号用配線
73 放熱用配線
74 信号用ビア
75 放熱用ビア(サーマルビア)
90 電子部品
91 再配線電極
91a 裏面
91b 電極形成面
91c パッド
91d 絶縁層
Claims (6)
- 絶縁基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板であって、
前記複数のプリント配線基材のうち、前記電子部品の電極形成面側とは反対側の裏面側に少なくとも2層分のプリント配線基材が配置され、前記電子部品の裏面側に配置された少なくとも2層分のプリント配線基材は、前記配線パターンとして前記電子部品の裏面上の領域に前記絶縁基材を介して多層に配置された放熱用配線パターンを含み、前記放熱用配線パターンは、放熱用配線と信号用配線とが連続した状態で形成され、前記ビアとして前記裏面上の領域に配置されて前記電子部品の裏面及び前記多層に配置された放熱用配線パターンを接続する複数の放熱用ビアを含み、
前記放熱用配線パターンは、前記放熱用ビアと接続された箇所から連続して前記電子部品の外周側に配置された他のビアにも接続されている
ことを特徴とする部品内蔵基板。 - 前記放熱用ビアは、前記他のビアよりも大きな直径を有する
ことを特徴とする請求項1記載の部品内蔵基板。 - 前記放熱用ビアの直径は、60μm〜500μmの範囲に設定されている
ことを特徴とする請求項1又は2記載の部品内蔵基板。 - 樹脂基材に配線パターン及びビアが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板の製造方法であって、
複数の樹脂基材に前記配線パターン及び前記ビアを形成すると共に、前記複数の樹脂基材のうち、前記電子部品の電極形成面側とは反対側の裏面側に配置される少なくとも2層分の樹脂基材に、前記配線パターンとして前記電子部品の裏面上の領域に前記絶縁基材を介して多層に配置され、且つ放熱用配線と信号用配線とが連続した状態で形成される放熱用配線パターンを形成すると共に、前記ビアとして前記電子部品の裏面側及び前記放熱用配線パターンと接続される複数の放熱用ビアを形成し、前記複数の樹脂基材のうちの少なくとも一つに前記電子部品を内蔵する開口部を形成して複数のプリント配線基材を形成する工程と、
前記電子部品の裏面側に前記放熱用ビア及び放熱用配線パターンが形成されたプリント配線基材を少なくとも2層分積層し、前記電子部品の裏面が前記放熱用ビアを介して前記多層に配置される放熱用配線パターンと接続され、且つ前記放熱用配線パターンが前記放熱用ビアと接続された箇所から連続して前記電子部品の外周側に配置された他のビアにも接続されるように前記複数のプリント配線基材を熱圧着して一括積層する工程とを備えた
ことを特徴とする部品内蔵基板の製造方法。 - 前記放熱用ビアは、前記他のビアよりも大きな直径を有するように形成される
ことを特徴とする請求項4記載の部品内蔵基板の製造方法。 - 前記ビア及び前記放熱用ビアは、前記ビアのビアホールを形成した後にレーザ光出力を調整して前記放熱用ビアのビアホールを形成し、形成された各ビアホール内に導電性ペーストを充填するレーザ加工及び導電性ペースト充填加工により形成される
ことを特徴とする請求項4又は5記載の部品内蔵基板の製造方法。
Priority Applications (2)
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JP2013007797A JP5406389B2 (ja) | 2012-03-01 | 2013-01-18 | 部品内蔵基板及びその製造方法 |
US14/157,669 US9282628B2 (en) | 2012-03-01 | 2014-01-17 | Component built-in board and method of manufacturing the same |
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JP2012045721 | 2012-03-01 | ||
JP2012045721 | 2012-03-01 | ||
JP2013007797A JP5406389B2 (ja) | 2012-03-01 | 2013-01-18 | 部品内蔵基板及びその製造方法 |
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JP5406389B2 true JP5406389B2 (ja) | 2014-02-05 |
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5406389B2 (ja) | 2012-03-01 | 2014-02-05 | 株式会社フジクラ | 部品内蔵基板及びその製造方法 |
JP2015185564A (ja) * | 2014-03-20 | 2015-10-22 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
JP2015220281A (ja) * | 2014-05-15 | 2015-12-07 | イビデン株式会社 | プリント配線板 |
JP6315681B2 (ja) * | 2014-05-27 | 2018-04-25 | 株式会社フジクラ | 部品内蔵基板及びその製造方法並びに実装体 |
EP3735942B1 (en) | 2015-02-03 | 2024-06-19 | RCM Enterprise, LLC | Bio-mechanical prosthetic finger with h-shaped rocker |
US9707101B2 (en) | 2015-02-03 | 2017-07-18 | Rcm Enterprise Llc | Bio-mechanical prosthetic finger with Y-shaped rocker |
WO2016126739A1 (en) | 2015-02-03 | 2016-08-11 | RCM Enterprise, LLC | Biomechanical finger brace assembly |
US9629731B2 (en) | 2015-05-15 | 2017-04-25 | RCM Enterprise, LLC | Bidirectional biomechanical prosthetic full finger configured for abduction and adduction with MCP pivot and multiple-finger ring |
JP6720294B2 (ja) | 2015-05-15 | 2020-07-08 | アールシーエム エンタープライズ, エルエルシーRcm Enterprise, Llc | Mcpピボットによる外転及び内転を行うように構成された生体力学的双方向フル義指 |
WO2017035387A1 (en) | 2015-08-25 | 2017-03-02 | RCM Enterprise, LLC | Bio-mechanical prosthetic thumb |
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KR101762027B1 (ko) * | 2015-11-20 | 2017-07-26 | 삼성전기주식회사 | 코일 부품 및 그 제조 방법 |
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