WO2016147541A1 - 窒化物半導体装置 - Google Patents

窒化物半導体装置 Download PDF

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Publication number
WO2016147541A1
WO2016147541A1 PCT/JP2016/000655 JP2016000655W WO2016147541A1 WO 2016147541 A1 WO2016147541 A1 WO 2016147541A1 JP 2016000655 W JP2016000655 W JP 2016000655W WO 2016147541 A1 WO2016147541 A1 WO 2016147541A1
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Prior art keywords
nitride semiconductor
layer
opening
semiconductor device
semiconductor layer
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PCT/JP2016/000655
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English (en)
French (fr)
Inventor
柴田　大輔
田中　健一郎
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パナソニック株式会社
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Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to JP2017506045A priority Critical patent/JP6665157B2/ja
Publication of WO2016147541A1 publication Critical patent/WO2016147541A1/ja
Priority to US15/698,222 priority patent/US10193001B2/en

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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Definitions

  • the present disclosure relates to a nitride semiconductor device.
  • Patent Document 1 discloses a nitride semiconductor device including an SBD (Schottky Barrier Diode) protection unit for bypassing against a surge voltage or the like.
  • the nitride semiconductor device described in Patent Document 1 has a configuration in which a vertical FET (Field Effect Transistor) as a switching element and a vertical SBD are arranged in parallel on the same GaN substrate. is doing. According to this configuration, it is said that a semiconductor device for large current that achieves withstand voltage performance and low on-resistance and has a simple structure can be obtained.
  • SBD Schottky Barrier Diode
  • Patent Document 1 has a problem that the high breakdown voltage characteristic inherent in the nitride semiconductor vertical FET cannot be fully utilized due to the SBD protection unit.
  • an object of the present disclosure is to provide a vertical nitride semiconductor device having high breakdown voltage and low loss characteristics.
  • a nitride semiconductor device includes a substrate having a first main surface and a second main surface facing each other, and a first substrate disposed on the first main surface.
  • the nitride semiconductor device of the present disclosure it is possible to provide a nitride semiconductor device with high breakdown voltage and low loss.
  • FIG. 1 is a cross-sectional view of the nitride semiconductor device according to the embodiment.
  • FIG. 2A is a schematic cross-sectional view showing the operation of the diode during forward bias of the nitride semiconductor device according to the comparative example.
  • FIG. 2B is a schematic cross-sectional view illustrating the operation of the diode during forward bias of the nitride semiconductor device according to the embodiment.
  • FIG. 2C is a schematic cross-sectional view illustrating the operation of the diode during reverse bias of the nitride semiconductor device according to the comparative example.
  • FIG. 2D is a schematic cross-sectional view illustrating the operation of the diode during reverse bias of the nitride semiconductor device according to the embodiment.
  • FIG. 2A is a schematic cross-sectional view showing the operation of the diode during forward bias of the nitride semiconductor device according to the comparative example.
  • FIG. 2B is a schematic cross-sectional view illustrating the operation of
  • FIG. 3 is a graph showing current-voltage characteristics of a device in which SBDs are connected in parallel to a vertical nitride semiconductor transistor and a device in which MPS diodes are connected in parallel.
  • FIG. 4A is a plan view and a cross-sectional view of the nitride semiconductor device according to the embodiment.
  • FIG. 4B is a diagram illustrating an example of a planar layout of the second and third openings of the nitride semiconductor device according to the embodiment.
  • FIG. 5A is a plan view and a cross-sectional view of a nitride semiconductor device according to Modification 1 of the embodiment.
  • FIG. 5B is a diagram illustrating an example of a planar layout of the second and third openings of the nitride semiconductor device according to the first modification of the embodiment.
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Modification 2 of the embodiment.
  • FIG. 7 is a cross-sectional view of the nitride semiconductor device according to Modification 3 of the embodiment.
  • FIG. 8 is a graph showing the return current-voltage characteristics of the SBD and PN diode.
  • SBD has a merit that a rising voltage is lower than that of a PN diode, but has a demerit that a withstand voltage is low.
  • the semiconductor device according to Patent Document 1 when the withstand voltage of the SBDs connected in parallel is lower than the withstand voltage of the vertical FET, the withstand voltage of the entire device is limited by the withstand voltage of the SBD even if the withstand voltage of the vertical FET is sufficiently high. Will be. That is, the semiconductor device according to Patent Document 1 has a problem that the withstand voltage performance is not sufficient by using the SBD as a protection unit.
  • the breakdown voltage of the entire device can be sufficiently secured, but the rising voltage becomes high as described above.
  • energy is consumed by the PN diode. That is, when the rising voltage is high, the conduction loss increases accordingly.
  • FIG. 8 is a graph showing the reflux current-voltage characteristics of the SBD and PN diode. More specifically, the graph of the figure compares the loss when the SBD and the PN diode generate a return current. As shown in the graph of FIG. 8, it can be seen that the loss of the PN diode having a high operating voltage is larger than that of the SBD when the same amount of return current is generated. That is, there is a problem in that conduction loss increases by using a PN diode as a protection unit.
  • a nitride semiconductor device is arranged on a substrate having a first main surface and a second main surface facing each other, and on the first main surface.
  • the first conductivity type first nitride semiconductor layer, the second conductivity type second nitride semiconductor layer disposed on the first nitride semiconductor layer, and the second nitride A first opening formed in a semiconductor layer and reaching the first nitride semiconductor layer; and a third nitride semiconductor layer of the first conductivity type covering the first opening and having a channel region
  • a second opening and a source electrode to cover the third opening characterized in that it comprises a drain electrode disposed on the second major surface.
  • a nitride semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings.
  • the following embodiment shows a specific example of the present invention, and the numerical value, shape, material, component, arrangement position and connection form of the component are examples, and limit the present invention. is not.
  • Various modifications in which the present embodiment is modified within a range conceivable by those skilled in the art are also included in the present disclosure without departing from the gist of the present disclosure.
  • FIG. 1 is a cross-sectional view of the nitride semiconductor device according to the embodiment.
  • the nitride semiconductor device 1 according to the present embodiment includes a substrate 100, a drift layer 102, a base layer 104, a block layer 106, a base layer 108, a channel formation layer 112, and a gate.
  • An electrode 118, a source electrode 124, and a drain electrode 126 are provided.
  • a gate opening 110 first opening that penetrates the base layer 108, the block layer 106, and the base layer 104 and reaches the drift layer 102 is formed. Yes.
  • the opening is an area where a predetermined layer formed in the substrate surface direction is partially deleted, and at least a partial area of the area is the predetermined layer in the substrate surface direction. It is an enclosed area.
  • the opening has a space in the process of forming the nitride semiconductor device, but is filled with another layer when the formation is completed.
  • the gate opening 110 is formed in the foundation layer 104, and when the formation of the nitride semiconductor device 1 is completed, the gate opening 110 is filled with the channel formation layer 112 and the gate electrode 118.
  • the substrate 100 is, for example, an n-type GaN substrate containing n-type impurities, and has a film thickness of about 300 ⁇ m.
  • Si or Ge can be used as the n-type impurity
  • Mg can be used as the p-type impurity.
  • n-type and p-type include any of the above-described impurities.
  • the substrate 100 may be other than the GaN substrate, and may be any substrate that has conductivity and lattice-matches to an acceptable level in terms of the characteristics of the semiconductor layer formed on the substrate 100 and the element.
  • Ga 2 An O 3 substrate or a SiC substrate may be used.
  • it is possible to use a Si substrate in this case, it is preferable to form a buffer layer for lattice matching with the upper layer.
  • the drift layer 102 is an n-type (first conductivity type) first nitride semiconductor layer formed on the substrate 100.
  • the drift layer 102 is, for example, an n-type GaN layer containing an n-type impurity and has a thickness of about 8 ⁇ m.
  • the concentration of the n-type impurity is, for example, about 1 ⁇ 10 15 cm ⁇ 3 to 1 ⁇ 10 17 cm ⁇ 3 .
  • the underlayer 104 is a p-type (second conductivity type) second nitride semiconductor layer containing a p-type impurity formed on the drift layer 102 and has a thickness of about 200 nm.
  • the underlayer 104 may be formed by crystal growth, or may be formed by, for example, injecting Mg into an undoped GaN layer.
  • the block layer 106 is formed on the base layer 104, and any material may be used as long as it is an insulating layer or a semi-insulating layer, and the film thickness is about 200 nm. Since the block layer 106 can suppress the occurrence of a parasitic npn structure, the influence of malfunction due to the parasitic npn structure can be reduced.
  • a material of the block layer 106 for example, a GaN layer doped with C at 3 ⁇ 10 17 cm ⁇ 3 or more, more preferably 1 ⁇ 10 18 cm ⁇ 3 or more may be used.
  • the impurity concentration of Si or O serving as an n-type impurity is preferably lower than the impurity concentration of C, for example, 5 ⁇ 10 16 cm ⁇ 3 or less, more preferably 2 ⁇ 10 16 cm ⁇ 3 or less. Is preferred.
  • the block layer 106 may be formed using ion implantation of Mg, Fe, B, or the like. As long as the ion species can be increased in resistance, the same effect can be obtained with other ion species.
  • the underlayer 108 is formed on the block layer 106 and is, for example, an n-type AlGaN layer containing undoped or n-type impurities, and has a thickness of about 20 nm.
  • the underlayer 108 functions to stop the diffusion of p-type impurities (such as Mg) from the underlayer 104.
  • the channel formation layer 112 covers the gate opening 110, and the n-type (first conductivity type) third nitride semiconductor layer disposed in the upper surface of the base layer 108, the upper surface of the drift layer 102, and the gate opening 110.
  • the electron transit layer 114 and the electron supply layer 116 having a larger band gap than the electron transit layer 114 are provided.
  • the electron transit layer 114 may be disposed on the electron supply layer 116, but it is preferable that the electron supply layer 116 be disposed on the electron transit layer 114.
  • a two-dimensional electron gas (2DEG) which will be described later, is arranged farther from the p-type base layer 104, and the two-dimensional electron gas (2DEG) is less susceptible to the constriction effect by the base layer 104, and the on-resistance Can be reduced.
  • the electron transit layer 114 is, for example, a GaN layer that is regrown to a thickness of about 100 nm and includes an n-type impurity such as undoped or at least Si.
  • the electron supply layer 116 is, for example, an AlGaN layer regrown to a film thickness of about 50 nm.
  • a two-dimensional electron gas (2DEG) serving as a channel region is formed in the vicinity of the interface between the electron transit layer 114 and the electron supply layer 116 in the electron transit layer 114.
  • 2DEG two-dimensional electron gas
  • an AlN layer may be formed by regrowth between the electron transit layer 114 and the electron supply layer 116. The regrown AlN layer can suppress alloy scattering and improve channel mobility.
  • the gate electrode 118 is disposed on the channel formation layer 112 and is made of, for example, Pd.
  • the gate electrode material does not have to be Pd, and any material can be used as long as it is a Schottky contact with the n-type nitride semiconductor.
  • a Ni-based material or WSi is used. Can do.
  • an insulating layer such as SiN or SiO 2 may be formed between the gate electrode 118 and the channel formation layer 112. With this configuration, a normally-off operation can be realized by suppressing the gate current and shifting the threshold voltage in the positive direction.
  • an opening 120 (second opening) reaching the base layer 104 is formed in a region separated from the gate electrode 118.
  • An opening 122 (third opening) reaching the drift layer 102 is formed on the bottom surface of the opening 120.
  • one opening 122 may be provided, it is desirable that two or more openings be formed. Note that the opening 120 is partially filled with the source electrode 124 when the formation is completed. The opening 122 is filled with the source electrode 124 when the formation is completed.
  • a source electrode 124 made of Ti / Al is disposed so as to cover the side wall 121 of the opening 120 and the side wall 123 of the opening 122.
  • the source electrode 124 is in contact with the two-dimensional electron gas (2DEG) formed in the channel formation layer 112, and is in contact with the base layer 104 and the drift layer 102 through the opening 122.
  • 2DEG two-dimensional electron gas
  • the material of the source electrode 124 may not be Ti / Al, and may be any material as long as it is in ohmic contact with the n-type.
  • the drain electrode 126 is disposed on the back surface of the substrate 100.
  • the drain electrode material may be any material as long as it is in ohmic contact with the n-type.
  • the nitride semiconductor device 1 according to this embodiment is characterized in that an MPS (Merged PiN Schottky) diode is formed in parallel with the vertical GaN transistor.
  • the MPS diode has the merits of both the high withstand voltage characteristics of the PiN diode (strictly speaking, in the present embodiment, the PN diode) and the low operating voltage of the SBD.
  • the MPS diode included in the nitride semiconductor device 1 includes a PN diode formed by the base layer 104 and the drift layer 102, and an SBD formed by the source electrode 124 and the drift layer 102 at the bottom of the opening 122. It consists of Further, the PN diode and the SBD are alternately arranged by the plurality of openings 122. As a result, it is possible to operate at a higher withstand voltage than in the prior art, and to perform energy consumption such as surge voltage and return current with low loss.
  • FIG. 2A is a schematic cross-sectional view showing the operation of the diode during forward bias of the nitride semiconductor device according to the comparative example.
  • FIG. 2B is a schematic cross-sectional view illustrating the operation of the diode during forward bias of the nitride semiconductor device according to the embodiment.
  • the opening 122 is not formed, and the opening 120 reaches the drift layer 102 directly.
  • a plurality of openings 122 are discretely formed between the openings 120 and the drift layer 102, and the plurality A base layer 104 is formed between the openings 122.
  • both the comparative example and the embodiment realize a low operating voltage because the forward current flows through the Schottky junction between the source electrode 124 and the drift layer 102. it can.
  • the nitride semiconductor device 1 according to the embodiment has the SBD between the source electrode 124 and the drift layer 102, a low operating voltage can be realized when the diode is forward biased, and thus the return current flows through the SBD. A reduction in loss when flowing can be realized.
  • FIG. 2C is a schematic cross-sectional view showing the operation of the diode during reverse bias of the nitride semiconductor device according to the comparative example.
  • FIG. 2D is a schematic cross-sectional view illustrating the operation of the diode during reverse bias of the nitride semiconductor device according to the embodiment.
  • the underlayer 104 is also formed below the center of the opening 120 and is formed by the underlayer 104 and the drift layer 102. Since the depletion layer thus formed extends, the depletion layer can be extended over the entire bottom surface of the opening 122, that is, over the entire Schottky junction. As a result, the leakage current can be reduced, so that a high breakdown voltage can be ensured.
  • a plurality of openings 122 are formed as in the present embodiment. Thereby, when the reverse bias is applied, the depletion layer can be more efficiently extended from the base layer 104 to the bottom surface of the opening 122, so that a higher breakdown voltage can be achieved.
  • the width of the opening 122 is preferably about 0.5 to 10 ⁇ m, more preferably about 1 to 5 ⁇ m.
  • the width of the underlayer 104 formed discretely by the plurality of openings 122 is preferably about 0.5 to 10 ⁇ m, and more preferably about 1 to 5 ⁇ m. However, this is not limited as long as there is an effect that a high breakdown voltage and a low loss can be realized by parallel connection of the PN diode and the SBD.
  • FIG. 3 is a graph showing current-voltage characteristics of a device in which an SBD is connected in parallel to a vertical nitride semiconductor transistor and a device in which an MPS diode is connected in parallel. More specifically, the graph in the figure compares the breakdown voltage characteristics of the two devices. It can be seen that the device with the MPS diode connected in parallel has a higher withstand voltage than the device with the SBD connected in parallel.
  • the nitride semiconductor device 1 according to the present embodiment includes the MPS diode in parallel with the vertical GaN transistor, the forward breakdown voltage is maintained while maintaining a high breakdown voltage by the function of the PN diode at the time of reverse bias. Since the rising voltage is low due to the function of the SBD at the time, it is possible to reduce the loss when the return current flows through the MPS diode.
  • FIG. 4A is a plan view and a cross-sectional view of the nitride semiconductor device according to the embodiment.
  • FIG. 4B is a diagram illustrating an example of a planar layout of the second and third openings of the nitride semiconductor device according to the embodiment.
  • rectangular source electrodes 124 are regularly arranged in plan view, and devices are integrated in a finger shape.
  • the gate electrode 118 surrounds the source electrode 124 in plan view.
  • one opening 122 may be provided continuously in the longitudinal direction of the source electrode 124 (pattern 1), or a plurality (for example, non-continuous in the longitudinal direction (for example, 4 in FIG. 4B) may be formed (pattern 2).
  • FIG. 5A is a plan view and a cross-sectional view of a nitride semiconductor device according to Modification 1 of the embodiment.
  • FIG. 5B is a diagram illustrating an example of a planar layout of the second and third openings of the nitride semiconductor device according to the first modification of the embodiment.
  • hexagonal source electrodes 124 are regularly arranged in a plan view, and the devices are integrated in a hexagonal shape.
  • the gate electrode 118 surrounds the source electrode 124 in plan view.
  • the opening 122 may be a hexagonal continuous ring shape along the outer shape of the source electrode 124 (pattern 1), or along the outer shape of the source electrode 124.
  • a plurality (for example, six in FIG. 5B) may be formed discontinuously (pattern 2).
  • FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Modification 2 of the embodiment.
  • the nitride semiconductor device 2 according to this modification is different from the nitride semiconductor device 1 in that the nitride semiconductor device 2 further includes a nitride semiconductor layer 600.
  • the description of the same configuration as that of the nitride semiconductor device 1 will be omitted, and a description will be given focusing on the configuration different from the nitride semiconductor device 1.
  • the nitride semiconductor device 2 includes a substrate 100, a drift layer 102, a base layer 104, a block layer 106, a base layer 108, a channel formation layer 612, and a gate.
  • An electrode 118, a source electrode 124, and a drain electrode 126 are provided.
  • a gate opening 110 first opening that penetrates the base layer 108, the block layer 106, and the base layer 104 and reaches the drift layer 102 is formed. Yes.
  • an opening 120 (second opening) reaching the base layer 104 is formed in a region separated from the gate electrode 118.
  • An opening 122 (third opening) reaching the drift layer 102 is formed on the bottom surface of the opening 120.
  • the channel formation layer 612 includes a nitride semiconductor layer 600, an electron transit layer 114, and an electron supply layer 116.
  • the nitride semiconductor layer 600 is a p-type nitride semiconductor layer (fourth nitride semiconductor layer), and is disposed between the channel formation layer 112 and the gate electrode 118.
  • the p-type nitride semiconductor layer 600 is, for example, a p-type GaN layer or an AlGaN layer containing a p-type impurity.
  • an insulating film such as SiN or SiO 2 may be inserted.
  • any material can be used as long as it has an effect of increasing the channel potential.
  • FIG. 7 is a cross-sectional view of a nitride semiconductor device according to Modification 3 of the present embodiment.
  • the nitride semiconductor device 3 according to this modification is different from the nitride semiconductor device 1 in the configuration of the source electrode.
  • the description of the same configuration as that of the nitride semiconductor device 1 will be omitted, and a description will be given focusing on the configuration different from the nitride semiconductor device 1.
  • the nitride semiconductor device 3 includes a substrate 100, a drift layer 102, a base layer 104, a block layer 106, a base layer 108, a channel formation layer 112, and a gate.
  • An electrode 118, a source electrode 700, and a drain electrode 126 are provided.
  • the nitride semiconductor device 3 is formed with a gate opening 110 (first opening) that penetrates the base layer 108, the block layer 106, and the base layer 104 and reaches the drift layer 102. Yes.
  • an opening 120 (second opening) reaching the base layer 104 is formed in a region separated from the gate electrode 118.
  • An opening 122 (third opening) reaching the drift layer 102 is formed on the bottom surface of the opening 120.
  • the source electrode 700 has a metal layer 702 and a metal layer 704 made of a metal different from the metal layer 702.
  • the metal layer 704 is a second metal layer in contact with the base layer 104 and the drift layer 102 in the opening 122.
  • the metal layer 702 is a first metal layer that is in contact with the two-dimensional electron gas (2DEG) at the side wall 121 of the opening 120, and is electrically connected to the metal layer 704.
  • the metal layer 704 functions as an anode electrode.
  • the metal layer 704 includes at least one of Pd, Ni, Au, Pt, and the like, and a material that is in ohmic contact with the base layer 104 that is a p-type nitride semiconductor is applied. Thereby, more stable electrical connection with the base layer 104 becomes possible. Therefore, when a reverse bias is applied (when a positive bias is applied to the drain electrode 126), the depletion layer can be more stably extended from the base layer 104, so that the reverse leakage can be further reduced and further increased. Withstand voltage can be increased.
  • the gate end is an end portion of the gate electrode 118 in the direction in which the gate electrode 118 and the source electrode 124 are arranged.
  • the gate end is the end of the nitride semiconductor layer 600 in the direction in which the gate electrode 118 and the source electrode 124 are arranged.
  • the threshold voltage of the transistor is determined only by the side wall 111 (side wall 2DEG 130) of the gate opening 110.
  • the carrier concentration of the flat portion (flat portion 2DEG132) of the channel formation layer 112 parallel to the main surface of the substrate 100 can be increased, the on-resistance can be reduced.
  • the threshold voltage of the transistor is the threshold voltage of the side wall 111 (side wall 2DEG130) of the gate opening 110 or the outside of the gate opening 110.
  • This is the larger of the threshold voltages of the flat part (flat part 2DEG132).
  • the film thickness of the electron transit layer 114 parallel to the main surface of the substrate 100 may be made smaller than the film thickness of the electron transit layer 114 parallel to the side wall 111 of the gate opening 110.
  • the distance between the two-dimensional electron gas (2DEG) on the side wall 111 of the gate opening 110 and the base layer 104 is such that the two-dimensional electron gas (2DEG) on the flat portion of the channel formation layer 112 and the base layer 104 Longer than the distance.
  • the two-dimensional electron gas on the sidewall 111 of the gate opening 110 can reduce the influence of the depletion layer extending from the base layer 104 as compared with the flat portion. It becomes possible to selectively reduce the threshold voltage of the region. Therefore, the threshold voltage of the transistor can be determined by the flat portion of the channel formation layer 112.
  • the carrier concentration of the side wall 2DEG 130 which is a two-dimensional electron gas formed on the side wall 111 of the gate opening 110 is lower than the carrier concentration of the flat portion 2DEG 132 which is the two-dimensional electron gas of the flat portion. That is, since the side wall 2DEG 130 is more susceptible to the constriction effect of the depletion layer extending from the base layer 104 than the flat part 2DEG 132, the on-resistance can be further reduced when it is away from the base layer 104.
  • the thinner the electron transit layer 114 outside the gate opening 110 the shallower the opening 120 can be made.
  • the process time can be shortened, and when the source electrode 124 is formed by vapor deposition, the occurrence of the step breakage of the vapor deposition film, that is, the phenomenon that the vapor deposition film becomes discontinuous is prevented. It becomes easy.
  • the film thickness of the electron transit layer 114 disposed outside the gate opening 110 is preferably smaller than the film thickness of the electron transit layer 114 disposed on the side wall 111 of the gate opening 110.
  • the nitride semiconductor device according to the present invention is not limited to the above embodiment and the first to third modifications thereof.
  • Various modifications including the obtained modification and the nitride semiconductor device according to the embodiment and the modification are also included in the present invention.
  • the nitride semiconductor device according to the present disclosure is useful as a power device used in, for example, a power supply circuit for consumer equipment.
  • Nitride semiconductor device 100 Substrate 102 Drift layer 104, 108 Underlayer 106 Block layer 110 Gate opening 111, 121, 123 Side wall 112, 612 Channel forming layer 118 Gate electrode 120, 122 Opening 124, 700 Source electrode 126 Drain electrode 130 Side wall 2DEG 132 Flat part 2DEG 600 Nitride semiconductor layer 702, 704 Metal layer

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Abstract

　窒化物半導体装置（１）は、基板（１００）と、基板（１００）の表面に配置されたｎ型のドリフト層（１０２）と、ドリフト層（１０２）上に配置されたｐ型の下地層（１０４）と、下地層（１０４）に形成され、ドリフト層（１０２）に達するゲート開口部（１１０）と、ゲート開口部（１１０）を覆い、チャネル領域を有するｎ型のチャネル形成層（１１２）とゲート開口部（１１０）内のチャネル形成層（１１２）上に配置されたゲート電極（１１８）と、ゲート電極（１１８）と離間し、下地層（１０４）に達する開口部（１２０）と、開口部（１２０）の底面に形成され、ドリフト層（１０２）に達する開口部（１２２）と、開口部（１２０）および開口部（１２２）を覆うソース電極（１２４）と、基板（１００）の裏面上に配置されたドレイン電極（１２６）とを備える。

Description

窒化物半導体装置
　本開示は、窒化物半導体装置に関する。
　特許文献１では、サージ電圧等に対するバイパス用のＳＢＤ（Ｓｃｈｏｔｔｋｙ　Ｂａｒｒｉｅｒ　Ｄｉｏｄｅ）保護部を備える窒化物半導体装置が開示されている。具体的には、特許文献１に記載された窒化物半導体装置は、同一のＧａＮ基板上に、スイッチング素子の縦型ＦＥＴ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）と縦型ＳＢＤとが並列に配置された構成を有している。この構成により、耐圧性能および低オン抵抗を実現し、構造が簡単な、大電流用の半導体装置が得られるとしている。
特開２０１１－１３５０９４号公報
　しかしながら、特許文献１に係る半導体装置では、ＳＢＤ保護部が原因で、窒化物半導体系の縦型ＦＥＴが本来有する高耐圧特性を活かしきれていないという課題がある。
　本開示は、上記課題に鑑み、高耐圧かつ低損失な特性を有する縦型の窒化物半導体装置を提供することを目的とする。
　上記課題を解決するため、本開示の一態様に係る窒化物半導体装置は、互いに背向する第１主面および第２主面を有する基板と、前記第１主面の上に配置された第１導電型の第１の窒化物半導体層と、前記第１の窒化物半導体層の上に配置された第２導電型の第２の窒化物半導体層と、前記第２の窒化物半導体層に形成され、前記第１の窒化物半導体層に達する第１の開口部と、前記第１の開口部を覆い、チャネル領域を有する、前記第１導電型の第３の窒化物半導体層と、前記第１の開口部内の前記第３の窒化物半導体層上に配置されたゲート電極と、前記ゲート電極と離間し、前記第２の窒化物半導体層に達する第２の開口部と、前記第２の開口部の底面に形成され、前記第１の窒化物半導体層に達する第３の開口部と、前記第２の開口部および前記第３の開口部を覆うソース電極と、前記第２主面に配置されたドレイン電極と、を備える。
　本開示の窒化物半導体装置によれば、高耐圧かつ低損失な窒化物半導体デバイスを提供することが可能となる。
図１は、実施形態に係る窒化物半導体装置の断面図である。 図２Ａは、比較例に係る窒化物半導体装置の順バイアス時のダイオードの動作を表す断面外略図である。 図２Ｂは、実施形態に係る窒化物半導体装置の順バイアス時のダイオードの動作を表す断面外略図である。 図２Ｃは、比較例に係る窒化物半導体装置の逆バイアス時のダイオードの動作を表す断面外略図である。 図２Ｄは、実施形態に係る窒化物半導体装置の逆バイアス時のダイオードの動作を表す断面外略図である。 図３は、縦型の窒化物半導体トランジスタにＳＢＤを並列に接続したデバイス、および、ＭＰＳダイオードを並列に接続したデバイスの電流－電圧特性を表すグラフである。 図４Ａは、実施形態に係る窒化物半導体装置の平面図および断面図である。 図４Ｂは、実施形態に係る窒化物半導体装置の第２および第３の開口部の平面レイアウトの例を示す図である。 図５Ａは、実施形態の変形例１に係る窒化物半導体装置の平面図および断面図である。 図５Ｂは、実施形態の変形例１に係る窒化物半導体装置の第２および第３の開口部の平面レイアウトの例を示す図である。 図６は、実施形態の変形例２に係る窒化物半導体装置の断面図である。 図７は、実施形態の変形例３に係る窒化物半導体装置の断面図である。 図８は、ＳＢＤおよびＰＮダイオードの還流電流－電圧特性を示すグラフである。
　（本発明の基礎となった知見）
　本発明者は、「背景技術」の欄において記載した従来の半導体装置に関し、以下の問題が生じることを見出した。
　一般的に、ＳＢＤはＰＮダイオードに比べて、立ち上がり電圧が低いというメリットがある一方で、耐圧が低いというデメリットがある。特許文献１に係る半導体装置では、並列接続されたＳＢＤの耐圧が、縦型ＦＥＴの耐圧よりも低い場合、たとえ縦型ＦＥＴの耐圧が十分に高くとも、装置全体の耐圧はＳＢＤの耐圧に律速されてしまう。つまり、特許文献１に係る半導体装置では、ＳＢＤを保護部とすることにより、耐圧性能が十分でないという課題を有する。
　これに対して、ＳＢＤをＰＮダイオードに置き換えた場合、装置全体の耐圧は十分に確保できるようになるものの、上述したように立ち上がり電圧が高くなる。インバーター応用を考えた場合、Ｌ負荷から還流電流が発生するため、ＰＮダイオードでエネルギーを消費することになる。つまり、立ち上がり電圧が高いと、その分、導通損失が大きくなってしまう。
　図８は、ＳＢＤおよびＰＮダイオードの還流電流－電圧特性を示すグラフである。より具体的には、同図のグラフは、ＳＢＤおよびＰＮダイオードの還流電流発生時における損失を比較したものである。図８のグラフに示すように、同じ大きさの還流電流が発生している場合、動作電圧の高いＰＮダイオードの損失が、ＳＢＤに比べて大きいことが分かる。つまり、ＰＮダイオードを保護部とすることにより、導通損失が大きくなってしまうという課題を有する。
　このような問題を解決するために、本発明の一態様に係る窒化物半導体装置は、互いに背向する第１主面および第２主面を有する基板と、前記第１主面の上に配置された第１導電型の第１の窒化物半導体層と、前記第１の窒化物半導体層の上に配置された第２導電型の第２の窒化物半導体層と、前記第２の窒化物半導体層に形成され、前記第１の窒化物半導体層に達する第１の開口部と、前記第１の開口部を覆い、チャネル領域を有する、前記第１導電型の第３の窒化物半導体層と、前記第１の開口部内の前記第３の窒化物半導体層上に配置されたゲート電極と、前記ゲート電極と離間し、前記第２の窒化物半導体層に達する第２の開口部と、前記第２の開口部の底面に形成され、前記第１の窒化物半導体層に達する第３の開口部と、前記第２の開口部および前記第３の開口部を覆うソース電極と、前記第２主面に配置されたドレイン電極と、を備えることを特徴とする。
　本態様によれば、高耐圧かつ低損失な窒化物半導体装置を提供することが可能となる。
　以下、本開示の実施の形態に係る窒化物半導体装置について、図面を参照しながら説明する。なお、以下の実施形態は、本発明の一具体例を示すものであり、数値、形状、材料、構成要素、構成要素の配置位置および接続形態などは、一例であり、本発明を限定するものではない。本開示の主旨を逸脱しない限り、本実施の形態に対して当業者が思いつく範囲内の変更を施した各種変形例も本開示に含まれる。また、本開示の主旨を逸脱しない範囲において、実施形態および変形例の少なくとも一部を組み合わせることも可能である。
　（実施形態）
　［１．窒化物半導体装置の断面構成］
　図１は、実施形態に係る窒化物半導体装置の断面図である。図１に示すように、本実施形態に係る窒化物半導体装置１は、基板１００と、ドリフト層１０２と、下地層１０４と、ブロック層１０６と、下地層１０８と、チャネル形成層１１２と、ゲート電極１１８と、ソース電極１２４と、ドレイン電極１２６とを備える。また、窒化物半導体装置１には、下地層１０８と、ブロック層１０６と、下地層１０４とを貫通して、ドリフト層１０２に到達するゲート開口部１１０（第１の開口部）が形成されている。なお、本実施形態において、開口部とは、基板面方向に層形成された所定層が一部削除された領域であって、当該領域の少なくとも一部領域が当該基板面方向に当該所定層で囲まれた領域である。また、開口部は、窒化物半導体装置の形成過程では空間を有しているが、形成完了時には他層で充填されている。例えば、ゲート開口部１１０は下地層１０４に形成され、窒化物半導体装置１の形成完了時には、ゲート開口部１１０、はチャネル形成層１１２およびゲート電極１１８で充填されている。
　基板１００は、例えば、ｎ型不純物を含むｎ型のＧａＮ基板であり、膜厚は３００μｍ程度である。なお、ｎ型不純物としては、ＳｉやＧｅを用いることができ、ｐ型不純物としては、Ｍｇを用いることができる。以下、特に断りの無い限り、ｎ型、ｐ型という場合は、上述した不純物のいずれかが含まれているものとする。基板１００は、ＧａＮ基板以外であってもよく、導電性を有し、基板１００上に形成された半導体層と素子の特性上許容できる程度で格子整合する基板であれば良く、例えば、Ｇａ２Ｏ３基板やＳｉＣ基板でも構わない。また、Ｓｉ基板を使うことも可能ではあるが、この場合は、上層と格子整合させるためにバッファ層を形成する方が好ましい。
　ドリフト層１０２は、基板１００の上に形成されたｎ型（第１導電型）の第１の窒化物半導体層である。ドリフト層１０２は、例えば、ｎ型不純物を含むｎ型のＧａＮ層であり、膜厚は８μｍ程度である。ｎ型不純物の濃度は、例えば、約１×１０１５ｃｍ－３～１×１０１７ｃｍ－３である。
　下地層１０４は、ドリフト層１０２の上に形成されたｐ型不純物を含むｐ型（第２導電型）の第２の窒化物半導体層であり、膜厚は２００ｎｍ程度である。下地層１０４は、結晶成長で形成しても良いし、例えばアンドープのＧａＮ層へＭｇを注入して形成してもよい。
　ブロック層１０６は、下地層１０４の上に形成され、絶縁層または半絶縁層であればどのような材料を用いてもよく、膜厚は２００ｎｍ程度である。ブロック層１０６は、寄生ｎｐｎ構造の発生を抑制することができるため、当該寄生ｎｐｎ構造による誤動作の影響を低減することができる。ブロック層１０６の材料としては、例えばＣを３×１０１７ｃｍ－３以上、さらに好ましくは１×１０１８ｃｍ－３以上にドープしたＧａＮ層を用いればよい。このとき、ｎ型不純物となるＳｉやＯの不純物濃度は、Ｃの不純物濃度に比べて低くする方が良く、例えば５×１０１６ｃｍ－３以下、さらに好ましくは２×１０１６ｃｍ－３以下が好ましい。ブロック層１０６は、Ｍｇ、Ｆｅ、Ｂなどのイオン注入を用いて形成されてもよい。高抵抗化できるイオン種であれば、上記以外のイオン種でも同様の効果が得られる。
　下地層１０８は、ブロック層１０６の上に形成され、例えば、アンドープ又はｎ型不純物を含むｎ型のＡｌＧａＮ層であり、膜厚は２０ｎｍ程度である。下地層１０８は、下地層１０４からのｐ型不純物（Ｍｇ等）の拡散をストップする機能を果たす。
　チャネル形成層１１２は、ゲート開口部１１０を覆い、下地層１０８の上面、ドリフト層１０２の上面、およびゲート開口部１１０に配置されたｎ型（第１導電型）の第３の窒化物半導体層であり、電子走行層１１４と、電子走行層１１４よりバンドギャップの大きい電子供給層１１６とを備える。なお、電子供給層１１６の上に電子走行層１１４が配置されていても良いが、電子走行層１１４の上に電子供給層１１６が配置されている方が好ましい。これにより、後述する２次元電子ガス（２ＤＥＧ）が、ｐ型の下地層１０４からより離れて配置されるため、２次元電子ガス（２ＤＥＧ）が下地層１０４による狭窄効果を受けにくくなり、オン抵抗を低減することができる。
　電子走行層１１４は、例えば、膜厚１００ｎｍ程度に再成長され、アンドープ又は少なくともＳｉ等のｎ型不純物を含むＧａＮ層である。電子供給層１１６は、例えば、膜厚５０ｎｍ程度に再成長されたＡｌＧａＮ層である。電子走行層１１４の、電子走行層１１４と電子供給層１１６との界面近傍において、チャネル領域となる２次元電子ガス（２ＤＥＧ）が形成される。なお、図示していないが、電子走行層１１４と電子供給層１１６との間に、ＡｌＮ層を再成長により形成してもよい。再成長ＡｌＮ層によって、合金散乱を抑制し、チャネル移動度を向上させることができる。
　ゲート電極１１８は、チャネル形成層１１２の上に配置され、例えば、Ｐｄから構成される。なお、ゲート電極材料には、Ｐｄでなくてもよく、ｎ型の窒化物半導体に対してショットキー接触となるような材料であればどんな材料でもよく、例えばＮｉ系材料、ＷＳｉなどを使うことができる。さらに、ＳｉＮやＳｉＯ２のような絶縁層を、ゲート電極１１８とチャネル形成層１１２との間に形成してもよい。この構成によって、ゲート電流を抑制し、かつ、閾値電圧を正方向にシフトさせてノーマリオフ動作を実現することが可能になる。
　また、窒化物半導体装置１には、ゲート電極１１８と離間した領域に、下地層１０４に達する開口部１２０（第２の開口部）が形成されている。開口部１２０の底面には、ドリフト層１０２に達する開口部１２２（第３の開口部）が形成されている。開口部１２２は１つでもよいが、２つ以上形成されていることが望ましい。なお、開口部１２０には、形成完了時には、ソース電極１２４が一部充填されている。また、開口部１２２には、形成完了時には、ソース電極１２４が充填されている。
　開口部１２０の側壁部１２１および開口部１２２の側壁部１２３を覆うように、Ｔｉ／Ａｌで構成されるソース電極１２４が配置されている。ソース電極１２４は、チャネル形成層１１２に形成されている二次元電子ガス（２ＤＥＧ）に接しており、開口部１２２を介して、下地層１０４およびドリフト層１０２と接している。なお、ソース電極１２４の材料としては、Ｔｉ／Ａｌでなくてもよく、ｎ型に対してオーミック接触となる材料であればどんな材料でもよい。
　ドレイン電極１２６は、基板１００の裏面上に配置されている。ドレイン電極材料は、ｎ型に対してオーミック接触となる材料であれば何でもよい。
　本実施形態に係る窒化物半導体装置１は、縦型ＧａＮトランジスタと並列にＭＰＳ（Ｍｅｒｇｅｄ　ＰｉＮ　Ｓｃｈｏｔｔｋｙ）ダイオードが形成されていることを特徴としている。ＭＰＳダイオードは、ＰｉＮダイオード（厳密に言えば、本実施形態では、ＰＮダイオード）の高耐圧特性とＳＢＤの持つ低動作電圧の両方のメリットを有している。
　具体的には、窒化物半導体装置１が有するＭＰＳダイオードは、下地層１０４およびドリフト層１０２により形成されたＰＮダイオードと、開口部１２２底部において、ソース電極１２４およびドリフト層１０２により形成されたＳＢＤとで構成されている。また、ＰＮダイオードとＳＢＤとは、複数の開口部１２２により、それぞれ交互に配置されている。これにより、従来に比べて、より高耐圧動作が可能であり、かつ、サージ電圧および還流電流などのエネルギー消費を低損失に行うことが可能になる。
　以下では、図２Ａ～図２Ｄを用いて、窒化物半導体装置が有するダイオードの動作メカニズムを説明する。
　図２Ａは、比較例に係る窒化物半導体装置の順バイアス時のダイオードの動作を表す断面外略図である。また、図２Ｂは、実施形態に係る窒化物半導体装置の順バイアス時のダイオードの動作を表す断面外略図である。図２Ａに示すように、比較例に係る窒化物半導体装置には、開口部１２２が形成されておらず、開口部１２０が直接、ドリフト層１０２に達している。これに対して、図２Ｂに示すように、本実施形態に係る窒化物半導体装置１には、開口部１２０とドリフト層１０２との間に複数の開口部１２２が離散的に形成され、当該複数の開口部１２２の間に下地層１０４が形成されている。
　図２Ａ及び図２Ｂに示すように、ダイオードの順バイアス時において、比較例および実施形態ともに、ソース電極１２４とドリフト層１０２とのショットキー接合部を順方向電流が流れるため、低動作電圧を実現できる。つまり、実施形態に係る窒化物半導体装置１は、ソース電極１２４とドリフト層１０２との間にＳＢＤを有するので、ダイオードの順バイアス時において低動作電圧を実現できるため、還流電流がＳＢＤを介して流れる際の低損失化を実現することができる。
　図２Ｃは、比較例に係る窒化物半導体装置の逆バイアス時のダイオードの動作を表す断面外略図である。また、図２Ｄは、実施形態に係る窒化物半導体装置の逆バイアス時のダイオードの動作を表す断面外略図である。
　図２Ｃに示すように、ダイオードの逆バイアス時において、比較例では、開口部１２２が無いため、下地層１０４から伸びる空乏層が、開口部１２０中央部のショットキー接合部にまで届かなくなる。その結果、逆バイアス時においても、ショットキー接合部を大きなリーク電流が流れてしまうため、耐圧が低下する。
　一方、図２Ｄに示すように、複数の開口部１２２が形成された本実施形態では、開口部１２０の中央部下方にも下地層１０４が形成され、当該下地層１０４とドリフト層１０２とにより形成された空乏層が伸びるため、開口部１２２の底面全体、つまり、全ショットキー接合部にわたって空乏層を延在させることができる。その結果、リーク電流を低減することができるため、高い耐圧を確保することができる。
　なお、上記観点から、開口部１２２は、本実施形態のように複数形成されていることが好ましい。これにより、逆バイアス印加時において、より効率的に下地層１０４から開口部１２２の底面に空乏層を伸ばすことができるため、更なる高耐圧化が可能になる。
　また、開口部１２２の幅は、約０．５～１０μｍが好ましく、約１～５μｍがより好ましい。また、複数の開口部１２２によって離散的に形成される下地層１０４の幅は、約０．５～１０μｍが好ましく、約１～５μｍがより好ましい。但し、ＰＮダイオードとＳＢＤとの並列接続によって高耐圧および低損失化が実現できる効果があればこの限りではない。
　図３は、縦型の窒化物半導体トランジスタにＳＢＤを並列に接続したデバイス、および、ＭＰＳダイオードを並列に接続したデバイスの電流－電圧特性を表すグラフである。より具体的には、同図のグラフは、上記２つのデバイスについての耐圧特性を比較している。ＳＢＤを並列に接続したデバイスに比べて、ＭＰＳダイオードを並列に接続したデバイスの方が、耐圧が高いことが分かる。
　つまり、本実施形態に係る窒化物半導体装置１は、縦型ＧａＮトランジスタと並列にＭＰＳダイオードを有しているため、逆バイアス時におけるＰＮダイオードの機能により高耐圧を維持しつつ、且つ、順バイアス時におけるＳＢＤの機能により立ち上がり電圧が低いため、還流電流がＭＰＳダイオードを介して流れる際の低損失化を実現することができる。
　［２．窒化物半導体装置の平面構成］
　図４Ａは、実施形態に係る窒化物半導体装置の平面図および断面図である。また、図４Ｂは、実施形態に係る窒化物半導体装置の第２および第３の開口部の平面レイアウトの例を示す図である。
　図４Ａに示すように、平面視において、長方形状のソース電極１２４が規則的に並び、フィンガー型にデバイスが集積化されている。ゲート電極１１８は、平面視において、ソース電極１２４を囲んでいる。
　図４Ｂに示すように、平面視において、開口部１２２は、ソース電極１２４の長手方向に連続して１つ設けられていてもよいし（パターン１）、当該長手方向に非連続に複数（例えば、図４Ｂでは８つ）形成されていても良い（パターン２）。
　図５Ａは、実施形態の変形例１に係る窒化物半導体装置の平面図および断面図である。また、図５Ｂは、実施形態の変形例１に係る窒化物半導体装置の第２および第３の開口部の平面レイアウトの例を示す図である。
　図５Ａに示すように、平面視において、六角形状のソース電極１２４が規則的に並び、六角形状にデバイスが集積化されている。ゲート電極１１８は、平面視において、ソース電極１２４を囲んでいる。
　図５Ｂに示すように、平面視において、開口部１２２は、ソース電極１２４の外形に沿うように、六角形状の連続する環形状でも良いし（パターン１）、ソース電極１２４の外形に沿うように、非連続に複数（例えば、図５Ｂでは６つ）形成されていても良い（パターン２）。
　図４Ａ、図４Ｂ、図５Ａおよび図５Ｂに示されたデバイスレイアウトを適用することにより、面積効率を向上させることが可能になる。
　［３．ゲート構造の変形例］
　図６は、実施形態の変形例２に係る窒化物半導体装置の断面図である。本変形例に係る窒化物半導体装置２は、窒化物半導体装置１と比較して、さらに窒化物半導体層６００を備える点が構成として異なる。以下、窒化物半導体装置１と同じ構成は説明を省略し、窒化物半導体装置１と異なる構成を中心に説明する。
　図６に示すように、本変形例に係る窒化物半導体装置２は、基板１００と、ドリフト層１０２と、下地層１０４と、ブロック層１０６と、下地層１０８と、チャネル形成層６１２と、ゲート電極１１８と、ソース電極１２４と、ドレイン電極１２６とを備える。また、窒化物半導体装置２には、下地層１０８と、ブロック層１０６と、下地層１０４とを貫通して、ドリフト層１０２に到達するゲート開口部１１０（第１の開口部）が形成されている。また、窒化物半導体装置２には、ゲート電極１１８と離間した領域に、下地層１０４に達する開口部１２０（第２の開口部）が形成されている。開口部１２０の底面には、ドリフト層１０２に達する開口部１２２（第３の開口部）が形成されている。
　チャネル形成層６１２は、窒化物半導体層６００と、電子走行層１１４と、電子供給層１１６とを備える。
　窒化物半導体層６００は、ｐ型の窒化物半導体層（第４の窒化物半導体層）であり、チャネル形成層１１２とゲート電極１１８との間に配置されている。ｐ型の窒化物半導体層６００は、例えば、ｐ型不純物を含むｐ型のＧａＮ層又はＡｌＧａＮ層である。窒化物半導体層６００を有する上記構成により、チャネル部分のポテンシャルが持ち上がるため、閾値電圧を増大させることができ、ノーマリオフ化が実現できる。
　なお、ｐ型の窒化物半導体層６００の代わりに、ＳｉＮやＳｉＯ２のような絶縁膜を挿入してもよい。つまり、チャネルのポテンシャルを持ち上げる効果がある材料であればよい。
　［４．ソース構造の変形例］
　図７は、本実施形態の変形例３に係る窒化物半導体装置の断面図である。本変形例に係る窒化物半導体装置３は、窒化物半導体装置１と比較して、ソース電極の構成が異なる。以下、窒化物半導体装置１と同じ構成は説明を省略し、窒化物半導体装置１と異なる構成を中心に説明する。
　図７に示すように、本変形例に係る窒化物半導体装置３は、基板１００と、ドリフト層１０２と、下地層１０４と、ブロック層１０６と、下地層１０８と、チャネル形成層１１２と、ゲート電極１１８と、ソース電極７００と、ドレイン電極１２６とを備える。また、窒化物半導体装置３には、下地層１０８と、ブロック層１０６と、下地層１０４とを貫通して、ドリフト層１０２に到達するゲート開口部１１０（第１の開口部）が形成されている。また、窒化物半導体装置３には、ゲート電極１１８と離間した領域に、下地層１０４に達する開口部１２０（第２の開口部）が形成されている。開口部１２０の底面には、ドリフト層１０２に達する開口部１２２（第３の開口部）が形成されている。
　本変形例において、ソース電極７００は、金属層７０２と、金属層７０２と異なる金属から構成される金属層７０４とを有している。金属層７０４は、開口部１２２において、下地層１０４およびドリフト層１０２と接する第２の金属層である。金属層７０２は、開口部１２０の側壁部１２１において二次元電子ガス（２ＤＥＧ）と接触する第１の金属層であり、金属層７０４と電気的に接続されている。金属層７０４は、アノード電極として機能する。
　金属層７０４は、Ｐｄ、Ｎｉ、Ａｕ、Ｐｔなどの少なくとも１つを含んでおり、ｐ型の窒化物半導体である下地層１０４とオーミック接触するような材料が適用される。これにより、下地層１０４との、より安定した電気的接続が可能になる。よって、逆バイアス印加時（ドレイン電極１２６に正バイアス印加時）において、下地層１０４から、より安定して空乏層を伸ばすことができるため、逆方向リークをより低減することができ、更なる高耐圧化が可能になる。
　なお、図７に示された上記変形例３と、図６に示された変形例２とを組み合わせることも可能である。
　［５．ゲート端位置と閾値電圧との関係］
　ここで、ゲート端の位置とトランジスタの閾値電圧との関係について説明する。なお、ゲート端とは、窒化物半導体装置１および３では、ゲート電極１１８とソース電極１２４との並び方向におけるゲート電極１１８の端部である。また、窒化物半導体装置２では、ゲート端とは、ゲート電極１１８とソース電極１２４との並び方向における窒化物半導体層６００の端部である。
　ゲート端の位置をゲート開口部１１０の内側に配置する場合、トランジスタの閾値電圧は、ゲート開口部１１０の側壁部１１１（側壁部２ＤＥＧ１３０）のみで決定される。この配置構成では、基板１００の主面に平行なチャネル形成層１１２の平坦部（平坦部２ＤＥＧ１３２）のキャリア濃度を大きくすることができるため、オン抵抗を低減できる。
　一方、ゲート端の位置をゲート開口部１１０の外側に配置する場合、トランジスタの閾値電圧は、ゲート開口部１１０の側壁部１１１（側壁部２ＤＥＧ１３０）の閾値電圧、または、ゲート開口部１１０の外側の平坦部（平坦部２ＤＥＧ１３２）の閾値電圧のうち大きい方となる。例えば、トランジスタの閾値電圧を平坦部で決まるようにする場合は、ゲート開口部１１０の側壁部１１１の閾値電圧だけを小さくする必要がある。この場合、基板１００の主面に平行方向の電子走行層１１４の膜厚を、ゲート開口部１１０の側壁部１１１に平行方向の電子走行層１１４の膜厚よりも小さくすればよい。これにより、ゲート開口部１１０の側壁部１１１上の２次元電子ガス（２ＤＥＧ）と下地層１０４との距離が、チャネル形成層１１２の平坦部の２次元電子ガス（２ＤＥＧ）と下地層１０４との距離よりも長くなる。
　この構成により、ゲート開口部１１０の側壁部１１１上の２次元電子ガスが、下地層１０４から延びる空乏層の影響を、平坦部に比べて低減できすることができるため、側壁部１１１上のチャネル領域の閾値電圧を選択的に小さくすることが可能になる。よって、トランジスタの閾値電圧を、チャネル形成層１１２の平坦部で決まるようにすることができる。
　［６．電子走行層の膜厚］
　一般的に、縦型デバイスにおけるＧａＮの結晶成長は、ＧａＮ結晶のｃ面が基板主面（上面）と平行になるように行われる。この場合、基板主面と平行な２次元電子ガスに比べて、基板主面から傾いた２次元電子ガスの分極は小さくなるため、その分キャリア濃度が低下する。
　この観点から、ゲート開口部１１０の側壁部１１１上に形成された２次元電子ガスである側壁部２ＤＥＧ１３０のキャリア濃度は、平坦部の２次元電子ガスである平坦部２ＤＥＧ１３２のキャリア濃度より低い。つまり、側壁部２ＤＥＧ１３０は、平坦部２ＤＥＧ１３２に比べて、下地層１０４から伸びる空乏層の狭窄効果を受けやすいため、下地層１０４から遠ざけた方が、よりオン抵抗を低減できる。
　また、ゲート開口部１１０の外側における電子走行層１１４が薄いほど、開口部１２０の深さを浅くすることができる。開口部１２０の深さが浅いほど、プロセス時間を短縮でき、かつ、ソース電極１２４を蒸着で形成する場合には、蒸着膜の段切れの発生、つまり、蒸着膜が不連続になる現象を防ぎやすくなる。
　以上より、ゲート開口部１１０の外側に配置された電子走行層１１４の膜厚が、ゲート開口部１１０の側壁部１１１上に配置された電子走行層１１４の膜厚よりも小さい方が好ましい。この構成により、プロセスを容易にしつつ、かつ、オン抵抗を低減することが可能になる。
　（その他の実施形態）
　なお、本発明に係る窒化物半導体装置は、上記実施形態およびその変形例１～３に限定されるものではない。上記実施形態および変形例における任意の構成要素を組み合わせて実現される別の実施形態や、上記実施形態および変形例に対して本発明の趣旨を逸脱しない範囲で当業者が思いつく各種変形を施して得られる変形例や、上記実施形態および変形例に係る窒化物半導体装置を内蔵した各種機器も本発明に含まれる。
　本開示に係る窒化物半導体装置は、例えば、民生機器の電源回路等で用いられるパワーデバイスとして有用である。
　１、２、３　　窒化物半導体装置
　１００　　基板
　１０２　　ドリフト層
　１０４、１０８　　下地層
　１０６　　ブロック層
　１１０　　ゲート開口部
　１１１、１２１、１２３　　側壁部
　１１２、６１２　　チャネル形成層
　１１８　　ゲート電極
　１２０、１２２　　開口部
　１２４、７００　　ソース電極
　１２６　　ドレイン電極
　１３０　　側壁部２ＤＥＧ
　１３２　　平坦部２ＤＥＧ
　６００　　窒化物半導体層
　７０２、７０４　　金属層

Claims (9)

  1. 　互いに背向する第１主面および第２主面を有する基板と、
    　前記第１主面の上に配置された第１導電型の第１の窒化物半導体層と、
    　前記第１の窒化物半導体層の上に配置された第２導電型の第２の窒化物半導体層と、
    　前記第２の窒化物半導体層に形成され、前記第１の窒化物半導体層に達する第１の開口部と、
    　前記第１の開口部を覆い、チャネル領域を有する、前記第１導電型の第３の窒化物半導体層と、
    　前記第１の開口部内の前記第３の窒化物半導体層上に配置されたゲート電極と、
    　前記ゲート電極と離間し、前記第２の窒化物半導体層に達する第２の開口部と、
    　前記第２の開口部の底面に形成され、前記第１の窒化物半導体層に達する第３の開口部と、
    　前記第２の開口部および前記第３の開口部を覆うソース電極と、
    　前記第２主面に配置されたドレイン電極と、を備える
    　窒化物半導体装置。
  2. 　前記窒化物半導体装置は、離散的に配置された複数の前記第３の開口部を備える
    　請求項１に記載の窒化物半導体装置。
  3. 　前記ドレイン電極と前記ソース電極との間に逆バイアスが印加されているとき、前記第２の開口部の下方において、前記第１の窒化物半導体層と前記第２の窒化物半導体層とによって形成された空乏層が、前記第３の開口部の底面全体に広がる
    　請求項１又は２に記載の窒化物半導体装置。
  4. 　前記第３の窒化物半導体層は、
    　窒化物半導体からなる電子走行層と、
    　前記電子走行層よりバンドギャップが大きい、窒化物半導体からなる電子供給層と、を有する
    　請求項１から３のいずれか１項に記載の窒化物半導体装置。
  5. 　前記電子供給層は、前記電子走行層の上に配置されている
    　請求項４に記載の窒化物半導体装置。
  6. 　前記基板は、窒化物半導体から構成され、
    　前記第１主面は、ｃ面であり、
    　前記第１の開口部の側壁部上に配置された前記電子走行層の膜厚は、前記第１の開口部の外側に配置された前記電子走行層の膜厚よりも大きい
    　請求項５に記載の窒化物半導体装置。
  7. 　前記ソース電極は、
    　前記電子走行層と前記電子供給層との界面に発生する２次元電子ガスに接触する第１の金属層と、
    　前記第３の開口部において、前記第１の窒化物半導体層及び第２の窒化物半導体層と接触する第２の金属層と、を有する
    　請求項４から６のいずれか１項に記載の窒化物半導体装置。
  8. 　前記第２の金属層は、前記第２の窒化物半導体層とオーミック接触する
    　請求項７に記載の窒化物半導体装置。
  9. 　さらに、
    　前記ゲート電極と前記第３の窒化物半導体層との間に配置された前記第２導電型の第４の窒化物半導体層を備える
    　請求項１から８のいずれか１項に記載の窒化物半導体装置。
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