WO2016030966A1 - 半導体素子 - Google Patents
半導体素子 Download PDFInfo
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- WO2016030966A1 WO2016030966A1 PCT/JP2014/072292 JP2014072292W WO2016030966A1 WO 2016030966 A1 WO2016030966 A1 WO 2016030966A1 JP 2014072292 W JP2014072292 W JP 2014072292W WO 2016030966 A1 WO2016030966 A1 WO 2016030966A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 description 62
- 238000011084 recovery Methods 0.000 description 23
- 238000010992 reflux Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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Definitions
- the present invention relates to a semiconductor element used for, for example, a switch, an air conditioner, a refrigerator, a washing machine, a bullet train, a train, a hybrid car, solar power or a wind power converter.
- Patent Document 1 discloses a semiconductor element in which an IGBT and a reflux diode are integrated on the same chip.
- the end portion of the cathode region is separated by 100 ⁇ m or more from the end portion of the anode region in a direction away from the IGBT portion.
- the semiconductor element in which the switching element region and the diode region are integrated on one chip is more advantageous for downsizing the device than when the switching element and the diode are separate components.
- the current flowing through the parasitic diode in the switching element region is weighted to the current flowing through the diode region.
- the recovery current becomes large.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor element that can reduce the recovery current.
- a semiconductor element includes a first conductivity type emitter region provided on the upper surface side of a first conductivity type substrate, a second conductivity type base region provided on the upper surface side of the substrate, A switching element region having an active region having a second conductivity type collector layer provided on the lower surface side of the substrate; a second conductivity type anode layer provided on the upper surface side of the substrate; A diode region having a first conductivity type cathode layer provided on the lower surface side, the cathode layer being separated from the active region in plan view, and on the upper surface side of the active region, A high-concentration region of the second conductivity type having a higher impurity concentration than the anode layer is formed.
- the cathode layer is separated from the active region in plan view, and the second conductivity type high concentration region having a higher impurity concentration than the anode layer is formed on the upper surface side of the active region, so that the characteristics of the switching element region are maintained.
- the recovery current can be reduced.
- 1 is a partial cross-sectional view of a semiconductor element according to a first embodiment.
- 1 is a plan view of a semiconductor element according to a first embodiment. It is a partial cross section figure of the semiconductor element which added the circuit symbol. It is a graph which shows the relationship between the retreat distance and the carrier concentration of the substrate in the reflux mode. It is a graph which shows the relationship between retreat distance and a recovery current.
- 6 is a partial cross-sectional view of a semiconductor element according to a second embodiment.
- FIG. It is a partial cross section figure of the semiconductor element which shows the diode produced by providing a well area
- FIG. 6 is a partial cross-sectional view of a semiconductor element according to a third embodiment.
- FIG. 1 is a partial cross-sectional view of a semiconductor element according to Embodiment 1 of the present invention.
- the semiconductor element includes a first conductivity type substrate 10.
- the substrate 10 is made of, for example, Si, GaN, or SiC.
- an active region R2 and a diode region R3 constituting a part of the switching element region R1 are formed.
- a carrier store region 12 of the first conductivity type is provided on the upper surface side of the substrate 10.
- the impurity concentration of the carrier store region 12 is higher than the impurity concentration of the substrate 10.
- a second conductivity type base region 14 located on the carrier store region 12 is provided on the upper surface side of the substrate 10.
- a first conductivity type emitter region 16 located on the base region 14 is provided on the upper surface side of the substrate 10.
- the impurity concentration of the emitter region 16 is higher than the impurity concentration of the carrier store region 12.
- a P + contact region 18 of the second conductivity type adjacent to the emitter region 16 is provided on the base region 14.
- the impurity concentration of the P + contact region 18 is higher than the impurity concentration of the base region 14.
- a trench gate electrode 20 that penetrates the carrier store region 12 and the base region 14 is provided.
- the trench gate electrode 20 is made of, for example, polysilicon.
- the side and bottom surfaces of the trench gate electrode 20 are covered with a gate insulating film 22.
- the emitter region 16, the base region 14, the carrier store region 12, and the substrate 10 are in contact with the gate insulating film 22.
- An upper surface electrode 24 is formed on the upper surface of the substrate 10.
- the aforementioned P + contact region 18 is provided between the base region 14 and the upper surface electrode 24.
- an interlayer insulating film 26 is provided between them.
- an n-channel MOSFET structure is formed on the upper surface side of the active region R2.
- a first conductivity type buffer layer 30 is provided on the lower surface side of the substrate 10.
- a collector layer 32 of the second conductivity type located under the buffer layer 30 is provided on the lower surface side of the substrate 10.
- a lower surface electrode 34 is provided on the lower surface of the collector layer 32.
- a carrier store region 12 is provided on the upper surface side of the substrate 10.
- a second conductivity type anode layer 40 located on the carrier store region 12 is provided on the upper surface side of the substrate 10.
- the impurity concentration of the anode layer 40 is lower than the impurity concentration of the base region 14 and lower than the impurity concentration of the P + contact region 18.
- the impurity concentration of the carrier store region 12 formed between the anode layer 40 and the substrate 10 is higher than the impurity concentration of the substrate 10.
- An upper surface electrode 24 is provided on the upper surface of the anode layer 40.
- a trench gate electrode 20 and a gate insulating film 22 are also provided in the diode region R3.
- the trench gate electrode 20 penetrates the anode layer 40 and the carrier store region 12.
- a first conductivity type buffer layer 30 is provided on the lower surface side of the substrate 10.
- a first conductivity type cathode layer 42 located under the buffer layer 30 is provided on the lower surface side of the substrate 10.
- the impurity concentration of the cathode layer 42 is higher than the impurity concentration of the substrate 10.
- a lower surface electrode 34 is provided on the lower surface of the cathode layer 42.
- a PIN diode is formed in the diode region R3.
- the collector layer 32 extends from the boundary between the active region R2 and the diode region R3 by a distance W1 toward the diode region R3.
- the end 42a of the cathode layer 42 is set back from the boundary by a distance W1 in a direction away from the active region R2 in plan view. This distance W1 may be referred to as a retreat distance.
- FIG. 2 is a plan view of the semiconductor element according to the first embodiment of the present invention.
- the switching element region R1 has an active region R2 and a gate region R4.
- a gate electrode is formed on the surface of the gate region R4.
- the outline of the upper surface electrode 24 is indicated by a broken line.
- the upper surface electrode 24 functions as an emitter electrode in the active region R2 and functions as an anode electrode in the diode region R3.
- the outline of the cathode layer 42 is indicated by a one-dot chain line.
- the cathode layer 42 is separated from the active region R2 by a distance W1 in plan view.
- An outer peripheral region R5 is provided on the outer periphery of the semiconductor element.
- the operation of the semiconductor element according to the first embodiment of the present invention will be described.
- electrons flow from the upper surface electrode 24 into the substrate 10 through the n-channel MOSFET in the active region R2.
- the lower surface of the substrate 10 has a structure called an anode short, and an electron current first flows from the buffer layer 30 through the cathode layer 42 to the lower surface electrode 34 (collector electrode).
- the junction between the collector layer 32 and the buffer layer 30 becomes a forward bias, holes flow from the collector layer 32 to the substrate 10 and conductivity modulation starts, and a steady state is obtained.
- An ideal ON state (steady state) of the diode is a state in which holes flow from the anode layer 40 through the carrier store region 12 to the substrate 10 and current flows into the cathode layer 42. In other words, it is ideal that the current is composed only of holes flowing from the anode layer 40 to the substrate 10.
- FIG. 3 is a partial cross-sectional view of a semiconductor element to which a circuit symbol is added.
- a current also flows through the diode D 2 including the P + contact region 18, the base region 14, the carrier store region 12, the substrate 10, and the cathode layer 42. Therefore, in the reflux mode, the current of the diode D2 is superimposed on the current of the diode D1.
- the diode OFF operation (recovery operation) starts. While the diode D2 is forward-biased, a recovery current flows from the lower electrode 34 to the upper electrode 24. After that, when the forward bias of the diode D2 disappears and the carrier inside the substrate 10 disappears, the diode D2 is turned off.
- the base region 14 and the P + contact region 18 in the active region R2 operate as anodes.
- the impurity concentration of the base region 14 and the P + contact region 18 may be lowered.
- the base region 14 is a part that determines the threshold voltage of the n-channel MOSFET, it cannot be easily reduced in concentration.
- the P + contact region 18 needs to have a high concentration in order to reduce the contact resistance, it cannot be easily reduced in concentration. If the impurity concentration of the base region 14 and the P + contact region 18 that function as the anode is high, a large number of carriers remain in the substrate 10 during recovery, and thus the recovery current increases.
- the cathode layer 42 is separated from the active region R2 in plan view in order to prevent the recovery current from increasing. Therefore, the length of the i layer of the diode D2 which is a parasitic PIN diode can be increased. Specifically, when the thickness of the substrate is d, the length of the i layer can be ⁇ (d 2 + W 1 2 ). This length is longer than the length “d” of the i layer when the cathode layer is formed up to the boundary between the diode region R3 and the active region R2. Thereby, since the current by the diode D2 can be suppressed, the recovery current can be reduced.
- the impurity concentration of the anode layer 40 is lower than the impurity concentration of the base region 14 and the impurity concentration of the P + contact region 18, the recovery current can be suppressed. By reducing the recovery current in this way, switching losses such as Eon and Err are reduced, and the breakdown tolerance is improved.
- the base region 14 and the P + contact region 18 are high concentration regions.
- either the base region 14 or the P + contact region 18 may be a high concentration region, or a region other than the base region and the P + contact region may be a high concentration region.
- FIG. 4 is a graph showing the relationship between the receding distance W1 and the carrier concentration of the substrate 10 in the reflux mode.
- FIG. 5 is a graph showing the relationship between the receding distance W1 and the recovery current.
- the lifetime in FIG. 5 refers to the lifetime of holes in the substrate 10.
- the lifetime value may be obtained by simulation, or may be obtained by a microwave photoconductive decay method (Microwave Photo Conductivity Decay method).
- FIG. 5 shows the recovery current for each of cases where the lifetime is 1 ⁇ sec, 2 ⁇ sec, and 3 ⁇ sec.
- the recovery current decreases and converges to a certain value as the backward distance W1 is increased. If the value of W1 / lifetime (the left side of / is the numerator and the right side is the denominator) is 100 or more, the recovery current can be reduced by 10 to 20% compared to the case where the value is about 50. Accordingly, the distance between the cathode layer and the active region in the plan view (retreat distance W1) is not less than the length obtained by the carrier lifetime [s] ⁇ 100 in units of seconds with the unit as meters. It is preferable.
- the value of W1 / lifetime is preferably 100 to 300.
- W1 is 1.5d or more and the W1 / lifetime value is between 100 and 300.
- the semiconductor element according to the first embodiment of the present invention can be variously modified without losing its characteristics.
- a planar gate structure may be formed in the active region.
- the n-type is the first conductivity type and the p-type is the second conductivity type, the conductivity type may be reversed.
- the positional relationship among the gate region R4, the active region R2, and the diode region R3 is not limited to the positional relationship in FIG.
- the active region R2 may be formed so as to surround the diode region R3.
- the diode region R3 may be formed so as to surround the switching element region R1.
- the diode region R3 may be formed so as to be in contact with both the active region R2 and the gate region R4.
- the carrier store region 12 and the buffer layer 30 may be omitted.
- FIG. FIG. 6 is a partial cross-sectional view of a semiconductor element according to Embodiment 2 of the present invention.
- the switching element region R1 has a gate region R4 between the active region R2 and the diode region R3.
- a gate electrode 50 is formed in the gate region R4.
- the gate electrode 50 is a portion that receives a gate drive signal from the outside.
- a gate line 52 connected to the gate electrode 50 is provided in the gate region R4.
- the gate line 52 connects the gate electrode 50 and the trench gate electrode 20.
- An insulator 54 is provided below the gate electrode 50 and the gate line 52.
- a second conductivity type well region 56 is formed in the substrate 10 of the gate region R4.
- the well region 56 is formed deeper in the substrate 10 than the anode layer 40.
- the impurity concentration of the well region 56 is higher than the impurity concentration of the anode layer 40.
- FIG. 7 is a partial cross-sectional view of the semiconductor element showing the diode D3 generated by providing the well region. Since the end portion of the cathode layer 42 is retracted in the direction away from the gate region R4 from the boundary between the gate region R4 and the diode region R3, the i layer of the diode D3 is correspondingly longer. Therefore, the recovery current can be reduced.
- each element can be optimized by providing the gate region R4 between the active region R2 and the diode region R3.
- W1 the retreat distance W1 described in the first embodiment, it is preferable to set W2 to 1.5 d or more, or set the W2 / lifetime value to a value between 100 and 300.
- FIG. FIG. 8 is a partial cross-sectional view of a semiconductor element according to Embodiment 3 of the present invention.
- the second conductivity type well region 100 is formed on the active region R2 side of the gate region R4, and is not formed on the diode region R3 side of the gate region R4.
- the trench gate electrode, the gate oxide film, and the carrier store region are not formed in the diode region R3. Therefore, only the anode layer 40 is formed on the upper surface side of the substrate 10 in the diode region R3.
- the distance between the cathode layer 42 and the well region 100 in plan view is W3. Since the well region 100 is formed only on the active region R2 side, if the end portion of the cathode layer 42 is provided at the same position as in the second embodiment, W3 becomes very long. Therefore, the recovery current can be made sufficiently small. Further, since the well region 100 is formed only on the active region R2 side, the recovery current can be sufficiently reduced even if the end portion of the cathode layer 42 is moved to the gate region R4 side.
- the well region 100 is formed on the active region R2 side, it is not necessary to significantly recede the cathode layer. Therefore, it is not necessary to make the diode region larger by the amount of retreat of the cathode layer, so that the diode region can be made smaller.
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Abstract
Description
n型の導電型のことを第1導電型と称しp型の導電型のことを第2導電型と称する。本発明の実施の形態1に係る半導体素子は、IGBTと還流用のダイオード(Free Wheeling Diode(FWD))を1チップに集積したReverse-Conducting Insulated Gate Bipolar Transistor(RC-IGBT)である。図1は、本発明の実施の形態1に係る半導体素子の一部断面図である。この半導体素子は第1導電型の基板10を備えている。基板10は例えばSi、GaN、又はSiCで形成される。この基板10に、スイッチング素子領域R1の一部を構成する活性領域R2と、ダイオード領域R3が作りこまれている。
図6は、本発明の実施の形態2に係る半導体素子の一部断面図である。スイッチング素子領域R1は、活性領域R2とダイオード領域R3の間に、ゲート領域R4を有する。ゲート領域R4にはゲート電極50が形成されている。ゲート電極50は外部からゲート駆動信号を受ける部分である。ゲート領域R4には、ゲート電極50と接続されたゲート線52が設けられている。ゲート線52はゲート電極50とトレンチゲート電極20を接続する。ゲート電極50及びゲート線52の下には絶縁体54が設けられている。ゲート領域R4の基板10には第2導電型のウェル領域56が形成されている。ウェル領域56はアノード層40よりも基板10の深い位置にまで形成されている。ウェル領域56の不純物濃度はアノード層40の不純物濃度より高い。
図8は、本発明の実施の形態3に係る半導体素子の一部断面図である。第2導電型のウェル領域100は、ゲート領域R4の活性領域R2側に形成され、ゲート領域R4のダイオード領域R3側には形成されていない。また、ダイオード領域R3には、トレンチゲート電極、ゲート酸化膜及びキャリアストア領域を形成していない。そのため、ダイオード領域R3の基板10の上面側にはアノード層40だけが形成されている。
Claims (9)
- 第1導電型の基板の上面側に設けられた第1導電型のエミッタ領域と、前記基板の上面側に設けられた第2導電型のベース領域と、前記基板の下面側に設けられた第2導電型のコレクタ層と、を有する活性領域を備えたスイッチング素子領域と、
前記基板の上面側に設けられた第2導電型のアノード層と、前記基板の下面側に設けられた第1導電型のカソード層と、を有するダイオード領域と、を備え、
前記カソード層は、平面視で前記活性領域から離れており、
前記活性領域の上面側には、前記アノード層よりも不純物濃度が高い第2導電型の高濃度領域が形成されたことを特徴とする半導体素子。 - 前記高濃度領域は、前記ベース領域であることを特徴とする請求項1に記載の半導体素子。
- 前記基板の上面に形成された上面電極と、
前記ベース領域と前記上面電極の間に設けられた、前記ベース領域よりも不純物濃度が高い第2導電型のP+コンタクト領域と、を備え、
前記高濃度領域は前記P+コンタクト領域であることを特徴とする請求項1に記載の半導体素子。 - 平面視での、前記カソード層と前記活性領域との距離は、単位をメートルとして、前記基板における秒を単位としたキャリアのライフタイム×100で得られる長さ以上であることを特徴とする請求項1~3のいずれか1項に記載の半導体素子。
- 平面視での、前記カソード層と前記活性領域との距離は、前記基板の厚さの1.5倍以上であることを特徴とする請求項1~4のいずれか1項に記載の半導体素子。
- 前記スイッチング素子領域は、前記活性領域と前記ダイオード領域の間に、ゲート電極とゲート線が形成されたゲート領域を有することを特徴とする請求項1~5のいずれか1項に記載の半導体素子。
- 前記ゲート領域の前記基板に形成された第2導電型のウェル領域を備え、
前記カソード層は、平面視で前記ウェル領域から離れたことを特徴とする請求項6に記載の半導体素子。 - 前記ウェル領域は、前記ゲート領域の前記活性領域側に形成され、前記ゲート領域の前記ダイオード領域側には形成されないことを特徴とする請求項7に記載の半導体素子。
- 前記アノード層と前記基板の間に、前記基板よりも不純物濃度の高い第1導電型のキャリアストア領域を備えたことを特徴とする請求項1~8のいずれか1項に記載の半導体素子。
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JP7095303B2 (ja) | 2018-02-14 | 2022-07-05 | 富士電機株式会社 | 半導体装置 |
JP2019140322A (ja) * | 2018-02-14 | 2019-08-22 | 富士電機株式会社 | 半導体装置 |
JPWO2019220940A1 (ja) * | 2018-05-17 | 2020-12-10 | 富士電機株式会社 | 半導体装置 |
US11276771B2 (en) | 2018-05-17 | 2022-03-15 | Fuji Electric Co., Ltd. | Semiconductor device |
JP6996621B2 (ja) | 2018-05-17 | 2022-01-17 | 富士電機株式会社 | 半導体装置 |
WO2019220940A1 (ja) * | 2018-05-17 | 2019-11-21 | 富士電機株式会社 | 半導体装置 |
JP7158317B2 (ja) | 2019-03-07 | 2022-10-21 | 三菱電機株式会社 | 半導体装置 |
JP2020145341A (ja) * | 2019-03-07 | 2020-09-10 | 三菱電機株式会社 | 半導体装置 |
JP7204544B2 (ja) | 2019-03-14 | 2023-01-16 | 株式会社東芝 | 半導体装置 |
JP2020150159A (ja) * | 2019-03-14 | 2020-09-17 | 株式会社東芝 | 半導体装置 |
JP2020202224A (ja) * | 2019-06-07 | 2020-12-17 | 三菱電機株式会社 | 半導体装置 |
JP7118033B2 (ja) | 2019-06-07 | 2022-08-15 | 三菱電機株式会社 | 半導体装置 |
JP7396037B2 (ja) | 2019-12-25 | 2023-12-12 | 株式会社デンソー | 半導体装置 |
DE112020002890T5 (de) | 2020-01-17 | 2022-02-24 | Fuji Electric Co., Ltd. | Halbleitervorrichtung |
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CN106796938B (zh) | 2019-11-05 |
DE112014006895B4 (de) | 2024-05-29 |
JPWO2016030966A1 (ja) | 2017-04-27 |
US20170162560A1 (en) | 2017-06-08 |
DE112014006895T5 (de) | 2017-05-11 |
KR101921844B1 (ko) | 2019-02-13 |
JP6274318B2 (ja) | 2018-02-07 |
KR20170036063A (ko) | 2017-03-31 |
US10361191B2 (en) | 2019-07-23 |
CN106796938A (zh) | 2017-05-31 |
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