JP7118033B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7118033B2 JP7118033B2 JP2019106712A JP2019106712A JP7118033B2 JP 7118033 B2 JP7118033 B2 JP 7118033B2 JP 2019106712 A JP2019106712 A JP 2019106712A JP 2019106712 A JP2019106712 A JP 2019106712A JP 7118033 B2 JP7118033 B2 JP 7118033B2
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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Description
以下、図面を参照しながら実施の形態1~実施の形態4について説明する。図面は模式的に示されたものであるため、サイズ及び位置の相互関係は適宜変更し得る。以下の説明では、同じまたは対応する構成要素には同じ符号を付与し、繰り返しの説明を省略する場合がある。半導体の導電型について、第1の導電型をN型、第2の導電型をP型として説明を行う。しかし、これらを反対にして第1の導電型をP型、第2の導電型をN型としてもよい。N+型はN型よりもドナー不純物の濃度が高く、N-型はN型よりもドナー不純物の濃度が低いことを意味する。同様に、P+型はP型よりもアクセプタ不純物の濃度が高く、P-はP型よりもアクセプタ不純物の濃度が低いことを意味する。
図1はこの発明の実施の形態1である半導体装置1の構造を示す断面図である。実施の形態1の半導体装置1はRC-IGBTである。図1にはXYZ直交座標系を記している。後に示す図2,図4~図8においてもXYZ直交座標系を記している。
図4はこの発明の実施の形態2である半導体装置2の構造を示す断面図である。実施の形態2の半導体装置2は実施の形態1と同様、RC-IGBTである。
(基本例)
図5はこの発明の実施の形態3の基本例である半導体装置3Aの構造を示す断面図である。実施の形態3の半導体装置3Aは実施の形態1と同様、RC-IGBTである。
図6はこの発明の実施の形態3の変形例である半導体装置3Bの構造を示す断面図である。実施の形態3の半導体装置3Bは実施の形態1と同様、RC-IGBTである。
(基本例)
図7はこの発明の実施の形態4の基本例である半導体装置4Aの構造を示す断面図である。実施の形態4の半導体装置4Aは実施の形態1と同様、RC-IGBTである。
図8はこの発明の実施の形態4の変形例である半導体装置4Bの構造を示す断面図である。実施の形態4の半導体装置4Bは実施の形態1と同様、RC-IGBTである。
Claims (6)
- 内部にIGBTを有するIGBT領域と、内部にMOSFETを有するMOSFET領域とを含んで構成される半導体装置であって、
第1及び第2の主面を有する半導体基板と、
前記半導体基板に設けられる第1の導電型のドリフト層とを備え、
前記IGBT領域は、
前記半導体基板に設けられ、前記ドリフト層に対し前記第1の主面側に隣接して配置される第2の導電型のベース層と、
前記第1の主面側から前記ベース層を貫通して前記ドリフト層の一部に達する領域に、絶縁膜を介して埋め込まれたトレンチゲートとを含み、
前記MOSFET領域は、
前記半導体基板に設けられ、前記ドリフト層の上層部に選択的に設けられる、第2の導電型のチャネル含有領域と、
前記チャネル含有領域の上層部に選択的に設けられる第1の導電型のMOS用電極領域とを含み、前記MOS用電極領域が形成されていない前記チャネル含有領域の上層部の少なくとも一部がチャネル領域として規定され、
前記チャネル領域上にゲート絶縁膜を介して設けられる平面ゲートをさらに含み、
前記チャネル領域、前記ゲート絶縁膜及び前記平面ゲートを含んで第1の導電型のMOSFETが構成され、
前記トレンチゲートは前記IGBT領域と前記MOSFET領域との境界に存在する境界トレンチゲートを含み、
前記チャネル含有領域は、前記境界トレンチゲートに側面が接触するトレンチゲート隣接領域を含み、
前記トレンチゲート隣接領域の形成深さは、前記境界トレンチゲートの形成深さより深いことを特徴する、
半導体装置。 - 請求項1記載の半導体装置であって、
前記チャネル含有領域は、互いに離散して設けられる複数のチャネル含有領域を含み、
前記MOSFET領域は、
前記複数のチャネル含有領域間の前記ドリフト層の上層部に設けられる、第1の導電型の少なくとも一つの上層拡散領域をさらに備え、
前記チャネル領域、前記ゲート絶縁膜及び前記平面ゲートに加え、前記MOS用電極領域及び前記少なくとも一つの上層拡散領域を含んで前記MOSFETが構成され、
前記少なくとも一つの上層拡散領域は前記ドリフト層に比べ、第1の導電型の不純物濃度が高く、
前記少なくとも一つの上層拡散領域の形成深さは、前記複数のチャネル含有領域の形成深さより浅いことを特徴する、
半導体装置。 - 請求項1または請求項2記載の半導体装置であって、
前記チャネル含有領域は、第2の導電型の第1の部分拡散領域と、前記第1の部分拡散領域に側面が接触して設けられる第2の導電型の第2の部分拡散領域とを含み、前記第1の部分拡散領域は前記トレンチゲート隣接領域を含み、
前記MOS用電極領域が形成されていない前記第2の部分拡散領域の上層部が前記チャネル領域として規定され、
前記第2の部分拡散領域の形成深さは、前記第1の部分拡散領域の形成深さより浅いことを特徴する、
半導体装置。 - 請求項2記載の半導体装置であって、
前記複数のチャネル含有領域は、複数の第1及び第2の部分拡散領域を含み、前記複数の第1及び第2の部分拡散領域のうち、対応する第1及び第2の部分拡散領域は側面が接触して一体的に前記チャネル含有領域を構成し、
前記複数の第1の部分拡散領域は前記トレンチゲート隣接領域を含み、
前記複数の第2の部分拡散領域の形成深さは、前記少なくとも一つの上層拡散領域の形成深さより浅いことを特徴する、
半導体装置。 - 請求項1記載の半導体装置であって、
前記チャネル含有領域は、互いに離散した複数のチャネル含有領域を含み、
前記MOSFET領域は、
前記複数のチャネル含有領域間の前記ドリフト層の上層部に前記複数のチャネル含有領域に接触することなく設けられる、第2の導電型の少なくとも一つの上層ダミー領域をさらに備え、
前記少なくとも一つの上層ダミー領域は電気的にフローティングに設定される、
半導体装置。 - 請求項5記載の半導体装置であって、
前記少なくとも一つの上層ダミー領域は、前記半導体基板の前記第1の主面を基準とした“0”でない有意な埋込深さに、その表面が位置するように、前記ドリフト層の内部に形成され、
前記ドリフト層はその上方に前記平面ゲートが存在するゲート下領域を有する、
半導体装置。
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