WO2015096438A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

Info

Publication number
WO2015096438A1
WO2015096438A1 PCT/CN2014/081130 CN2014081130W WO2015096438A1 WO 2015096438 A1 WO2015096438 A1 WO 2015096438A1 CN 2014081130 W CN2014081130 W CN 2014081130W WO 2015096438 A1 WO2015096438 A1 WO 2015096438A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
patterned metal
metal layer
array substrate
insulating layer
Prior art date
Application number
PCT/CN2014/081130
Other languages
English (en)
French (fr)
Inventor
姚星
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/409,217 priority Critical patent/US10317758B2/en
Publication of WO2015096438A1 publication Critical patent/WO2015096438A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device having the array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • each gate line needs to be connected to a corresponding gate driving circuit to drive each of the display areas.
  • a thin film transistor provided in the pixel unit to realize image display.
  • the Gate Driver on Array (GOA) technology is a gate drive circuit technology commonly used in the field of TFT-LCD technology. The technology is to directly fabricate the gate drive circuit in the GOA region on the array substrate. , instead of an external driver chip.
  • the wiring of the gate driving circuit in the GOA region known by the inventors is completed by two layers of metal lines by using a metal in the same layer as the gate driving element in the GOA region, for example, the gate and source/drain of the thin film transistor.
  • the wiring of the gate drive circuit connection line is performed.
  • the wiring spacing in the GOA area known by the inventors is wide, and therefore the width of the GOA area is large, which has limitations in the design of the narrow frame.
  • the same layer of metal wires are easily crossed, or the pitch of the same layer of metal wires is too small to easily cause a short circuit.
  • Embodiments of the present invention provide an array substrate and a display device having the same, which can meet the design requirements of a narrow bezel, and avoid the problem that the metal lines intersect in the gate driving circuit region and the pitch is too small to be short-circuited.
  • an embodiment of the present invention provides an array substrate, including: a display area; a non-display area disposed at a periphery of the display area, including: a gate driving circuit region (GOA region), including: a first patterned metal layer Formed on the base substrate; a first insulating layer formed on the first patterned metal layer; a second patterned metal layer formed on the first insulating layer; and a second insulating layer covering the a second patterned metal layer; a third patterned metal layer formed on the second insulation a side of the layer facing away from the base substrate, the third patterned metal layer includes a plurality of metal lines insulated from each other, the plurality of metal lines being respectively connected to the first patterned metal layer and the via through via holes The patterned second patterned metal layer is used as a connection line between the elements in the gate driving circuit.
  • GOA region gate driving circuit region
  • an embodiment of the present invention further provides a display device comprising: an array substrate, as described above; and an opposite substrate, the pair of the substrate and the array substrate.
  • FIG. 1 is a schematic cross-sectional view showing an exemplary structure of a GOA region of an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view showing an exemplary cross-sectional structure of a GOA region of an array substrate according to a second embodiment of the present invention
  • Fig. 3 is a schematic cross-sectional view showing an outline of a GOA region of an array substrate according to a third embodiment of the present invention. detailed description
  • An embodiment of the present invention provides an array substrate, including: a display area; and a non-display area disposed around the display area, including: a gate driving circuit area (GOA area).
  • GOA area gate driving circuit area 1 shows an exemplary cross-sectional view of a GOA region. As shown in FIG.
  • the GOA region includes: a first patterned metal layer 1 formed on the base substrate 10; a first insulating layer 2 formed in the a first patterned metal layer 1; a second patterned metal layer 3 formed on the first insulating layer 2; a second insulating layer 4 covering the second patterned metal layer 3, wherein The second insulating layer 4 faces away from the base
  • a third patterned metal layer 5 is formed on one side of the base substrate 10, and the third patterned metal layer 5 includes a plurality of metal lines insulated from each other, and the plurality of metal lines are respectively connected to the first pattern through via holes.
  • the metal layer 1 and the second patterned metal layer 2 serve as a connection line between elements in the gate driving circuit.
  • At least one of the plurality of metal lines is used to connect the first patterned metal layer and the second patterned metal layer; or the plurality of metal lines are used to connect the a first patterned metal layer and the second patterned metal layer.
  • FIG. 1 exemplarily shows that one metal line connection in the third patterned metal layer 5 is located at the gate of the first patterned metal layer 1 and another source/drain of the second patterned metal layer 2,
  • the plurality of metal lines further include a metal line and/or one end connected to one of the first patterned metal layers and the other end to another one of the first patterned metals.
  • a metal line connected to one of the second patterned metal layers and the other end to the other of the second patterned metal.
  • the driving element provided in the GOA region is, for example, a thin film transistor.
  • the first patterned metal layer 1 includes a gate
  • the first insulating layer 2 is a gate insulating layer
  • the metal layer 3 includes a source/drain
  • the second insulating layer 4 is a passivation layer.
  • a patterned active layer is disposed in the GOA region, disposed between the first insulating layer and the second patterned metal layer, for forming a channel of the thin film transistor.
  • the driving element provided in the GOA region is, for example, a thin film transistor.
  • the first patterned metal layer 1 includes a source/drain
  • the first insulating layer 2 is a gate insulating layer.
  • the second patterned metal layer 3 includes a gate electrode
  • the second insulating layer 4 is a passivation layer.
  • a patterned active layer is further disposed in the GOA region, disposed between the first patterned metal layer and the first insulating layer.
  • FIG. 1 is only an example and does not limit the embodiment of the present invention.
  • the plurality of metal lines are insulated by an insulating layer 9, which is coplanar with the third patterned metal layer 5.
  • the array substrate of the embodiment of the present invention has a third patterned metal layer added to the GOA region, and the connection line of the components in the gate driving circuit and part or all of the signal lines of the gate driving circuit can use the third patterned metal layer.
  • a metal wire whereby the position of the signal line and the connection line can be moved from the original component to the upper layer of the component, and a metal wire is connected to the first patterned metal layer of the gate driving circuit and the second through the via hole
  • a transparent conductive layer 7 is further formed between the second insulating layer 4 and the third patterned metal layer 5.
  • the array substrate includes a first patterned metal layer 1, a first insulating layer 2, a second patterned metal layer 3, a second insulating layer 4, and a transparent conductive layer formed on a GOA region on the base substrate 10.
  • a layer 7 and a third patterned metal layer 5 the third patterned metal layer 5 includes a plurality of metal lines insulated from each other and respectively connecting the first patterned metal layer 1 and the second patterned metal layer through via holes 3.
  • the transparent conductive layer is conformal to the plurality of metal lines in the third patterned metal layer.
  • the present embodiment is based on the structure of the third embodiment, in the second insulating layer 4 and A third insulating layer 6 is further formed between the transparent conductive layers 7, wherein a via hole is formed in the third insulating layer 6, and the third insulating layer 6 has a thickness of 1 to 2 ⁇ m.
  • the capacitance between the third patterned metal layer and the thin film transistor device in the GOA region can be effectively reduced, and the feasibility of the processing can be ensured (the thickness of the third insulating layer is too large, resulting in difficulty in processing) and The effect of the array substrate. As shown in FIG.
  • the array substrate includes a first patterned metal layer 1, a first insulating layer 2, a second patterned metal layer 3, a second insulating layer 4, and a third formed on a GOA region on the base substrate 10.
  • the difference between the present embodiment and the third embodiment is that the array substrate does not include the transparent conductive layer 7, and the via hole is formed between the second insulating layer 4 and the third patterned metal layer 5.
  • a fifth embodiment of the present invention provides a display device, comprising: the array substrate according to any one of the first embodiment to the fourth embodiment; and a counter substrate opposite to the array substrate.
  • the display device may be a liquid crystal television, a smart phone, a tablet, or the like.
  • the material of the metal line in the third patterned metal layer is generally used in the art, such as a gate metal and a source/drain metal, etc.
  • the selection is made by those skilled in the art, and the embodiment of the present invention is not particularly limited.
  • the array substrate according to the embodiment of the invention is provided with a third patterned metal layer in the GOA region, and the connection line of the components in the gate driving circuit and part or all of the signal lines of the gate driving circuit may be used in the third patterned metal layer.
  • a metal wire whereby the position of the signal line and the connecting line can be moved from the same component to the upper layer of the component, and a metal wire is connected to the first patterned metal layer and the second pattern of the gate driving circuit through the via hole
  • the metal layer can greatly reduce the area of the GOA area. Further, by adding a thicker resin (ie, a third insulating layer) between the third patterned metal layer and the first patterned metal layer and the second patterned metal layer metal, the coupling capacitance is reduced, and the display is further improved. quality.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及具有该阵列基板的显示装置。该阵列基板包括：显示区域；非显示区域，设置在显示区域周边，包括：栅极驱动电路区域，即GOA区域，包括：第一图案化金属层（1），形成在基底基板（10）上；第一绝缘层（2），形成在所述第一图案化金属层（1）上；第二图案化金属层（3），形成在所述第一绝缘层（2）上；第二绝缘层（4），覆盖所述第二图案化金属层（3）；第三图案化金属层（5），形成在所述第二绝缘层（4）的背离所述基底基板（10）的一侧，所述第三图案化金属层（5）包括彼此绝缘的多条金属线，所述多条金属线分别通过过孔连接到所述第一图案化金属层（1）和所述第二图案化金属层（3），用作所述栅极驱动电路中元件之间的连接线。通过在GOA区域中设置包括多条金属线的第三图案化金属层（5），从而有效减少了GOA走线所占空间，减小了GOA区域宽度，实现了窄边框设计。

Description

阵列基板及显示装置 技术领域
本发明的实施例涉及一种阵列基板及具有该阵列基板的显示装置。 背景技术
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )是目前常见的液晶显示器， 在 TFT-LCD中， 每一栅线都需要连 接到相应的栅极驱动电路以驱动显示区域中每个像素单元中设置的薄膜晶体 管， 以实现图像显示。 阵列基板栅极驱动电路（Gate Driver on Array, GOA ) 技术是目前 TFT-LCD技术领域常用的一种栅极驱动电路技术， 该技术是将 栅极驱动电路直接制作在阵列基板上的 GOA区域中， 代替外接的驱动芯片。
发明人已知的 GOA区域中栅极驱动电路的布线是由两层金属线完成， 通过用与 GOA区域中的栅极驱动元件， 例如， 薄膜晶体管的栅极和源 /漏极 同层的金属进行栅极驱动电路连接线的布线。
然而， 为了避免同层金属线交叉或者间距太小引起短路， 发明人已知的 GOA区域中的布线间距都较宽， 因此 GOA区域宽度较大， 在窄边框的设计 中具有局限性。 而且， 其中同层金属线容易交叉， 或者同层金属线的间距过 小而容易引起电路短路。 发明内容
本发明的实施例提供一种阵列基板及具有该阵列基板的显示装置， 能满 足窄边框的设计要求， 且避免了栅极驱动电路区域中金属线交叉以及间距过 小容易短路的问题。
一方面， 本发明的实施例提供了一种阵列基板， 包括： 显示区域； 非显 示区域， 设置在显示区域周边， 包括： 栅极驱动电路区域（GOA区域）， 包 括： 第一图案化金属层， 形成在基底基板上； 第一绝缘层， 形成在所述第一 图案化金属层上； 第二图案化金属层， 形成在所迷第一绝缘层上； 第二绝缘 层， 复盖所述第二图案化金属层； 第三图案化金属层， 形成在所述第二绝缘 层的背离所述基底基板的一侧， 所述第三图案化金属层包括彼此绝缘的多条 金属线， 所述多条金属线分别通过过孔连接到所述第一图案化金属层和所述 图案化第二图案化金属层， 用作所述栅极驱动电路中元件之间的连接线。
另一方面， 本发明的实施例还提供一种显示装置， 包括： 阵列基板， 如 以上所述； 以及对置基板， 与所述阵列基板对盒。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是本发明第一实施例提供的阵列基板的 GOA区域的示例性截面结 构示意图；
图 2是本发明第二实施例提供的阵列基板的 GOA区域的示例性截面结 构示意图； 以及
图 3是本发明第三实施例提供的阵列基板的 GOA区域的示例性截面结 构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
第一实施例
本发明实施例提供了一种阵列基板， 包括： 显示区域； 非显示区域， 设 置在显示区域周边， 包括： 栅极驱动电路区域（GOA 区域） 。 图 1 示出了 GOA区域的示例性截面示意图， 如图 1所示， GOA区域包括： 第一图案化 金属层 1， 形成在所述基底基板 10上； 第一绝缘层 2， 形成在所述第一图案 化金属层 1上； 第二图案化金属层 3， 形成在所述第一绝缘层 2上； 第二绝 缘层 4，覆盖所述第二图案化金属层 3，其中在所述第二绝缘层 4背离所述基 底基板 10的一侧形成有第三图案化金属层 5，所述第三图案化金属层 5包括 彼此绝缘的多条金属线， 所述多条金属线分别通过过孔连接到第一图案化金 属层 1和所述第二图案化金属层 2， 用作所述栅极驱动电路中元件之间的连 接线。 由此， 通过将栅极驱动电路的引线设置在第三图案化金属层中， 从而 有效减少了 GOA走线所占空间， 减小了 GOA区域宽度， 满足了窄边框的设 计要求。
示例性地， 所述多条金属线中至少有一条金属线用于连接所述第一图案 化金属层和所述第二图案化金属层； 或者所述多条金属线都用于连接所述第 一图案化金属层和所述第二图案化金属层。
图 1中示例性地示出了第三图案化金属层 5中的一条金属线连接位于第 一图案化金属层 1的栅极与位于第二图案化金属层 2的另一源 /漏极，但是这 仅是示例， 实际中第三图案化金属层 5可以进行多种连接。
备选地， 多条金属线中还包括一端连接到所述第一图案化金属层中一图 案金属而另一端连接到所述第一图案化金属中另一图案金属的金属线和 /或 一端连接到所述第二图案化金属层中一图案金属而另一端连接到所述第二图 案化金属中另一图案金属的金属线。
示例性地， GOA区域中设置的驱动元件例如是薄膜晶体管， 当该薄膜晶 体管为底栅型时，第一图案化金属层 1包括栅极，第一绝缘层 2为栅绝缘层， 第二图案化金属层 3包括源 /漏极，第二绝缘层 4为钝化层。此外，其中 GOA 区域中还设置有图案化有源层， 设置在第一绝缘层与所述第二图案化金属层 之间， 用于形成薄膜晶体管的沟道。
示例性地， GOA区域中设置的驱动元件例如是薄膜晶体管， 当该薄膜晶 体管为顶栅型时， 第一图案化金属层 1包括源 /漏极， 第一绝缘层 2为栅绝缘 层，第二图案化金属层 3包括栅极，第二绝缘层 4为钝化层。此外，其中 GOA 区域中还设置有图案化有源层， 设置在第一图案化金属层与所述第一绝缘层 之间。
示例性地， 当 GOA区域中设置有多个薄膜晶体管时， 如图 1所示， 第 三图案化金属层中至少有一条金属线用于连接一个薄膜晶体管的栅极和另一 个薄膜晶体管的源 /漏极， 当然， 第三图案化金属层中的一条金属线可以根据 GOA 电路的需要而连接第一图案化金属层中的图案金属与第二图案化金属 层中的图案金属， 本领域的技术人员可以根据实际需要进行选择， 图 1仅是 给出了一个示例， 并不对本发明的实施例进行限制。
备选地， 所述多条金属线之间通过绝缘层 9绝缘， 所述绝缘层 9与所述 第三图案化金属层 5共面。
这样， 本发明实施例的阵列基板在 GOA区域加设了第三图案化金属层， 栅极驱动电路中元件的连接线和栅极驱动电路部分或全部信号线可以釆用第 三图案化金属层中的金属线， 由此， 可将信号线和连接线的位置从原来的元 件同层移动到元件上方， 并且一条金属线通过过孔连接栅极驱动电路的第一 图案化金属层和第二图案化金属层， 可大大减小 GOA区域的面积。
第二实施例
由于第三图案化金属层 5通过过孔分别连接至第一图案化金属层 1和第 二图案化金属层 3， 因此， 为了避免第三图案化金属层 5在过孔处折断， 本 实施例在第一实施例结构的基础上， 在所述第二绝缘层 4和所述第三图案化 金属层 5之间还形成有透明导电层 7。
如图 2所示， 阵列基板包括在衬底基板 10上的 GOA区域形成的第一图 案化金属层 1、 第一绝缘层 2、 第二图案化金属层 3、 第二绝缘层 4、 透明导 电层 7和第三图案化金属层 5， 第三图案化金属层 5包括彼此绝缘的多条金 属线并且通过过孔分别连接所述第一图案化金属层 1和所述第二图案化金属 层 3。 通过增加的透明导电层 7作为第三图案化金属层 5的过渡层， 避免了 第三图案化金属层 5在过孔处的折断。
示例性地， 所述透明导电层与所述第三图案化金属层中的所述多条金属 线共形。
第三实施例
为了降低第三图案化金属层 5和第二图案化金属层 3以及第一图案化金 属层 1之间的电容， 本实施例在第三实施例的结构基础上， 在第二绝缘层 4 和透明导电层 7之间还形成有第三绝缘层 6， 其中， 该第三绝缘层 6中形成 有过孔， 该第三绝缘层 6的厚度为 1~2μπι。 在该厚度范围内， 能够有效降低 第三图案化金属层与 GOA区域中薄膜晶体管器件之间的电容， 又能确保其 加工的可行性（第三绝缘层的厚度太大导致加工难度大）及阵列基板的使用 效果。 如图 3所示， 阵列基板包括在衬底基板 10上的 GOA区域形成的第一图 案化金属层 1、 第一绝缘层 2、 第二图案化金属层 3、 第二绝缘层 4、 第三绝 缘层 6、透明导电层 7和第三图案化金属层 5，第三图案化金属层 5包括彼此 绝缘的多条金属线， 并且通过过孔分别连接所述第一图案化金属层 1和所述 第二图案化金属层 3。 通过增加的第三绝缘层 6， 降低了第三图案化金属层 5 和第一图案化金属层 1以及第二图案化金属层 3之间的寄生电容， 减少了信 号受到的干扰， 增强了显示质量。
第四实施例
本实施例与第三实施例相比， 区别点仅在于所述阵列基板不包括透明导 电层 7， 在第二绝缘层 4和第三图案化金属层 5之间直接形成其中形成有过 孔的第三绝缘层 6。
第五实施例
本发明的第五实施例提供了一种显示装置， 包括： 上述第一实施例 -第四 实施例中任一实施例的所述阵列基板；以及与所述阵列基板对盒的对置基板。 所述显示装置可以是液晶电视、 智能手机、 平板电脑等等。
示例性地， 在根据本发明实施例的技术方案中， 第三图案化金属层中的 金属线的材质釆用本领域常规使用的即可， 如栅极金属和源 /漏极金属等， 具 体的选择为本领域技术人员所掌握， 本发明的实施例对此不作特别限定。
根据本发明实施例的阵列基板在 GOA区域加设了第三图案化金属层， 栅极驱动电路中元件的连接线和栅极驱动电路部分或全部信号线可以釆用第 三图案化金属层中的金属线， 由此， 可将信号线和连接线的位置从原来的元 件同层移动到元件上方， 并一条金属线通过过孔连接栅极驱动电路的第一图 案化金属层和第二图案化金属层， 可大大减小 GOA区域的面积。 进一步地， 通过在第三图案化金属层与第一图案化金属层和第二图案化金属层金属之间 加入较厚的树脂 （即第三绝缘层） ， 降低了耦合电容， 进一步提高了显示质 量。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。 本申请要求于 2013年 12月 26日递交的中国专利申请第 201310731356.8 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板， 包括：
显示区域；
非显示区域， 设置在显示区域周边， 包括：
栅极驱动电路区域（GOA区域） ， 包括：
第一图案化金属层， 形成在基底基板上；
第一绝缘层， 形成在所述第一图案化金属层上； 第二图案化金属层， 形成在所述第一绝缘层上； 第二绝缘层， 覆盖所述第二图案化金属层；
第三图案化金属层， 形成在所述第二绝缘层的背离所述基底基 板的一侧， 所述第三图案化金属层包括彼此绝缘的多条金属线， 所述多条金 属线分别通过过孔连接到所述第一图案化金属层和所述图案化第二图案化金 属层， 用作所述栅极驱动电路中元件之间的连接线。
2、 如权利要求 1 所述的阵列基板， 其中所述多条金属线中至少有一条 金属线用于连接所述第一图案化金属层和所述第二图案化金属层。
3、 如权利要求 2所述的阵列基板， 其中多条金属线中还包括一端连接 到所述第一图案化金属层中一图案金属而另一端连接到所述第一图案化金属 中另一图案金属的金属线和 /或一端连接到所述第二图案化金属层中一图案 金属而另一端连接到所述第二图案化金属中另一图案金属的金属线。
4、 如权利要求 1 所述的阵列基板， 其中所述多条金属线都用于连接所 述第一图案化金属层和所述第二图案化金属层。
5、如权利要求 1-4中任一项所述的阵列基板， 其中透明导电层形成在所 述第二绝缘层和所述第三图案化金属层之间。
6、如权利要求 1-5中任一项所述的阵列基板， 其中在所述第二绝缘层和 所述透明导电层之间还形成有第三绝缘层， 所述第三绝缘层中形成有过孔。
7、如权利要求 6所述的阵列基板，其中所述第三绝缘层的厚度为 1~2μπι。
8、如权利要求 1所述的阵列基板，其中所述多条金属线还包括所述栅极 驱动电路的部分时钟信号线。
9、如权利要求 1-4中任一项所述的阵列基板， 其中所述第一图案化金属 层包括多个栅极， 第一绝缘层为栅绝缘层， 第二图案化金属层包括多个源 / 漏极， 第二绝缘层为钝化层。
10、如权利要求 9所述的阵列基板，其中所述栅极驱动电路区域还包括： 图案化有源层， 设置在第一绝缘层与所述第二图案化金属层之间。
11、 如权利要求 5所述的阵列基板， 其中所述透明导电层与所述第三图 案化金属层中的所述多条金属线共形。
12、 如权利要求 1-4中任一项所述的阵列基板， 其中所述第一图案化金 属层包括多个源 /漏极， 第一绝缘层为栅绝缘层， 第二图案化金属层包括多个 栅极， 第二绝缘层为钝化层。
13、如权利要求 12所述的阵列基板，其中所述栅极驱动电路区域还包括： 图案化有源层， 设置在第一图案化金属层与所述第一绝缘层之间。
14、如权利要求 1-13中任一项所述的阵列基板， 其中所述多条金属线之 间通过绝缘层绝缘， 所述绝缘层与所述第三图案化金属层共面。
15、如权利要求 9或 10所述的阵列基板，其中至少一条所述金属线用于 连接一个栅极与对应于另一栅极的所述源 /漏极；或者至少一条金属线用于连 接一个栅极与对应于该栅极的所述源 /漏极。
16、 一种显示装置， 包括：
阵列基板， 如权利要求 1~15中任一项所述；
对置基板， 与所述阵列基板对盒。
PCT/CN2014/081130 2013-12-26 2014-06-30 阵列基板及显示装置 WO2015096438A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/409,217 US10317758B2 (en) 2013-12-26 2014-06-30 Array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310731356.8A CN103676382B (zh) 2013-12-26 2013-12-26 阵列基板及显示装置
CN201310731356.8 2013-12-26

Publications (1)

Publication Number Publication Date
WO2015096438A1 true WO2015096438A1 (zh) 2015-07-02

Family

ID=50314410

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/081130 WO2015096438A1 (zh) 2013-12-26 2014-06-30 阵列基板及显示装置

Country Status (3)

Country Link
US (1) US10317758B2 (zh)
CN (1) CN103676382B (zh)
WO (1) WO2015096438A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103676382B (zh) * 2013-12-26 2017-03-08 京东方科技集团股份有限公司 阵列基板及显示装置
CN104460154A (zh) * 2014-12-15 2015-03-25 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN107170757B (zh) * 2017-05-25 2019-09-24 深圳市华星光电技术有限公司 一种阵列基板及其制作方法
CN107689196A (zh) * 2017-09-05 2018-02-13 信利（惠州）智能显示有限公司 一种amoled显示屏及其布线方法
US11119369B1 (en) 2018-11-29 2021-09-14 HKC Corporation Limited Array substrate and display panel
CN109993156B (zh) * 2019-04-24 2022-09-06 京东方科技集团股份有限公司 超声波指纹识别面板及显示装置
CN110568686A (zh) * 2019-08-08 2019-12-13 深圳市华星光电半导体显示技术有限公司 阵列基板及显示面板
CN110941124B (zh) * 2019-12-02 2021-06-01 Tcl华星光电技术有限公司 一种阵列基板、阵列基板制程方法及显示面板
CN111077707A (zh) 2019-12-18 2020-04-28 Tcl华星光电技术有限公司 一种阵列基板和显示面板
CN111223439A (zh) * 2020-03-12 2020-06-02 深圳市华星光电半导体显示技术有限公司 应用于阵列基板的goa电路、阵列基板及goa电路的制作方法
CN111292679A (zh) * 2020-03-18 2020-06-16 Tcl华星光电技术有限公司 显示面板及显示装置
CN112002733B (zh) * 2020-08-06 2023-12-01 武汉华星光电半导体显示技术有限公司 Oled显示装置及制备方法
CN111929954A (zh) * 2020-08-19 2020-11-13 惠科股份有限公司 显示装置
CN114967255B (zh) * 2022-04-07 2023-10-10 滁州惠科光电科技有限公司 阵列基板、显示面板和阵列基板的制作方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1517751A (zh) * 2003-01-08 2004-08-04 ���ǵ�����ʽ���� 上基底及具有该基底的液晶显示装置
CN1885105A (zh) * 2005-06-23 2006-12-27 三星电子株式会社 阵列基板和具有该阵列基板的显示设备
CN1992292A (zh) * 2005-12-29 2007-07-04 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
US20070197019A1 (en) * 2006-02-06 2007-08-23 Shin-Tack Kang Liquid Crystal Display Device and Manufacturing Method Thereof
US20080169473A1 (en) * 2007-01-16 2008-07-17 Yong-Seok Cho Thin film transistor array panel
CN101383327A (zh) * 2007-09-05 2009-03-11 奇美电子股份有限公司 液晶显示装置、像素阵列基板和像素阵列基板的制作
CN103676382A (zh) * 2013-12-26 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0966484A4 (en) * 1996-05-07 2002-04-17 Millennium Pharm Inc NEUROTACTIN AND APPLICATIONS THEREOF
US6163055A (en) * 1997-03-24 2000-12-19 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and manufacturing method thereof
EP2261915A3 (en) * 1998-02-23 2011-03-09 Kabushiki Kaisha Toshiba Information storage medium, information playback method and apparatus and information recording method
JP4718677B2 (ja) * 2000-12-06 2011-07-06 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
KR100900537B1 (ko) * 2002-08-23 2009-06-02 삼성전자주식회사 액정 표시 장치, 그 검사 방법 및 제조 방법
US7037272B2 (en) * 2004-07-26 2006-05-02 Ohlan Silpachai Infant respiratory monitoring system
KR101090253B1 (ko) * 2004-10-06 2011-12-06 삼성전자주식회사 박막 트랜지스터 표시판 및 이를 포함하는 액정 표시 장치
KR100647683B1 (ko) * 2005-03-08 2006-11-23 삼성에스디아이 주식회사 유기 박막 트랜지스터 및 이를 구비한 평판 디스플레이 장치
JP2007183629A (ja) * 2005-12-29 2007-07-19 Samsung Electronics Co Ltd 薄膜トランジスタ表示基板及びその製造方法
US7771576B2 (en) * 2006-07-18 2010-08-10 Ngk Spark Plug Co., Ltd. Gas sensor and method for manufacturing gas sensor
KR101366162B1 (ko) * 2007-03-20 2014-02-25 삼성디스플레이 주식회사 유기 발광 표시 패널 및 이의 제조방법
TWI328788B (en) * 2008-03-11 2010-08-11 Au Optronics Corp Gate driver-on-array and method of making the same
KR101276749B1 (ko) * 2009-08-03 2013-06-19 엘지디스플레이 주식회사 전기영동 표시장치 및 그 제조 방법
US9142568B2 (en) * 2010-09-10 2015-09-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing light-emitting display device
KR101484022B1 (ko) * 2012-05-31 2015-01-19 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 이의 제조 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1517751A (zh) * 2003-01-08 2004-08-04 ���ǵ�����ʽ���� 上基底及具有该基底的液晶显示装置
CN1885105A (zh) * 2005-06-23 2006-12-27 三星电子株式会社 阵列基板和具有该阵列基板的显示设备
CN1992292A (zh) * 2005-12-29 2007-07-04 三星电子株式会社 薄膜晶体管阵列面板及其制造方法
US20070197019A1 (en) * 2006-02-06 2007-08-23 Shin-Tack Kang Liquid Crystal Display Device and Manufacturing Method Thereof
US20080169473A1 (en) * 2007-01-16 2008-07-17 Yong-Seok Cho Thin film transistor array panel
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
CN101383327A (zh) * 2007-09-05 2009-03-11 奇美电子股份有限公司 液晶显示装置、像素阵列基板和像素阵列基板的制作
CN103676382A (zh) * 2013-12-26 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置

Also Published As

Publication number Publication date
US20160274432A1 (en) 2016-09-22
CN103676382B (zh) 2017-03-08
CN103676382A (zh) 2014-03-26
US10317758B2 (en) 2019-06-11

Similar Documents

Publication Publication Date Title
WO2015096438A1 (zh) 阵列基板及显示装置
US9620531B2 (en) TFT array substrate, display panel and display device
CN107589576B (zh) 阵列基板及其制作方法、触控显示面板
CN108196725B (zh) 触控显示基板和触控显示装置
US8350792B2 (en) Display device
WO2016141709A1 (zh) 阵列基板及其制作方法、显示装置
US11036099B2 (en) Array substrate comprising a plurality of touch signal lines having multiple non-touch-signal-transmitting lines comprising a curved section curving and detouring around a through hole
WO2016201838A1 (zh) 触控面板及其制备方法、触控显示装置
WO2018036179A1 (zh) 触控结构、阵列基板和显示装置
WO2016119373A1 (zh) 阵列基板、触控面板及阵列基板的制作方法
WO2016110036A1 (zh) 阵列基板及显示装置
WO2016119344A1 (zh) 阵列基板及其制造方法和显示面板
US20160147123A1 (en) Array substrate and display device
WO2017173779A1 (zh) 阵列基板和显示装置
US9627416B2 (en) Array substrate and method for manufacturing the same, display device
JP7362488B2 (ja) タッチ表示基板および表示装置
WO2017092485A1 (zh) 阵列基板及显示装置
WO2015096340A1 (zh) 阵列基板及其制备方法、显示装置
US20190094639A1 (en) Array substrate, manufacturing method thereof and display device
CN109270759A (zh) 阵列基板和显示面板
WO2016106893A1 (zh) 阵列基板及显示面板
TW201447450A (zh) 觸控顯示面板及其製造方法
KR102011315B1 (ko) 어레이 기판, 제조 방법, 및 대응하는 디스플레이 패널과 전자 디바이스
WO2016107310A1 (zh) 一种触摸显示屏的基板及其制造方法、触摸屏及显示装置
US9812469B2 (en) Array substrate having a plurality of gate electrode material lines, source-drain electrode material lines and first metal lines

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14409217

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14873740

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 02.12.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14873740

Country of ref document: EP

Kind code of ref document: A1