WO2015096340A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2015096340A1
WO2015096340A1 PCT/CN2014/076608 CN2014076608W WO2015096340A1 WO 2015096340 A1 WO2015096340 A1 WO 2015096340A1 CN 2014076608 W CN2014076608 W CN 2014076608W WO 2015096340 A1 WO2015096340 A1 WO 2015096340A1
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Prior art keywords
common electrode
bridge
array substrate
line
independent
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PCT/CN2014/076608
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English (en)
French (fr)
Inventor
崔贤植
金熙哲
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京东方科技集团股份有限公司
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Priority to US14/418,161 priority Critical patent/US9431432B2/en
Publication of WO2015096340A1 publication Critical patent/WO2015096340A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of display, and in particular, to an array substrate, a preparation method thereof, and a display device. Background technique
  • ADS Advanced-Super Dimensional Switching
  • ADS forms a multi-dimensional electric field by a parallel electric field generated by the pixel electrode or the common electrode edge in the same plane and a longitudinal electric field generated between the pixel electrode and the common electrode, so that the liquid crystal cell All of the aligned liquid crystal molecules directly between the inner pixel electrode or the common electrode, the pixel electrode or the common electrode can generate a rotation conversion, thereby improving the planar orientation system liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology improves TFT-LCD picture quality with high transmittance, wide viewing angle, high aperture ratio, low chromatic aberration, low response time, and no push mura.
  • the ADS mode display device is formed by pairing a color film substrate and an ADS array substrate.
  • the ADS array substrate includes: a substrate, a thin film transistor, a pixel electrode 11 and a common electrode 12 disposed on the substrate, and the pixel electrode 11 is The upper electrode is a slit electrode, and the common electrode 12 is a plate electrode.
  • the source/drain metal layer forms the source/drain 172 of the thin film transistor and the data line 171; the gate metal layer forms the gate line 13 (a portion of the gate line 13 serves as the gate of the thin film transistor) and the common electrode line 14, and also requires A gate pad 141 is formed, and then a second transparent conductive layer (2 nd ITO for forming the pixel electrode 11) is used to form the connection line 15.
  • the connection line 15 electrically connects the common electrode line 14 and the common electrode 12 through the via hole 16 in the gate connection region 141.
  • the process is increased. However, if the common electrode line 14 and the gate line 13 are disposed in the same layer, the presence of the common electrode line 14 and the gate connection region 141 may cause a decrease in the aperture ratio; in addition, when the common electrode line 14 is connected to the common electrode 12, there is a via hole. This will increase the connection resistance of the gate line. Summary of the invention
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device, which can improve an aperture ratio and improve a gate signal delay caused by an increase in connection resistance of a gate line.
  • an embodiment of the present invention provides an array substrate, including: a thin film transistor; a substrate; a common electrode disposed on the substrate; a gate line, the gate line including a plurality of discrete portions of the discontinuous distribution, the independent portion passing The bridges are connected to each other; and a common electrode line disposed in the same layer and spaced apart from the gate line, wherein the common electrode line has a connection portion that is directly electrically connected to the common electrode through a gap between the independent portions.
  • the common electrode line has a bent section that is bent into the gap and electrically connected to the connecting portion.
  • the bridge is disposed in the same layer as the source/drain of the thin film transistor; at least a portion of the bent portion is hidden at a blocking position of the bridge.
  • the bridge is disposed in the same layer as the source/drain of the thin film transistor.
  • the bridge is a transparent conductive material and is disposed in the same layer as the common electrode.
  • the array substrate further includes a pixel electrode, and the bridge is a transparent conductive material and is disposed in the same layer as the pixel electrode.
  • the array substrate further includes a parallel connection disposed above the independent portion via an insulating layer; and two ends of the parallel connection are respectively electrically connected to adjacent independent portions.
  • the parallel wiring is disposed in the same layer as the source/drain of the thin film transistor.
  • opposite ends of the two independent portions connected to the bridge are respectively provided with through holes, and the parallel wires and the bridges are electrically connected to the two independent portions through corresponding via holes.
  • embodiments of the present invention provide a display device including any of the array substrates described above.
  • an embodiment of the present invention further provides a method for preparing an array substrate, including the following steps:
  • Manufacturing a gate metal layer comprising forming a gate, a gate line, and a common electrode line, wherein the gate line formed includes a plurality of discrete portions of discontinuous distribution, and the formed common electrode line has a gap extending through the gap between the independent portions a connection to a preset position;
  • a thin film transistor comprising: forming a gate insulating layer of a thin film transistor, a semiconductor layer, a source and a drain, and a data line; 53. Forming a common electrode, wherein the common electrode is electrically connected to the common electrode line through a connection portion extending through the gap;
  • the method also includes the step of forming a bridge, the two ends of the bridge being electrically connected to two adjacent ones of the separate portions.
  • a bridge is formed over the independent portion.
  • step S5 a transparent conductive film is formed, and a pixel electrode is formed by a patterning process while forming a bridge over the independent portion.
  • the two ends of the bridge are electrically connected to the adjacent two of the independent portions through via holes, respectively.
  • step S2 is formed on the source/drain metal layer by a patterning process, in addition to forming the source, drain and data lines of the thin film transistor, and simultaneously above the independent portion. Formed and connected, the two ends of the parallel connection are respectively connected to the independent portion through a via hole.
  • the present invention also relates to a method of fabricating an array substrate, comprising the steps of: forming a plurality of discrete portions of a discontinuous distribution as a component of a gate line; forming a common electrode line having a pass through the separate portion a gap extending to a connection portion at a predetermined position; forming a bridge, the two ends of the bridge being electrically connected to two adjacent ones of the separate portions; and forming a common electrode, the common electrode extending through the A connection portion of the gap is electrically connected to the common electrode line.
  • the above preparation method further comprises the steps of: forming and connecting the upper portion of the independent portion via an insulating layer, and the two ends of the parallel wire are respectively electrically connected to the adjacent independent portions.
  • an array substrate, a method for fabricating the same, and a display device the gate line is disposed as a plurality of independent portions of intermittent distribution, and the independent portions are connected to each other by a bridge, and the common electrode line has a separate portion.
  • the common electrode line is directly electrically connected to the common electrode through the connection portion, and the gate connection region and the via hole provided for connecting the common electrode line and the common electrode are omitted as compared with the technique mentioned in the background art, thereby being improved Opening ratio, and improve grid line due to increased connection resistance
  • the gate signal is delayed.
  • FIG. 1 is a schematic structural view of an ADS mode array substrate known to the inventors
  • FIG. 2 is a schematic structural view of a gate metal layer of an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view of a gate metal layer of an array substrate according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an array substrate according to still another embodiment of the present invention
  • FIG. 5 is a schematic structural view of an array substrate according to still another embodiment of the present invention
  • FIG. 6 is an array substrate according to still another embodiment of the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate includes: a thin film transistor; a substrate; a common electrode 12 disposed on the substrate; a gate line, the gate line includes a plurality of discrete portions 130 that are intermittently distributed, and the independent portion 130 passes through the bridge 152.
  • the gate line Connected to each other; and a common electrode line 14 disposed in the same layer and spaced apart from the gate line, wherein the public power
  • the pole line 14 has a connection portion 144 that is directly connected to the common electrode 12 through a gap between the individual portions 130.
  • Embodiments of the present invention provide an array substrate for a planar field display device, the array substrate being provided with a pixel electrode and a common electrode, and a thin film transistor for controlling display signal loading.
  • the array substrate generally includes a substrate, a gate metal layer (for forming a gate line and a gate of a thin film transistor), a gate insulating layer, a semiconductor layer, and a source/drain metal layer (on the substrate) Forming a source and a drain of the data line and the thin film transistor, an interlayer insulating layer, a first transparent conductive layer, a passivation protective layer, a second transparent conductive layer, wherein the first transparent conductive layer and the second transparent conductive layer Used to form a pixel electrode and a common electrode, respectively.
  • the gate metal layer of this embodiment includes a gate line and a common electrode line 14, and the gate line includes a plurality of independent portions 130 of intermittent distribution, independent.
  • the portions 130 are interconnected by a bridge (not shown in the drawings, see reference numeral 152 in FIGS. 4-6); the connection portion 144 of the common electrode line 14 extends through the discontinuity of the gate line (or the gap between the individual portions 130) ) is directly electrically connected to the common electrode 12.
  • the independent portion 130 may further include a gate electrode 131 of the thin film transistor.
  • the gap between two adjacent independent portions 130 may be located below the bridge.
  • the embodiment of the present invention omits the gate connection region and the via hole provided for connecting the common electrode line and the common electrode, thereby increasing the aperture ratio and reducing the connection resistance of the gate line. In turn, the gate signal delay due to the increase in connection resistance is improved.
  • the gap between adjacent individual portions 130 may also be increased while the common electrode line 14 is bent to form a bent portion 142, such as As shown in FIG. 3 (only the common electrode 12 and the gate metal layer are shown), the bent sections of the common electrode line 14 are disposed at the gaps between the adjacent independent portions 130. Specifically, in FIGS. 3 and 4, in the gap between two adjacent independent portions 130, a portion of the common electrode line 14 is bent upward, and the bent portion 142 is branched and connected to the common electrode 12, and the other branch is connected. It is hidden in the blocking position of the grid bridge 152, thereby reducing the occupied area of the metal trace and further increasing the aperture ratio.
  • the bridge for connecting the independent portion 130 to form the gate line may be any conductive film layer well known to those skilled in the art on the array substrate, or newly added to specifically form the The conductive film layer of the bridge.
  • the bridge described in this embodiment may It is disposed in the same layer as the source/drain of the thin film transistor, and may also be disposed in the same layer as the pixel electrode or the common electrode on the substrate.
  • the bridge is a transparent conductive material. Therefore, the embodiment of the present invention does not specifically limit the film layer forming the bridge and the manner of formation.
  • the array substrate according to the present invention will be described in detail by way of another specific embodiment.
  • the array substrate is provided with a pixel electrode 11, a common electrode 12, a thin film transistor, a gate line, a common electrode line 14 and a data line 171; and the gate line and the data line 171 are vertically crisscrossed to form a pixel.
  • the pixel electrode 11 and the common electrode 12 are disposed in the pixel region, and the thin film transistor is disposed at an intersection of the gate line and the data line 171.
  • the gate line includes a plurality of discrete portions 130 of discrete distribution as shown in FIG. 3, formed of a gate metal layer, and the individual portions 130 are interconnected by a bridge 152 to form a turn-on gate line.
  • the bridge 152 is disposed in the same layer as the source/drain 172 of the thin film transistor.
  • the common electrode line 14 is disposed in parallel with the gate line, and a portion of the common electrode line 14 is folded up to form a bent portion 142, and the bent portion 142 is connected to the connecting portion 144 directly connected to the common electrode 12, and at least a portion of the bent portion 142 is hidden. In the occlusion position of the bridge 152.
  • the gate line includes a plurality of discrete portions 130 (the individual portions 130 may be referred to FIG. 2), and the individual portions 130 are connected to each other by a bridge 152, the bridge 152 and the pixel electrode 11 Same layer setting.
  • the common electrode line 14 is disposed in parallel with the gate line, and the connection portion 144 of the common electrode line 14 extends directly through the gap between the individual portions 130 below the bridge 152 to be directly connected to the common electrode 12.
  • the individual portions 130 are connected to each other by a bridge 152 to form a turn-on gate line.
  • the gate line resistance mainly reducing the gate line resistance due to the bridge
  • the gate signal delay is avoided, and in some (or all) of the independent portion 130
  • the upper layer is provided with an insulating layer and is connected to the line 153.
  • the array substrate may further include: a parallel wiring 153 overlapping the independent portion 130 via an insulating layer, and both ends of the parallel wiring 153 are electrically connected to the independent portion 130, respectively.
  • the two ends of the parallel connection 153 are connected to the separate portion 130 through vias, respectively.
  • the bridge 152 and the parallel connection 153 may be connected to the independent portion 130 according to the above requirements through separately provided via holes, and of course, the via holes may be shared.
  • the via holes may be shared.
  • only two via holes need to be provided on each of the independent portions 130, and the bridge 152, the parallel wires 153 and the independent portion 130 are electrically connected at the via holes.
  • the gate lines are disposed as separate portions of the intermittent distribution, and the connection portion 144 of the common electrode line 14 is directly connected to the common electrode 12 through the gap between the independent portions 130, omitting the connection of the common electrode line 14 and the common electrode 12
  • the gate connection region and the via hole can increase the aperture ratio and reduce the connection resistance of the gate line, thereby improving the gate signal delay caused by the increase of the connection resistance.
  • the parallel wiring 153 is provided in parallel with the independent portion 130 via the insulating layer over the independent portion 130, the gate line resistance can be lowered, and the gate signal delay due to the increase in the gate line resistance can be further improved.
  • the array substrate of the embodiment is exemplified by a thin film transistor having a bottom gate structure, but is also applicable to a thin film transistor having a top gate structure.
  • a thin film transistor having a top gate structure a person skilled in the art can according to actual conditions. Select a conductive layer (usually a metal layer or an electrode layer) above or below to form a bridge.
  • the embodiment of the invention further provides a display device comprising any of the above array substrates.
  • the display device can increase the aperture ratio and improve the gate signal delay due to the increase in the connection resistance of the gate line, thereby achieving higher display quality.
  • the display device may be: a liquid crystal panel, a electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • a method of preparing an array substrate according to an embodiment of the present invention is described below. As shown in FIG. 7, the method includes the following steps:
  • a gate metal layer forming a gate, a gate line, and a common electrode line; wherein, the gate line formed in the step includes a plurality of independent portions of the discontinuous distribution, and the formed common electrode line has an extension through the independent a gap between the portions and a connection portion to a preset position of the common electrode;
  • a thin film transistor forming a gate insulating layer, a semiconductor layer, a source and a drain of the thin film transistor, and a data line; wherein, in the step, a source of the thin film transistor is formed on the source/drain metal layer by a patterning process, In the case of the drain and the data line, a bridge is also formed over the independent portion, and both ends of the bridge are electrically connected to the adjacent two separate portions.
  • the gate line formed in step S1 includes a plurality of discrete portions of discontinuous distribution having a connection portion extending through a gap between the individual portions to a predetermined position of the common electrode.
  • a bridge is formed over the independent portion, and the two ends of the bridge are respectively adjacent to each other.
  • the two separate parts are electrically connected, and the rest of the steps are substantially similar to the prior art, and are not described herein again.
  • a transparent conductive film is formed, and a pixel electrode is formed by a patterning process while forming a bridge over the independent portion.
  • the common electrode lines formed in step S1 are bent to form a bent portion at a gap between the independent portions, and the aperture ratio can be further increased.
  • the gate connection region and the via hole provided for connecting the common electrode line and the common electrode are omitted, thereby increasing the aperture ratio, reducing the connection resistance of the gate line, and thereby improving the connection.
  • the gate signal is delayed due to the increase in resistance.
  • the gate metal layer when the gate metal layer is formed into a gate line, only a plurality of independent portions of the discontinuous distribution are formed, and the formed connection portion of the common electrode line extends to the common through the gap between the independent portions.
  • a preset position of the electrode when a source/drain or a pixel electrode of the thin film transistor is subsequently formed, a bridge is formed at the same time, and the independent portions are connected to each other to form a gate line, thus, compared with the technique mentioned in the background art
  • the gate connection region and the via hole for connecting the common electrode line and the common electrode can be omitted, thereby increasing the aperture ratio and improving the gate signal delay due to the increase in the connection resistance of the gate line.
  • the present invention provides a method of fabricating an array substrate, comprising the following steps:
  • Manufacturing a gate metal layer comprising forming a gate, a gate line, and a common electrode line, wherein the gate line formed includes a plurality of discrete portions of discontinuous distribution, and the formed common electrode line has a gap extending through the gap between the independent portions a connection to a preset position;
  • Manufacturing a thin film transistor comprising: forming a gate insulating layer of a thin film transistor, a semiconductor layer, a source and a drain, and a data line;
  • the method further includes a step of forming a bridge, and two ends of the bridge are respectively electrically connected to two adjacent ones of the adjacent portions.
  • the present invention also provides a method of fabricating an array substrate, comprising the steps of: forming a plurality of independent portions of a discontinuous distribution as a component of a gate line; forming a common electrode line, the common electrode line having an independent a gap between the portions extending to a connection portion at a preset position; forming a bridge, the two ends of the bridge being electrically connected to the adjacent two independent portions, respectively; and forming a common electrode, the common electrode extending through the The connection portion of the gap is electrically connected to the common electrode line.
  • the above preparation method further comprises the steps of: forming and connecting the upper portion of the independent portion via an insulating layer, and the two ends of the parallel wire are respectively electrically connected to the adjacent independent portions.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

提供一种阵列基板及其制备方法、显示装置，涉及显示领域，能够提高开口率，并改善栅线因连接电阻增加导致的栅信号延迟。本发明提供的阵列基板，包括：薄膜晶体管；基板；设置在基板上的公共电极（12）；栅线（13）；栅线（13）包括多个间断分布的独立部分（130），独立部分（130）通过搭桥（152）相互连接；以及与栅线（13）同层且间隔开设置的公共电极线（14），其中，公共电极线（14）具有穿过独立部分（130）之间的间隙而直接与公共电极（12）电连接的连接部（144）。

Description

阵列基板及其制备方法、 显示装置
技术领域
本发明涉及显示领域， 尤其涉及一种阵列基板及其制备方法、 显示 装置。 背景技术
高级超维场开关技术 (Advanced- Super Dimensional Switching, 简称： ADS ) 通过同一平面内像素电极或公共电极边缘所产生的平行电场以及 像素电极与公共电极间产生的纵向电场形成多维电场， 使液晶盒内像素 电极或公共电极之间、 像素电极或公共电极正上方所有取向液晶分子都 能够产生旋转转换， 从而提高了平面取向系液晶工作效率并增大了透光 效率。
高级超维场开关技术可以提高 TFT-LCD 画面品质， 具有高透过率、 宽视角、 高开口率、 低色差、 低响应时间、 无挤压水波纹 （push Mura) 等优点。
ADS 模式显示装置由彩膜基板和 ADS 阵列基板对盒而成， 如图 1 所示， ADS 阵列基板包括： 基板， 设置在基板上的薄膜晶体管、 像素电 极 11和公共电极 12， 像素电极 11在上为狭缝电极， 公共电极 12在下为 板式电极。 制备时， 源漏金属层形成薄膜晶体管的源 /漏极 172 以及数据 线 171 ; 栅金属层形成栅线 13 (栅线 13的一部分充当薄膜晶体管的栅极) 和公共电极线 14， 同时还需形成栅连接区 （Gate pad) 141， 然后利用第 二透明导电层 （2nd ITO, 用以形成像素电极 11 ) 形成连接线 15。 连接线 15在栅连接区 141通过过孔 16将公共电极线 14和公共电极 12电连接。
如果公共电极线 14与栅线 13设置在不同层， 则会增加工序。 但是 如果公共电极线 14与栅线 13设置在同一层， 则公共电极线 14以及栅连 接区 141的存在会导致开口率减少； 另外， 公共电极线 14与公共电极 12 连接时存在过孔， 也会使得栅线的连接电阻增加。 发明内容
本发明的实施例提供一种阵列基板及其制备方法、 显示装置， 可提 高开口率， 并改善栅线因连接电阻增加导致的栅信号延迟。
为达到上述目的， 本发明的实施例采用如下技术方案：
一方面， 本发明的实施例提供一种阵列基板， 包括： 薄膜晶体管； 基板； 设置在基板上的公共电极； 栅线， 所述栅线包括多个间断分布的 独立部分， 所述独立部分通过搭桥相互连接； 以及与所述栅线同层且间 隔开设置的公共电极线， 其中， 所述公共电极线具有穿过独立部分之间 的间隙而直接与所述公共电极电连接的连接部。
在本发明的一个实施例中， 所述公共电极线具有弯折到所述间隙中 且与所述连接部电连接的弯折段。 进一歩地， 所述搭桥与所述薄膜晶体 管的源 /漏极同层设置； 所述弯折段的至少一部分隐藏在所述搭桥的遮挡 位置。
在本发明的一个实施例中， 所述搭桥与所述薄膜晶体管的源 /漏极同 层设置。
在本发明的一个实施例中， 所述搭桥为透明导电材质且与所述公共 电极同层设置。 或者， 所述阵列基板还包括像素电极， 所述搭桥为透明 导电材质且与所述像素电极同层设置。
在本发明的一个实施例中， 所述阵列基板还包括隔着绝缘层重叠设 置在所述独立部分上方的并连线； 且所述并连线的两端分别与相邻的独 立部分电连接。 进一歩地， 所述并连线与所述薄膜晶体管的源 /漏极同层 设置。 可选地， 与搭桥相连的两个独立部分的相对的两端分别设置有过 孔， 所述并连线、 所述搭桥均通过对应过孔与所述两个独立部分电连接。
与相邻的独立部分电连接另一方面， 本发明实施例还提供一种显示 装置， 包括上述的任一阵列基板。
再一方面， 本发明的实施例还提供一种阵列基板的制备方法， 包括 如下歩骤：
51、 制造栅金属层， 包括形成栅极、 栅线和公共电极线， 其中形成 的栅线包括多个间断分布的独立部分， 形成的公共电极线具有穿过所述 独立部分之间的间隙延伸到预设位置的连接部；
52、 制造薄膜晶体管， 包括形成薄膜晶体管的栅绝缘层、 半导体层、 源极和漏极， 以及数据线； 53、 形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与 所述公共电极线电连接；
54、 形成钝化保护层；
55、 形成像素电极，
其中，
所述方法还包括形成搭桥的歩骤， 所述搭桥的两端分别与相邻的两 个所述独立部分电连接。
在一个具体的实施例中， 歩骤 S2中通过构图工艺在源漏金属层上形 成薄膜晶体管的源极、 漏极和数据线时， 还同歩在所述独立部分的上方 形成搭桥。
在一个具体的实施例中， 在歩骤 S5中， 形成透明导电膜， 并通过构 图工艺形成像素电极， 同时在所述独立部分的上方形成搭桥。
在一个具体的实施例中， 所述搭桥的两端分别通过过孔与相邻的两 个所述独立部分电连接。
进一歩地， 歩骤 S5 中形成搭桥时， 歩骤 S2中通过构图工艺在源漏 金属层上， 除形成薄膜晶体管的源极、 漏极和数据线外， 还同步在所述 独立部分的上方形成并连线， 所述并连线的两端分别通过过孔与所述独 立部分相连接。
本发明也涉及一种阵列基板的制备方法， 包括如下歩骤： 形成作为 栅线的组成部分的多个间断分布的独立部分； 形成公共电极线， 所述公 共电极线具有穿过所述独立部分之间的间隙延伸到预设位置的连接部； 形成搭桥， 所述搭桥的两端分别与相邻的两个所述独立部分电连接； 以 及形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与所述公 共电极线电连接。 可选地， 上述制备方法还包括歩骤： 隔着绝缘层在所 述独立部分的上方形成并连线， 所述并连线的两端分别与相邻的独立部 分电连接。
本发明实施例提供的阵列基板及其制备方法、 显示装置， 所述栅线 设置成多个间断分布的独立部分， 再通过搭桥将所述独立部分相互连接， 公共电极线具有穿过独立部分之间的间隙而直接与所述公共电极电连接 的连接部。 这样， 公共电极线通过连接部直接与公共电极电连接， 与背 景技术中提到的技术相比， 省去了为连接公共电极线和公共电极而设的 栅连接区和过孔， 因而可提高开口率， 并改善栅线因连接电阻增加导致 的栅信号延迟。 附图说明
为了更清楚地说明本发明实施例中的技术方案， 下面将对实施例中 所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅 是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造 性劳动的前提下， 还可以根据这些附图获得其它的附图。
图 1为发明人已知的 ADS模式阵列基板的结构示意图；
图 2 为根据本发明的一个实施例的阵列基板的栅金属层的结构示意 图；
图 3 为根据本发明的另一个实施例的阵列基板的栅金属层的结构示 意图；
图 4为根据本发明的再一个实施例的阵列基板的结构示意图； 图 5为根据本发明的又一个实施例的阵列基板的结构示意图； 图 6为根据本发明的还一个实施例的阵列基板的结构示意图； 以及 图 7为本发明的一个实施例的阵列基板的制备方法的流程图。
附图标记
11-像素电极， 12-公共电极， 13-栅线， 14-公共电极线， 141-栅 连接区，
15-连接线， 16-过孔， 171-数据线， 172-源 /漏极， 152-搭 桥，
131-薄膜晶体管的栅极， 130-独立部分， 142-弯折段， 153-并连线。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案 进行清楚、 完整地描述。
本发明实施例提供一种阵列基板。 参见图 2-6， 该阵列基板包括： 薄 膜晶体管； 基板； 设置在基板上的公共电极 12 ; 栅线， 所述栅线包括多 个间断分布的独立部分 130， 所述独立部分 130通过搭桥 152相互连接； 以及与所述栅线同层且间隔开设置的公共电极线 14， 其中， 所述公共电 极线 14具有穿过独立部分 130之间的间隙而直接与所述公共电极 12 电 连接的连接部 144。
本发明的实施例提供了一种用于平面场显示装置的阵列基板， 所述 阵列基板设置有像素电极和公共电极， 以及控制显示信号加载的薄膜晶 体管。 就膜层结构而言， 所述阵列基板一般包括基板， 设置在基板上的 栅金属层 （用于形成栅线和薄膜晶体管的栅极） ， 栅绝缘层， 半导体层， 源漏金属层 （用于形成数据线和薄膜晶体管的源极和漏极） ， 层间绝缘 层， 第一透明导电层， 钝化保护层， 第二透明导电层， 其中， 第一透明 导电层和第二透明导电层分别用于形成像素电极和公共电极。
为便于理解， 图 2中仅示出公共电极 12和栅金属层， 本实施例所述 栅金属层包括栅线和公共电极线 14， 所述栅线包括多个间断分布的独立 部分 130， 独立部分 130通过搭桥 （图中未示出， 参见图 4-6中的附图标 记 152 ) 相互连接； 公共电极线 14的连接部 144延伸经过栅线的间断处 (或独立部分 130之间的间隙） 而直接与公共电极 12 电连接。 其中， 独 立部分 130还可包括薄膜晶体管的栅极 131。
需要说明的是， 在本发明的实施例中， 相邻两个独立部分 130 之间 的间隙可以处位于搭桥下方。
与背景技术中提到的技术相比， 本发明实施例省去了为连接公共电 极线和公共电极而设的栅连接区和过孔， 因而可提高开口率， 减小栅线 的连接电阻， 进而改善因连接电阻增加导致的栅信号延迟。
如图 3-4 中所示， 在本发明的其他实施例中， 还可加大相邻独立部 分 130之间的间隙， 同时使公共电极线 14弯折以形成弯折段 142， 例如 如图 3所示 （仅示出公共电极 12和栅金属层） ， 公共电极线 14的弯折 段设置在相邻独立部分 130之间的间隙处。 具体而言， 在图 3、 4中， 在 相邻两个独立部分 130 的间隙， 部分公共电极线 14 向上弯折， 弯折段 142分出一支路与公共电极 12相连， 另一支路隐藏在栅线搭桥 152 的遮 挡位置， 从而减小金属走线占用面积， 进一歩提高开口率。
可以理解的是， 本发明实施例中用以连接独立部分 130 组成栅线的 搭桥， 可以是阵列基板上本领域技术人员所熟知的任意导电膜层， 或新 增设的专门用以形成所述搭桥的导电膜层。 例如， 本实施例所述搭桥可 以与薄膜晶体管的源 /漏极同层设置， 也可以与基板上的像素电极或公共 电极同层设置。 所述搭桥与像素电极或公共电极同层设置时， 所述搭桥 为透明导电材质。 因此， 本发明实施例对形成搭桥的膜层以及形成方式 不做具体限定。
为了本领域技术人员更好的理解根据本发明的阵列基板的结构， 下 面通过另外的具体的实施例对根据本发明的阵列基板进行详细说明。
在图 4所示的实施例中， 所述阵列基板上设置有像素电极 11、 公共 电极 12、 薄膜晶体管、 栅线、 公共电极线 14与数据线 171 ; 栅线与数据 线 171纵横交错形成像素区域， 像素电极 11和公共电极 12设置在像素 区域， 薄膜晶体管设置在栅线与数据线 171的交叉位置。
栅线如图 3所示包括多个间断分布的独立部分 130， 由栅金属层形成， 独立部分 130通过搭桥 152相互连接形成可导通的栅线。 如图 4所示， 搭桥 152与薄膜晶体管的源 /漏极 172 同层设置。 公共电极线 14与栅线 平行设置， 且部分公共电极线 14上折以形成弯折段 142， 弯折段 142连 接到与公共电极 12直接相连的连接部 144， 弯折段 142的至少一部分隐 藏在搭桥 152的遮挡位置。
在图 5所示的实施例中， 所述栅线包括多个间断分布的独立部分 130 (独立部分 130可参考图 2所示） ， 独立部分 130通过搭桥 152相互连 接， 搭桥 152与像素电极 11 同层设置。 公共电极线 14与栅线平行设置， 且公共电极线 14的连接部 144延伸通过搭桥 152下方的独立部分 130之 间的间隙而与公共电极 12直接相连。
独立部分 130通过搭桥 152 相互连接形成可导通的栅线， 为降低栅 线电阻 （主要是降低因 ΓΓϋ 搭桥增加的栅线电阻） ， 避免栅信号延迟， 在部分 （或全部） 独立部分 130的上方隔着绝缘层设置并连线 153。 在图 6所示的实施例中， 所述阵列基板还可包括： 隔着绝缘层重叠在独立部分 130上方的并连线 153， 且并连线 153的两端分别与独立部分 130电连接。 在可选的示例中， 并连线 153 的两端分别通过过孔与独立部分 130相连 接。
在可选的示例中， 搭桥 152、 并连线 153可分别通过独立设置的过孔 按上述要求与独立部分 130 连接， 当然也可以共用过孔。 在可选的示例 中， 如图 6所示， 每个独立部分 130上只需设置两个过孔， 搭桥 152、 并 连线 153和独立部分 130在过孔处实现电连接。
本发明实施例将栅线设置成间断分布的独立部分， 公共电极线 14 的 连接部 144通过独立部分 130之间的间隙直接连接至公共电极 12， 省去 了为连接公共电极线 14和公共电极 12 而设的栅连接区和过孔， 因而可 提高开口率， 减小栅线的连接电阻， 进而改善因连接电阻增加导致的栅 信号延迟。 另一方面， 在独立部分 130 上方隔着绝缘层设置与独立部分 130并连的并连线 153的情况下， 可降低栅线电阻， 进一歩改善因栅线电 阻增加导致的栅信号延迟。
需要说明的是， 本实施例所述阵列基板虽然以底栅结构的薄膜晶体 管为例， 但对于顶栅结构的薄膜晶体管同样适用， 对于顶栅结构的薄膜 晶体管， 本领域技术人员可以根据实际情况选择上方或下方的导电层 (一般为金属层或电极层） 形成搭桥。
本发明实施例还提供一种显示装置， 其包括上述任意一种阵列基板。 所述显示装置可提高开口率， 并改善栅线因连接电阻增加导致的栅信号 延迟， 从而获得更高的显示品质。 所述显示装置可以为： 液晶面板、 电 子纸、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导 航仪等任何具有显示功能的产品或部件。
下面描述根据本发明的一个实施例的制备阵列基板的方法， 如图 7 所示， 该方法包括歩骤：
51、 制造栅金属层， 形成栅极、 栅线和公共电极线； 其中， 本歩骤 中形成的栅线包括多个间断分布的独立部分， 形成的所述公共电极线具 有延伸经过所述独立部分之间的间隙而至公共电极的预设位置的连接部;
52、 制造薄膜晶体管， 形成薄膜晶体管的栅绝缘层、 半导体层、 源 极和漏极， 以及数据线； 其中， 本歩骤中通过构图工艺在源漏金属层上， 形成薄膜晶体管的源极、 漏极和数据线时， 还同歩在独立部分的上方形 成搭桥， 所述搭桥的两端分别与相邻的两个所述独立部分电连接。
53、 形成公共电极， 所述公共电极与所述公共电极线的连接部电连 接；
54、 形成钝化保护层； S5、 形成像素电极。
上述方法中， 歩骤 S1 中形成的栅线包括多个间断分布的独立部分， 具有延伸经过所述独立部分之间的间隙而至公共电极的预设位置的连接 部。 歩骤 S2 中通过构图工艺在源漏金属层上形成薄膜晶体管的源极、 漏 极和数据线时， 还同歩在所述独立部分的上方形成搭桥， 所述搭桥的两 端分别与相邻的两个所述独立部分电连接， 除此之外， 其余歩骤与现有 技术大致类似， 在此不再赘述。 或者可选地， 在歩骤 S5 中， 形成透明导 电膜， 并通过构图工艺形成像素电极， 同时在所述独立部分的上方形成 搭桥。 可选地， 歩骤 S1 中形成的公共电极线弯折以形成位于独立部分之 间的间隙处的弯折段， 可进一歩提高开口率。
本发明实施例所述阵列基板制备方法， 省去了为连接公共电极线和 公共电极而设的栅连接区和过孔， 因而可提高开口率， 减小栅线的连接 电阻， 进而改善因连接电阻增加导致的栅信号延迟。
本发明实施例提供的阵列基板制备方法， 在栅金属层形成栅线时， 只形成多个间断分布的独立部分， 形成的所述公共电极线的连接部经独 立部分之间的间隙延伸至公共电极的预设位置； 在后续形成薄膜晶体管 的源 /漏极或像素电极时， 再同歩形成搭桥， 将所述独立部分相互连接形 成栅线， 这样， 与背景技术中提及的技术相比， 可省去为连接公共电极 线和公共电极而设的栅连接区和过孔， 因而可提高开口率， 并改善栅线 因连接电阻增加导致的栅信号延迟。
为此， 本发明提出了一种阵列基板的制备方法， 包括如下歩骤：
51、 制造栅金属层， 包括形成栅极、 栅线和公共电极线， 其中形成 的栅线包括多个间断分布的独立部分， 形成的公共电极线具有穿过所述 独立部分之间的间隙延伸到预设位置的连接部；
52、 制造薄膜晶体管， 包括形成薄膜晶体管的栅绝缘层、 半导体层、 源极和漏极， 以及数据线；
53、 形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与 所述公共电极线电连接；
54、 形成钝化保护层； 以及
55、 形成像素电极， 其中， 所述方法还包括形成搭桥的歩骤， 所述搭桥的两端分别与相 邻的两个所述独立部分电连接。
本发明还提出了一种阵列基板的制备方法， 包括如下歩骤： 形成作 为栅线的组成部分的多个间断分布的独立部分； 形成公共电极线， 所述 公共电极线具有穿过所述独立部分之间的间隙延伸到预设位置的连接部; 形成搭桥， 所述搭桥的两端分别与相邻的两个所述独立部分电连接； 以 及形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与所述公 共电极线电连接。 可选地， 上述制备方法还包括歩骤： 隔着绝缘层在所 述独立部分的上方形成并连线， 所述并连线的两端分别与相邻的独立部 分电连接。
本说明书中的各个实施例均采用递进的方式描述， 各个实施例之间 相同相似的部分互相参见即可， 每个实施例重点说明的都是与其他实施 例的不同之处。 尤其， 对于方法实施例而言， 由于其基本相似于设备实 施例， 所以描述得比较简单， 相关之处参见设备实施例的部分说明即可。
以上所述， 仅为本发明的具体实施方式， 但本发明的保护范围并不 局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护范围应该以权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种阵列基板， 包括：
薄膜晶体管；
基板；
设置在基板上的公共电极；
栅线， 所述栅线包括多个间断分布的独立部分， 所述独立部分通过 搭桥相互连接； 以及
与所述栅线同层且间隔开设置的公共电极线， 其中，
所述公共电极线具有穿过独立部分之间的间隙而直接与所述公共电 极电连接的连接部。
2、 根据权利要求 1所述的阵列基板， 其中， 所述公共电极线具有弯 折到所述间隙中且与所述连接部电连接的弯折段。
3、 根据权利要求 2所述的阵列基板， 其中，
所述搭桥与所述薄膜晶体管的源 /漏极同层设置；
所述弯折段的至少一部分隐藏在所述搭桥的遮挡位置。
4、 根据权利要求 1所述的阵列基板， 其中，
所述搭桥与所述薄膜晶体管的源 /漏极同层设置。
5、 根据权利要求 1所述的阵列基板， 其中，
所述搭桥为透明导电材质且与所述公共电极同层设置。
6、 根据权利要求 1所述的阵列基板， 其中，
所述阵列基板还包括像素电极， 所述搭桥为透明导电材质且与所述 像素电极同层设置。
7、 根据权利要求 1-6中任一项所述的阵列基板， 其中，
所述阵列基板还包括隔着绝缘层重叠设置在所述独立部分上方的并 连线； 且所述并连线的两端分别与相邻的独立部分电连接。
8、 根据权利要求 7所述的阵列基板， 其中，
所述并连线与所述薄膜晶体管的源 /漏极同层设置。
9、 根据权利要求 7所述的阵列基板， 其中，
与搭桥相连的两个独立部分的相对的两端分别设置有过孔， 所述并 连线、 所述搭桥均通过对应过孔与所述两个独立部分电连接。
10、 一种显示装置， 包括： 权利要求 1-9任一项所述的阵列基板。
11、 一种阵列基板的制备方法， 包括如下歩骤：
51、 制造栅金属层， 包括形成栅极、 栅线和公共电极线， 其中形成 的栅线包括多个间断分布的独立部分， 形成的公共电极线具有穿过所述 独立部分之间的间隙延伸到预设位置的连接部；
52、 制造薄膜晶体管， 包括形成薄膜晶体管的栅绝缘层、 半导体层、 源极和漏极， 以及数据线；
53、 形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与 所述公共电极线电连接；
54、 形成钝化保护层；
55、 形成像素电极，
其中，
所述方法还包括形成搭桥的歩骤， 所述搭桥的两端分别与相邻的两 个所述独立部分电连接。
12、 根据权利要求 11所述的制备方法， 其中，
在步骤 S2 中通过构图工艺在源漏金属层上形成薄膜晶体管的源极、 漏极和数据线时， 还同歩在所述独立部分的上方形成搭桥。
13、 根据权利要求 11所述的制备方法， 其中，
在步骤 S5中，
形成透明导电膜， 并通过构图工艺形成像素电极， 同时在所述独立 部分的上方形成搭桥。
14、 根据权利要求 11所述的制备方法， 其中，
所述搭桥的两端分别通过过孔与相邻的两个所述独立部分电连接。
15、 根据权利要求 13所述的制备方法， 其中， 歩骤 S2 中通过构图 工艺在源漏金属层上， 除形成薄膜晶体管的源极、 漏极和数据线外， 还 同歩在所述独立部分的上方形成并连线， 所述并连线的两端分别通过过 孔与所述独立部分相连接。
16、 一种阵列基板的制备方法， 包括如下歩骤：
形成作为栅线的组成部分的多个间断分布的独立部分； 形成公共电极线， 所述公共电极线具有穿过所述独立部分之间的间 隙延伸到预设位置的连接部；
形成搭桥， 所述搭桥的两端分别与相邻的两个所述独立部分电连接; 以及
形成公共电极， 所述公共电极通过延伸过所述间隙的连接部与所述 公共电极线电连接。
17、 根据权利要求 16所述的制备方法， 还包括歩骤：
隔着绝缘层在所述独立部分的上方形成并连线， 所述并连线的两端 分别与相邻的独立部分电连接。
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