WO2016106893A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2016106893A1
WO2016106893A1 PCT/CN2015/071173 CN2015071173W WO2016106893A1 WO 2016106893 A1 WO2016106893 A1 WO 2016106893A1 CN 2015071173 W CN2015071173 W CN 2015071173W WO 2016106893 A1 WO2016106893 A1 WO 2016106893A1
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Prior art keywords
wire
disposed
display
area
display area
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PCT/CN2015/071173
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English (en)
French (fr)
Inventor
宋涛
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深圳市华星光电技术有限公司
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Priority to US14/440,841 priority Critical patent/US20160190158A1/en
Publication of WO2016106893A1 publication Critical patent/WO2016106893A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the invention relates to the field of display, and in particular to an array substrate and a display panel.
  • An electronic device such as a mobile phone usually includes a display panel including a display area and a non-display area.
  • the display area is usually an area for displaying an image, a text or a video
  • the non-display area is also called a bezel area
  • the non-display area is disposed around the display area.
  • the non-display area includes the adjacent display area.
  • each non-display sub-area is provided with a line or integrated chip. Therefore, the frame of the display panel in the prior art is wider, and thus affects the look and feel of the product and the user experience.
  • the present invention provides an array substrate that causes a display panel including the array substrate to have a narrow bezel.
  • the array substrate includes a display area and a non-display area disposed around the display area;
  • the non-display area includes a first non-display sub-area disposed on one side of the display area, and an integrated chip is disposed in the first non-display sub-area;
  • the display area is set with:
  • first wires comprise scan lines or Common electrode line
  • a first insulating layer is disposed between the first wire and the second wire, and a plurality of through holes are disposed on the first insulating layer;
  • Each of the first wires is electrically connected to one end of the second wire through a corresponding through hole
  • the other end of the second wire and the data line are electrically connected to the integrated chip.
  • At least one of the second wires comprises a first portion and a second portion connected to the first portion, the first portion is disposed along the second direction, and the first portion is stacked with the first wire.
  • the second portion is disposed along the first direction, and the second portion is stacked with the data line.
  • the data line is disposed on the second wire through a second insulating layer or the data line passes through a second insulation
  • the layer is disposed on a surface of the first wire away from the first insulating layer.
  • the first non-display sub-region is disposed corresponding to a bottom end of the display region.
  • a display panel in another aspect, has a narrower bezel.
  • the display panel includes an array substrate, and the array substrate includes a display area and a non-display area disposed around the display area;
  • the non-display area includes a first non-display sub-area disposed on one side of the display area, and an integrated chip is disposed in the first non-display sub-area;
  • the display area is set with:
  • first wires comprise scan lines or common electrode lines
  • a first insulating layer is disposed between the first wire and the second wire, and a plurality of through holes are disposed on the first insulating layer;
  • Each of the first wires is electrically connected to one end of the second wire through a corresponding through hole
  • the other end of the second wire and the data line are electrically connected to the integrated chip.
  • At least one of the second wires comprises a first portion and a second portion connected to the first portion, the first portion is disposed along the second direction, and the first portion is stacked with the first wire.
  • the second portion is disposed along the first direction, and the second portion is stacked with the data line.
  • the data line is disposed on the second wire through a second insulating layer or the data line passes through a second insulation
  • the layer is disposed on a surface of the first wire away from the first insulating layer.
  • the first non-display sub-region is disposed corresponding to a bottom end of the display region.
  • the array substrate of the present invention and the array substrate in the display panel are provided with the first insulating layer on a plurality of the first wires, and the first insulating layer is disposed on the first insulating layer a second wire, the first insulating layer is provided with a plurality of through holes, the second wire is electrically connected to the first wire through a corresponding through hole, and the other end of the second wire is electrically connected to the data line to The same first non-display sub-area.
  • the wiring on the non-display sub-regions on both sides of the array substrate is reduced, thereby reducing the width of the non-display sub-region of the array substrate, that is, the array substrate has a narrow bezel.
  • FIG. 1 is a schematic structural view of an array substrate according to a preferred embodiment of the present invention.
  • Figure 2 is a schematic cross-sectional view taken along line I-I of Figure 1.
  • FIG 3 is a schematic structural view of a display panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a cross-sectional structural view taken along line I-I of FIG.
  • the thin film transistor array 100 includes a display area 110 and a non-display area 120 disposed around the display area 110.
  • the non-display area 120 includes a first non-display sub-area 121 disposed on one side of the display area 110, and an integrated chip 1211 is disposed in the first non-display sub-area 121.
  • the integrated chip 1211 is used for signals and processes the feedback signals. For example, the integrated chip 1211 can transmit a scan signal to a scan line or a data signal to a data line.
  • the display area 110 is provided with a plurality of data lines 111 disposed along the first direction, a plurality of first conductive lines 112 disposed along the second direction, and a plurality of second conductive lines 113.
  • the first wire 112 includes a gate line or a common line.
  • a first insulating layer 114 is disposed between the first conductive line 112 and the second conductive line 113, and a plurality of via holes 1141 are disposed on the first insulating layer 114.
  • Each of the first wires 112 is electrically connected to one end of the second wire 113 through a corresponding through hole 1141 , and the other end of the second wire 113 and the data line 111 are electrically connected to the integrated chip 1121 .
  • the first direction is a vertical direction
  • the second direction is a horizontal direction
  • the first direction may be a horizontal direction
  • the second direction may also be a vertical direction
  • the first direction and the second direction may also be other directions as long as the first direction and the second direction are two directions that are not parallel.
  • the material of the second wire 113 may be a metal or an alloy or a transparent conductive material.
  • the material of the second wire 113 is a metal or an alloy such that the second wire 113 has a small electrical resistance to enhance the conductivity of the second wire 113.
  • a transparent conductive material may be disposed in the through hole 1141 to electrically connect the first wire 112 and the second wire 113.
  • the transparent conductive material may be, but not limited to, Indium Tin Oxides (ITO).
  • the non-display area 120 further includes a second non-display sub-area 122 opposite to the first non-display sub-area 121, and a third non-display sub-area 123 and a fourth non-display sub-area 124.
  • the third non-display sub-area 123 and the fourth non-display sub-area 124 are oppositely disposed, and two ends of the third non-display sub-area 123 are respectively associated with the first non-display sub-area 121 and the second non-
  • the display sub-regions 122 are connected to each other, and two ends of the fourth non-display sub-region 124 are respectively connected to the first non-display sub-region 121 and the second non-display sub-region 122.
  • the first non-display sub-area 121 is a non-display area of the bottom end of the mobile phone, and the first non-display sub-area 121 is generally corresponding to a HOME key or a menu key provided with a mobile phone;
  • the display area 122 corresponds to the top end of the mobile phone, and the second non-display area 122 is generally corresponding to the brand identity of the mobile phone;
  • the third non-display sub-area 123 and the fourth non-display sub-area 124 are respectively Non-display area on both sides of the phone.
  • At least one of the second wires 113 includes a first portion 1131 and a second portion 1132 connected to the first portion 1131, the first portion 1311 is disposed along the second direction, and the first portion 1131 and the first wire 112 tiered settings.
  • the first portion 1131 and the first wire 112 are stacked in the same direction to prevent the first portion 1131 from being stacked with the first wire 112 (for example, the first portion 1131 and the first wire)
  • the effect of the light transmittance on the flat setting between 112 is to avoid a decrease in the transmittance of the array substrate 100 caused when the first portion 1131 is disposed on the array substrate 100.
  • the second portion 1132 is disposed along a first direction, and the second portion 1132 is stacked with the data line 111.
  • the second portion 1132 is stacked in the same direction as the data line 111 to prevent the second portion 1132 from being stacked with the data line 111 (eg, the second portion 1132 and the data line).
  • the effect of the light transmittance on the tiling between the 111s is to avoid a decrease in the transmittance of the array substrate 100 caused by the second portion 1132 being disposed on the array substrate 100.
  • the first conductive line 112, the first insulating layer 114, and the second conductive line 113 are sequentially stacked, and the data line 111 is disposed on the second conductive line through a second insulating layer 115. 113 on.
  • the first wire 112, the first insulating layer 114, and the second wire 113 are sequentially stacked, and the data line 111 is disposed through a second insulating layer 115.
  • the second wire 113 is away from the surface of the first insulating layer 114.
  • the first non-display sub-region 121 is disposed corresponding to the bottom end of the display region 110.
  • the array substrate 100 of the present invention is provided with the first insulating layer 114 on a plurality of the first wires 112, and the second wires 113 are disposed on the first insulating layer 114.
  • a plurality of through holes 1141 are disposed on the first insulating layer 114
  • the second wires 113 are electrically connected to the first wires 112 through the corresponding through holes 1141
  • the other end of the second wires 113 and the data lines are 111 is electrically connected together to the same first non-display sub-area.
  • the wiring on the non-display sub-areas on both sides of the array substrate 100 is reduced, thereby reducing the non-display sub-area of the array substrate 100.
  • the width, that is, the array substrate 100 has a narrow bezel.
  • FIG. 3 is a schematic structural diagram of a display panel according to a preferred embodiment of the present invention.
  • the display panel 10 includes the array substrate 100, the color filter substrate 200, and the liquid crystal layer 300 as shown in FIGS. 1 and 2.
  • the array substrate 100 is disposed opposite to the color filter substrate 200
  • the liquid crystal layer 300 is disposed between the array substrate 100 and the color filter substrate 200 .
  • the thin film transistor array 100 includes a display area 110 and a non-display area 120 disposed around the display area 110.
  • the non-display area 120 includes a first non-display sub-area 121 disposed on one side of the display area 110, and an integrated chip 1211 is disposed in the first non-display sub-area 121.
  • the integrated chip 1211 is used for signals and processes the feedback signals. For example, the integrated chip 1211 can transmit a scan signal to a scan line or a data signal to a data line.
  • the display area 110 is provided with a plurality of data lines 111 disposed along the first direction, a plurality of first conductive lines 112 disposed along the second direction, and a plurality of second conductive lines 113.
  • the first wire 112 includes a gate line or a common line.
  • a first insulating layer 114 is disposed between the first conductive line 112 and the second conductive line 113, and a plurality of via holes 1141 are disposed on the first insulating layer 114.
  • Each of the first wires 112 is electrically connected to one end of the second wire 113 through a corresponding through hole 1141 , and the other end of the second wire 113 and the data line 111 are electrically connected to the integrated chip 1121 .
  • the first direction is a vertical direction
  • the second direction is a horizontal direction. It can be understood that in other embodiments, the first direction may be a horizontal direction, and the second direction may also be a vertical direction. In other embodiments, the first direction and the second direction may also be other directions as long as the first direction and the second direction are two directions that are not parallel.
  • the material of the second wire 113 may be a metal or an alloy or a transparent conductive material.
  • the material of the second wire 113 is a metal or an alloy such that the second wire 113 has a small electrical resistance to enhance the conductivity of the second wire 113.
  • a transparent conductive material may be disposed in the through hole 1141 to electrically connect the first wire 112 and the second wire 113.
  • the transparent conductive material may be, but not limited to, Indium Tin Oxides (ITO).
  • the non-display area 120 further includes a second non-display sub-area 122 opposite to the first non-display sub-area 121, and a third non-display sub-area 123 and a fourth non-display sub-area 124.
  • the first The third non-display sub-area 123 and the fourth non-display sub-area 124 are oppositely disposed, and the two ends of the third non-display sub-area 123 are respectively associated with the first non-display sub-area 121 and the second non-display sub-area 122 is connected, and two ends of the fourth non-display sub-area 124 are respectively connected to the first non-display sub-area 121 and the second non-display sub-area 122.
  • the first non-display sub-region 121 is a non-display area of the bottom end of the mobile phone, and the first non-display sub-region 121 is generally correspondingly disposed.
  • the second non-display area 122 corresponds to the top end of the mobile phone, and the second non-display area 122 is generally corresponding to the brand identity of the mobile phone;
  • the third non-display sub-area 123 And the fourth non-display sub-area 124 are respectively non-display areas on both sides of the mobile phone.
  • At least one of the second wires 113 includes a first portion 1131 and a second portion 1132 connected to the first portion 1131, the first portion 1311 is disposed along the second direction, and the first portion 1131 and the first wire 112 tiered settings.
  • the first portion 1131 and the first wire 112 are stacked in the same direction to prevent the first portion 1131 from being stacked with the first wire 112 (for example, the first portion 1131 and the first wire)
  • the effect of the light transmittance on the flat setting between 112 is to avoid a decrease in the transmittance of the array substrate 100 caused when the first portion 1131 is disposed on the array substrate 100.
  • the second portion 1132 is disposed along a first direction, and the second portion 1132 is stacked with the data line 111.
  • the second portion 1132 is stacked in the same direction as the data line 111 to prevent the second portion 1132 from being stacked with the data line 111 (eg, the second portion 1132 and the data line).
  • the effect of the light transmittance on the tiling between the 111s is to avoid a decrease in the transmittance of the array substrate 100 caused by the second portion 1132 being disposed on the array substrate 100.
  • the first conductive line 112, the first insulating layer 114, and the second conductive line 113 are sequentially stacked, and the data line 111 is disposed on the second conductive line through a second insulating layer 115. 113 on.
  • the first wire 112, the first insulating layer 114, and the second wire 113 are sequentially stacked, and the data line 111 is disposed through a second insulating layer 115.
  • the second wire 113 is away from the surface of the first insulating layer 114.
  • the first non-display sub-region 121 is disposed corresponding to the bottom end of the display region 110.
  • the array substrate 100 in the display panel 10 of the present invention is provided with the first insulating layer 114 on a plurality of the first wires 112, and is disposed on the first insulating layer 114.
  • a second wire 113 is disposed on the first insulating layer 114.
  • the second wire 113 is electrically connected to the first wire 112 through a corresponding through hole 1141, and the other end of the second wire 113 is connected.
  • the data line 111 is electrically connected to the same first non-display sub-area.
  • the wiring on the non-display sub-regions on both sides of the array substrate 100 is reduced, thereby reducing the width of the non-display sub-region of the array substrate 100, that is, the display panel 10 including the array substrate 100 has A narrower border.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（100）及显示面板（10）。所述阵列基板（100）包括显示区域（110）及围绕所述显示区域（110）设置的非显示区域（120）；所述非显示区域（120）包括设置在所述显示区域（110）一侧的第一非显示子区域（121），所述第一非显示子区域（121）内设置有集成芯片（1211）；所述显示区域（110）设置有：沿第一方向设置的多条数据线（111）；沿第二方向设置的多条第一导线（112），其中，所述第一导线（112）包括扫描线或公共电极线；及多条第二导线（113）；所述第一导线（112）与所述第二导线（113）之间设置第一绝缘层（114），所述第一绝缘层（114）上设置多个贯孔（1141）；每条第一导线（112）通过相应贯孔（1141）与所述第二导线（113）的一端电连接；所述第二导线（113）的另一端以及所述数据线（111）与所述集成芯片（1211）电连接。所述阵列基板（100）具有较窄的边框。

Description

阵列基板及显示面板
本发明要求2014年12月30日递交的发明名称为“阵列基板及显示面板”的申请号201410848784.3的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉显示领域，尤其涉及一种阵列基板及显示面板。
背景技术
随着技术的进步，手机等电子装置得到越来越广泛地应用。手机等电子装置的性能和构造也越来越丰富以满足使用者的各种需求，窄边框也成为一种趋势而被提出。窄边框的显示面板不仅能够提升面板的使用率而且能够提升产品观感和用户体验。手机等电子装置通常包括显示面板，显示面板包括显示区域及非显示区域。显示区域通常是用于显示图像、文字或者视频的区域，非显示区域也称为边框区域，所述非显示区域设置在显示区域的四周，通常，所述非显示区域包括邻近所述显示区域的顶部、底部、左侧以及右侧设置的四个非显示子区域，每个非显示子区域上均设置有线路或者集成芯片。因此，现有技术中显示面板的边框较宽，因此，影响产品的观感和用户体验。
发明内容
本发明提供一种阵列基板，所述阵列基板使得包括所述阵列基板的显示面板具有较窄的边框。
所述阵列基板包括显示区域及围绕所述显示区域设置的非显示区域；
所述非显示区域包括设置在所述显示区域一侧的第一非显示子区域，所述第一非显示子区域内设置有集成芯片；
所述显示区域设置有：
沿第一方向设置的多条数据线；
沿第二方向设置的多条第一导线，其中，所述第一导线包括扫描线或 公共电极线；及
多条第二导线；
所述第一导线与所述第二导线之间设置第一绝缘层，所述第一绝缘层上设置多个贯孔；
每条第一导线通过相应贯孔与所述第二导线的一端电连接；
所述第二导线的另一端以及所述数据线与所述集成芯片电连接。
其中，至少一所述第二导线包括第一部分及与所述第一部分相连的第二部分，所述第一部分沿所述第二方向设置，且所述第一部分与所述第一导线层叠设置。
其中，所述第二部分沿所述第一方向设置，且所述第二部分与所述数据线层叠设置。
其中，所述第一导线、所述第一绝缘层及所述第二导线依次层叠设置，所述数据线通过第二绝缘层设置于所述第二导线上或者所述数据线通过第二绝缘层设置于所述第一导线远离所述第一绝缘层的表面。
其中，所述第一非显示子区域对应所述显示区域的底端设置。
另一方面，提供了一种显示面板，所述显示面板具有较窄的边框。
所述显示面板包括阵列基板，所述阵列基板包括显示区域及围绕所述显示区域设置的非显示区域；
所述非显示区域包括设置在所述显示区域一侧的第一非显示子区域，所述第一非显示子区域内设置有集成芯片；
所述显示区域设置有：
沿第一方向设置的多条数据线；
沿第二方向设置的多条第一导线，其中，所述第一导线包括扫描线或公共电极线；及
多条第二导线；
所述第一导线与所述第二导线之间设置第一绝缘层，所述第一绝缘层上设置多个贯孔；
每条第一导线通过相应贯孔与所述第二导线的一端电连接，
所述第二导线的另一端以及所述数据线与所述集成芯片电连接。
其中，至少一所述第二导线包括第一部分及与所述第一部分相连的第二部分，所述第一部分沿所述第二方向设置，且所述第一部分与所述第一导线层叠设置。
其中，所述第二部分沿所述第一方向设置，且所述第二部分与所述数据线层叠设置。
其中，所述第一导线、所述第一绝缘层及所述第二导线依次层叠设置，所述数据线通过第二绝缘层设置于所述第二导线上或者所述数据线通过第二绝缘层设置于所述第一导线远离所述第一绝缘层的表面。
其中，所述第一非显示子区域对应所述显示区域的底端设置。
与现有技术相较，本发明的阵列基板及显示面板中的阵列基板通过在多个所述第一导线上设置所述第一绝缘层，并在所述第一绝缘层上设置所述第二导线，所述第一绝缘层上设置多个贯孔，所述第二导线通过相应贯孔与所述第一导线电连接，并且第二导线的另一端与所述数据线一起电连接至同一第一非显示子区域。由此，减少了所述阵列基板两侧的非显示子区域上的布线，从而减小了所述阵列基板的非显示子区域的宽度，即所述阵列基板具有较窄的边框。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的结构示意图。
图2为图1中沿I-I线的剖面结构示意图。
图3为本发明一较佳实施方式的显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造 性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1和图2，图1为本发明一较佳实施方式的阵列基板的结构示意图；图2为图1中沿I-I线的剖面结构示意图。所述阵列基板(thin film transistor array)100包括显示区域110及围绕所述显示区域110设置的非显示区域120。所述非显示区域120包括设置在所述显示区域110一侧的第一非显示子区域121，所述第一非显示子区域121内设置有集成芯片1211。所述集成芯片1211用于信号并将反馈回来的信号进行处理。比如，所述集成芯片1211可以发射扫描信号至扫描线或者是数据信号至数据线。所述显示区域110内设有沿第一方向设置的多条数据线111，沿第二方向设置的多条第一导线112，及多条第二导线113。其中，所述第一导线112包括扫描线(gate line)或公共电极线(common line)。所述第一导线112与所述第二导线113之间设置第一绝缘层114，所述第一绝缘层114上设置多个贯孔(via hole)1141。每条第一导线112通过相应的贯孔1141与所述第二导线113的一端电连接，所述第二导线113的另一端以及所述数据线111与所述集成芯片1121电连接。在本实施方式中，所述第一方向为竖直方向，所述第二方向为水平方向。可以理解地，在其他实施方式中，所述第一方向可以为水平方向，所述第二方向也可以为竖直方向。在其他实施方式中，所述第一方向和所述第二方向也可以为其他方向，只要所述第一方向和所述第二方向为不平行的两个方向即可。
所述第二导线113的材料可以为金属或者是合金或者是透明的导电材料。优选地，所述第二导线113的材料为金属或是合金，以使得所述第二导线113具有较小的电阻，以提升所述第二导线113的传导能力。所述贯孔1141内可以设置透明的导电材料以使得所述第一导线112与所述第二导线113电连接。所述透明导电材料可以为但不仅限于为铟锡氧化物(Indium Tin Oxides，ITO)。
所述非显示区域120还包括与所述第一非显示子区域121相对的第二非显示子区域122，以及第三非显示子区域123和第四非显示子区域124。所述第三非显示子区域123和所述第四非显示子区域124相对设置，且所述第三非显示子区域123的两端分别与所述第一非显示子区域121和第二非显示子区域122相连，所述第四非显示子区域124的两端分别与所述第一非显示子区域121和第二非显示子区域122相连。当所述阵列基板100应用于一电子装置中比如 手机中时，所述第一非显示子区域121为所述手机的底端的非显示区域，所述第一非显示子区域121通常对应设置有手机的HOME键或者菜单键；所述第二非显示区域122对应所述手机的顶端，所述第二非显示区域122上通常对应设置有手机的品牌标识；所述第三非显示子区域123和所述第四非显示子区域124分别为所手机的两侧的非显示区域。
至少一个所述第二导线113包括第一部分1131和所述第一部分1131相连的第二部分1132，所述第一部分1311沿所述第二方向设置，且所述第一部分1131与所述第一导线112层叠设置。所述第一部分1131与所述第一导线112沿同一方向且层叠设置，以避免所述第一部分1131与所述第一导线112不层叠设置(比如，所述第一部分1131与所述第一导线112之间平铺设置)时对透光率的影响，以避免在所述阵列基板100上设置第一部分1131时造成的所述阵列基板100透光率的下降。
所述第二部分1132沿第一方向设置，且所述第二部分1132与所述数据线111层叠设置。所述第二部分1132与所述数据线111沿同一方向且层叠设置，以避免所述第二部分1132与所述数据线111不层叠设置(比如，所述第二部分1132与所述数据线111之间平铺设置)时对透光率的影响，以避免在所述阵列基板100上设置第二部分1132时造成的所述阵列基板100透光率的下降。
在本实施方式中，所述第一导线112、所述第一绝缘层114及所述第二导线113依次层叠设置，所述数据线111通过一第二绝缘层115设置于所述第二导线113上。可以理解地，在其他实施方式中，所述第一导线112、所述第一绝缘层114及所述第二导线113依次层叠设置，所述数据线111通过一第二绝缘层115设置于所述第二导线113远离所述第一绝缘层114的表面。
优选地，所述第一非显示子区域121对应所述显示区域110的底端设置。
与现有技术相较，本发明的阵列基板100通过在多个所述第一导线112上设置所述第一绝缘层114，并在所述第一绝缘层114上设置所述第二导线113，所述第一绝缘层114上设置多个贯孔1141，所述第二导线113通过相应贯孔1141与所述第一导线112电连接，并且第二导线113的另一端与所述数据线111一起电连接至同一第一非显示子区域。由此，减少了所述阵列基板100两侧的非显示子区域上的布线，从而减小了所述阵列基板100的非显示子区域的 宽度，即所述阵列基板100具有较窄的边框。
下面结合图1和图2对本发明显示面板进行介绍。请一并参阅图3，图3为本发明一较佳实施方式的显示面板的结构示意图。所述显示面板10包括如图1和图2所示的阵列基板100、彩色滤光基板200及液晶层300。所述阵列基板100与所述彩色滤光基板200相对设置，所述液晶层300设置于所述阵列基板100与所述彩色滤光基板200之间。
所述阵列基板(thin film transistor array)100包括显示区域110及围绕所述显示区域110设置的非显示区域120。所述非显示区域120包括设置在所述显示区域110一侧的第一非显示子区域121，所述第一非显示子区域121内设置有集成芯片1211。所述集成芯片1211用于信号并将反馈回来的信号进行处理。比如，所述集成芯片1211可以发射扫描信号至扫描线或者是数据信号至数据线。所述显示区域110内设有沿第一方向设置的多条数据线111，沿第二方向设置的多条第一导线112，及多条第二导线113。其中，所述第一导线112包括扫描线(gate line)或公共电极线(common line)。所述第一导线112与所述第二导线113之间设置第一绝缘层114，所述第一绝缘层114上设置多个贯孔(via hole)1141。每条第一导线112通过相应的贯孔1141与所述第二导线113的一端电连接，所述第二导线113的另一端以及所述数据线111与所述集成芯片1121电连接。在本实施方式中，所述第一方向为竖直方向，所述第二方向为水平方向。可以理解地，在其他实施方式中，所述第一方向可以为水平方向，所述第二方向也可以为竖直方向。在其他实施方式中，所述第一方向和所述第二方向也可以为其他方向，只要所述第一方向和所述第二方向为不平行的两个方向即可。
所述第二导线113的材料可以为金属或者是合金或者是透明的导电材料。优选地，所述第二导线113的材料为金属或是合金，以使得所述第二导线113具有较小的电阻，以提升所述第二导线113的传导能力。所述贯孔1141内可以设置透明的导电材料以使得所述第一导线112与所述第二导线113电连接。所述透明导电材料可以为但不仅限于为铟锡氧化物(Indium Tin Oxides，ITO)。
所述非显示区域120还包括与所述第一非显示子区域121相对的第二非显示子区域122，以及第三非显示子区域123和第四非显示子区域124。所述第 三非显示子区域123和所述第四非显示子区域124相对设置，且所述第三非显示子区域123的两端分别与所述第一非显示子区域121和第二非显示子区域122相连，所述第四非显示子区域124的两端分别与所述第一非显示子区域121和第二非显示子区域122相连。当所述阵列基板100应用于一电子装置中比如手机中时，所述第一非显示子区域121为所述手机的底端的非显示区域，所述第一非显示子区域121通常对应设置有手机的HOME键或者菜单键；所述第二非显示区域122对应所述手机的顶端，所述第二非显示区域122上通常对应设置有手机的品牌标识；所述第三非显示子区域123和所述第四非显示子区域124分别为所手机的两侧的非显示区域。
至少一个所述第二导线113包括第一部分1131和所述第一部分1131相连的第二部分1132，所述第一部分1311沿所述第二方向设置，且所述第一部分1131与所述第一导线112层叠设置。所述第一部分1131与所述第一导线112沿同一方向且层叠设置，以避免所述第一部分1131与所述第一导线112不层叠设置(比如，所述第一部分1131与所述第一导线112之间平铺设置)时对透光率的影响，以避免在所述阵列基板100上设置第一部分1131时造成的所述阵列基板100透光率的下降。
所述第二部分1132沿第一方向设置，且所述第二部分1132与所述数据线111层叠设置。所述第二部分1132与所述数据线111沿同一方向且层叠设置，以避免所述第二部分1132与所述数据线111不层叠设置(比如，所述第二部分1132与所述数据线111之间平铺设置)时对透光率的影响，以避免在所述阵列基板100上设置第二部分1132时造成的所述阵列基板100透光率的下降。
在本实施方式中，所述第一导线112、所述第一绝缘层114及所述第二导线113依次层叠设置，所述数据线111通过一第二绝缘层115设置于所述第二导线113上。可以理解地，在其他实施方式中，所述第一导线112、所述第一绝缘层114及所述第二导线113依次层叠设置，所述数据线111通过一第二绝缘层115设置于所述第二导线113远离所述第一绝缘层114的表面。
优选地，所述第一非显示子区域121对应所述显示区域110的底端设置。
与现有技术相较，本发明显示面板10中的阵列基板100通过在多个所述第一导线112上设置所述第一绝缘层114，并在所述第一绝缘层114上设置所 述第二导线113，所述第一绝缘层114上设置多个贯孔1141，所述第二导线113通过相应贯孔1141与所述第一导线112电连接，并且第二导线113的另一端与所述数据线111一起电连接至同一第一非显示子区域。由此，减少了所述阵列基板100两侧的非显示子区域上的布线，从而减小了所述阵列基板100的非显示子区域的宽度，即包括所述阵列基板100的显示面板10具有较窄的边框。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板，其中，所述阵列基板包括显示区域及围绕所述显示区域设置的非显示区域；
    所述非显示区域包括设置在所述显示区域一侧的第一非显示子区域，所述第一非显示子区域内设置有集成芯片；
    所述显示区域设置有：
    沿第一方向设置的多条数据线；
    沿第二方向设置的多条第一导线，其中，所述第一导线包括扫描线或公共电极线；及
    多条第二导线；
    所述第一导线与所述第二导线之间设置第一绝缘层，所述第一绝缘层上设置多个贯孔；
    每条第一导线通过相应贯孔与所述第二导线的一端电连接；
    所述第二导线的另一端以及所述数据线与所述集成芯片电连接。
  2. 如权利要求1所述的阵列基板，其中，至少一所述第二导线包括第一部分及与所述第一部分相连的第二部分，所述第一部分沿所述第二方向设置，且所述第一部分与所述第一导线层叠设置。
  3. 如权利要求2所述的阵列基板，其中，所述第二部分沿所述第一方向设置，且所述第二部分与所述数据线层叠设置。
  4. 如权利要求1所述的阵列基板，其中，所述第一导线、所述第一绝缘层及所述第二导线依次层叠设置，所述数据线通过第二绝缘层设置于所述第二导线上或者所述数据线通过第二绝缘层设置于所述第一导线远离所述第一绝缘层的表面。
  5. 如权利要求1所述的阵列基板，其中，所述第一非显示子区域对应所述 显示区域的底端设置。
  6. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括显示区域及围绕所述显示区域设置的非显示区域；
    所述非显示区域包括设置在所述显示区域一侧的第一非显示子区域，所述第一非显示子区域内设置有集成芯片；
    所述显示区域设置有：
    沿第一方向设置的多条数据线；
    沿第二方向设置的多条第一导线，其中，所述第一导线包括扫描线或公共电极线；及
    多条第二导线；
    所述第一导线与所述第二导线之间设置第一绝缘层，所述第一绝缘层上设置多个贯孔；
    每条第一导线通过相应贯孔与所述第二导线的一端电连接，
    所述第二导线的另一端以及所述数据线与所述集成芯片电连接。
  7. 如权利要求6所述的显示面板，其中，至少一所述第二导线包括第一部分及与所述第一部分相连的第二部分，所述第一部分沿所述第二方向设置，且所述第一部分与所述第一导线层叠设置。
  8. 如权利要求7所述的显示面板，其中，所述第二部分沿所述第一方向设置，且所述第二部分与所述数据线层叠设置。
  9. 如权利要求6所述的显示面板，其中，所述第一导线、所述第一绝缘层及所述第二导线依次层叠设置，所述数据线通过第二绝缘层设置于所述第二导线上或者所述数据线通过第二绝缘层设置于所述第一导线远离所述第一绝缘层的表面。
  10. 如权利要求6所述的显示面板，其中，所述第一非显示子区域对应所 述显示区域的底端设置。
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