WO2016119373A1 - 阵列基板、触控面板及阵列基板的制作方法 - Google Patents

阵列基板、触控面板及阵列基板的制作方法 Download PDF

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Publication number
WO2016119373A1
WO2016119373A1 PCT/CN2015/081640 CN2015081640W WO2016119373A1 WO 2016119373 A1 WO2016119373 A1 WO 2016119373A1 CN 2015081640 W CN2015081640 W CN 2015081640W WO 2016119373 A1 WO2016119373 A1 WO 2016119373A1
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Prior art keywords
common electrode
array substrate
pixel units
layer
sub
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PCT/CN2015/081640
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English (en)
French (fr)
Inventor
王海生
董学
薛海林
陈希
刘英明
丁小梁
赵卫杰
杨盛际
刘红娟
李昌峰
刘伟
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/892,419 priority Critical patent/US11139317B2/en
Publication of WO2016119373A1 publication Critical patent/WO2016119373A1/zh
Priority to US17/478,471 priority patent/US11710748B2/en
Priority to US18/199,003 priority patent/US20230299092A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate

Definitions

  • Embodiments of the present invention relate to an array substrate, a touch panel, and a method of fabricating an array substrate.
  • touch panels and display functions are combined to form more and more touch panels, and more common touch panels include resistive touch panels, capacitive touch panels, and optical touch panels.
  • Capacitive touch panels have become mainstream touch panels due to their high accuracy, multi-touch and high touch resolution.
  • the capacitive touch panel is generally divided into a mutual-capacitive touch panel and a self-capacitive touch panel.
  • the self-capacitive touch panel is realized by a simple single-layer self-capacitance electrode structure. It has the advantage of lower cost and is therefore more widely used.
  • Embodiments of the present invention provide a method for fabricating an array substrate, a touch panel, and an array substrate to increase an aperture ratio of a pixel unit.
  • At least one embodiment of the present invention provides an array substrate including a substrate substrate and a plurality of gate lines, a plurality of data lines, a common electrode layer, and a plurality of arrays arranged on the substrate substrate a pixel unit, each of the pixel units includes a plurality of sub-pixel units surrounded by gate lines and data lines disposed laterally and vertically; the common electrode layer includes a plurality of common electrode blocks that can be reused as self-capacitance electrodes One of the common electrode blocks is connected to at least one wire, and the wires are located in the middle of each of the sub-pixel units in the same column.
  • At least one embodiment of the present invention also provides a touch panel including the array substrate in the above technical solution.
  • At least one embodiment of the present invention further provides a method for fabricating an array substrate in the above technical solution, the method comprising: forming a plurality of gate lines and a plurality of data lines on a substrate; above the substrate Forming a common electrode layer such that the common electrode layer includes a plurality of common electrode blocks that can be reused as self-capacitating electrodes, one of the common electrode blocks is connected with at least one wire; and forming a plurality of pixel units arranged in an array So that each of the pixel units includes a plurality of locations arranged by horizontal and vertical intersections
  • the gate line and the data line are surrounded by sub-pixel units, and the wires are located in the middle of each of the sub-pixel units in the same column.
  • 1a is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 1b is a schematic structural diagram of a pixel unit including red, blue, and green sub-pixel units for each pixel unit according to an embodiment of the present disclosure
  • Figure 2 is a diagram showing the connection relationship between the wire and the common electrode block of Figure 1a;
  • FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 4 is a connection diagram of a wire and a common electrode block in another embodiment
  • Figure 5 is a cross-sectional view taken along line B-B of Figure 1a or Figure 3;
  • FIG. 6 is a timing diagram of a time-division driving touch panel according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a flowchart of a specific implementation manner of a method for fabricating an array substrate according to an embodiment of the present invention.
  • the self-capacitive touch panel includes a plurality of pixel units, and in the pixel unit, there is a certain space between the wires connected to the self-capacitance electrodes and the adjacent data lines, and the wires And the data line itself is opaque, so in order to prevent light leakage in the space between the wire and the data line, the black matrix of the self-capacitive touch panel needs to cover the space between the data line, the wire, and the data line and the wire, which results in The coverage of the black matrix is large, which in turn causes the aperture ratio of the pixel unit to decrease.
  • an array substrate 10 includes: a substrate substrate 12, a plurality of gate lines 13 disposed on the substrate substrate 12, a plurality of data lines 16, a common electrode layer 18, and a plurality of pixel units 30 arranged in an array, each of the pixel units 30 includes a plurality of sub-pixel units 31, each sub-pixel unit 31 is surrounded by gate lines 13 and data lines 16 disposed laterally and vertically; the common electrode layer 18 includes The plurality of common electrode blocks 23 are used as self-capacitating electrodes, and one common electrode block 23 is connected to at least one of the wires 11, and the wires 11 are located in the middle of each of the sub-pixel units 31 in the same column (as shown in FIG. 1a). For example, as shown in FIG. 1a, each sub-pixel unit of column A shares one wire 11, and the wire 11 is located in the middle of each sub-pixel unit of column A.
  • each sub-pixel unit in the same column is for the extending direction of the wire 11 and is Refers to a sub-pixel unit disposed along the direction in which the wire 11 extends.
  • the middle portion of each sub-pixel unit refers to a central region (ie, an open region) of each sub-pixel unit, which is relative to a periphery (occlusion region) of each sub-pixel unit.
  • the wires may be disposed in the same layer as the data lines or the gate lines, such that the wires, and the data lines or the gate lines may be formed by one patterning process; or the wires and the data lines or the gate lines may be disposed in different layers, For example, when a wire is separately formed by one patterning process, or when the wire is formed in synchronization with other film layers on the array substrate (for example, a layer in which the gate is located), the wire and the gate line or the data line may be disposed in different layers.
  • the wires 11 connected to the common electrode layer 18 are located in the middle of each sub-pixel unit in the same column (for example, the wires are disposed on the pixel electrode of the sub-pixel unit and the common electrode block on the substrate substrate).
  • the area with the common orthographic projection), the middle of the sub-pixel unit belongs to the open area, and the open area has no black matrix coverage, so the black matrix only needs to cover the data line 16 (or the gate line 13); since the wire 11 is very thin, Even if it is not visible in the sub-pixel unit, the black matrix is not required to block the space between the wire 11 and the data line 16 (or the gate line 13) and the wire 11, so that the embodiment of the present invention can reduce the coverage of the black matrix.
  • the wire 11 and the data line 16 may be disposed in the same layer, and in the process of fabricating the array substrate 10, the wire may be formed by one patterning process. 11 and data 16 (or gate line 13), thereby reducing the masking process.
  • the arrangement of the wires 11 in the array substrate is various, for example, but not limited to the following modes of arrangement in the embodiment of the present invention.
  • each common electrode block 23 is connected with a wire 11 , and each sub-pixel unit in which the wire 11 is located belongs to a different pixel unit.
  • the wires 11 are arranged in this manner, one wire 11 does not appear in two or more sub-pixel units in the same pixel unit, and only one of the pixel units corresponds to the wire 11.
  • a partial pixel area of the array substrate is indicated in the figure, including 9 columns and 5 rows of sub-pixel units, and a broken line indicates a region corresponding to the common electrode block 23.
  • Figure 1a Just a schematic.
  • each common electrode block 23 corresponds to the same number of sub-pixel units, and one common electrode block 23 is connected to only one wire 11 .
  • the first three sub-pixel units of the first row of sub-pixel units constitute one pixel unit. In the unit, only one sub-pixel unit is provided with a wire 11.
  • the display device including the array substrate further includes a driving circuit, or the driving circuit can be directly disposed on the array substrate, and the driving circuit (hereinafter referred to as an integrated circuit 27) can be as shown in FIG. 2 .
  • the drive IC 27 is a component for driving a touch function and/or a component for realizing a display function; the common electrode block 23 is connected to the drive IC 27 through a wire 11.
  • a common electrode block 23 is connected to only one wire 11, and therefore, a common electrode block 23 is connected to the driving IC 27 through a wire 11.
  • each pixel unit includes at least red (R), blue (B), and green (G) three-color sub-pixel units, and in each pixel unit, a wire connected to the common electrode 11 is disposed in the middle of one of the red, blue, and green three-color sub-pixel units.
  • the wire 11 connected to the common electrode 18 is provided in the middle of the blue sub-pixel unit among the red, blue, and green three-color sub-pixel units.
  • each pixel unit includes red, blue, and green three-color sub-pixel units
  • the same column of pixel units includes three columns of sub-pixel units, which are a column of red sub-pixel units, a column of blue sub-pixel units, and a column of green sub-pixel units, and the wire 11
  • a middle portion of each column of each of the blue sub-pixel units is disposed in the column of pixel units.
  • each of the common electrode blocks 23 is connected with a plurality of wires 11, and the middle portions of the plurality of sub-pixel cells in each of the pixel cells respectively correspond to the wires 11.
  • the common electrode block 23 located at the distal end of the driving IC 27 is connected to the driving IC 27 through a plurality of wires 11, and the rest is located near the driving IC 27.
  • the common electrode block 23 at the end is connected to the drive IC 27 via a wire 11.
  • each common electrode block 23 in the upper dotted frame is a common electrode block located at the distal end of the driving IC 27, and is connected to the driving IC 27 through two wires 11;
  • the common electrode block 23 in the lower dotted line frame is a common electrode block located at the proximal end of the driving IC, and is connected to the driving IC through a wire 11; thus, the design can reduce the delay caused by the signal transmission during the driving process, and the other In terms of the relative arrangement mode 2, the number of wires 11 can also be reduced.
  • the distal end in this embodiment refers to the distance of the common electrode block from the driving IC 27, and the distance from the driving IC 27 is called the far end, and the distance from the IC 27 is called the near end; for example, if the entire array substrate is There are 20 rows of pixel units arranged from top to bottom and 10 rows of common electrode blocks are provided.
  • the common electrode block at the intermediate position can be used as a reference point, and the first two rows or three rows located above are referred to as located at the far end of the drive IC 27.
  • the common electrode block, while the other rows are referred to as common electrode blocks located at the proximal end of the drive IC 27.
  • the number of common electrode blocks located at the far end and the near end can be set according to actual needs, and will not be described here.
  • one common electrode block 23 corresponds to a plurality of sub-pixel units, such as: a common electrode as shown in FIG. 1a.
  • the shape of the common electrode block 23 may be, for example, a square, a rectangle, a diamond, or other regular polygon; for example, the common electrode block 23 is a square electrode block having a side length of 4 mm to 5 mm.
  • the wires 11 can be disposed below the common electrode layer 18, or the wires 11 can also be disposed over the common electrode layer 18 (eg, the wires are formed by a separate patterning process).
  • the array substrate 10 may further include a first protective layer 17 disposed on the wire 11, and the common electrode layer 18 may be disposed on the first protective layer 17, as shown in FIG. 5; or, the array substrate 10 may be disposed in a common a first protective layer on the electrode layer, the wire being disposed on the first protective layer.
  • the array substrate 10 in the embodiment of the present invention may further include a gate insulating layer 14 disposed on the plurality of gate lines 13 and disposed on the gate insulating layer 14 in addition to the above structure.
  • the upper active layer 15, the plurality of data lines 16 and the wires 11 are disposed above the active layer 15, the first protective layer 17 is disposed on the plurality of data lines 16 and the wires 11, and the common electrode layer 18 is disposed in the first protection On the layer 17, a second protective layer 19 is provided on the first protective layer 17 and the common electrode layer 18, and a pixel electrode 20 is provided on the second protective layer 19.
  • the sub-pixel unit includes a gate layer 24 disposed on the base substrate 12 (since the gate line 13 and the gate are formed in the same layer of metal, 24 in the figure indicates the gate line 13 And a gate electrode, hereinafter referred to as a gate layer), a gate insulating layer 14 disposed on the gate layer 24, and an active layer 15 disposed on the gate insulating layer 14 disposed on the active layer 15 a source 25/drain 26 and a wire 11, a first protective layer 17 disposed on the source 25/drain 26 and the wire 11, and a common electrode layer 18 disposed on the first protective layer 17, disposed at A protective layer 17 and a second protective layer 19 on the common electrode layer 18 are provided on the pixel electrode 20 on the second protective layer 19.
  • the common electrode layer 18 includes a plurality of common electrode blocks.
  • the common electrode block 23 in the common electrode layer 18 is connected to the wire 11.
  • the first protective layer 17 in the array substrate is provided with a first The via hole 21 and the common electrode block 23 are connected to the wire 11 through the first via hole 21.
  • the vias 21 in which the wires 11 and the common electrode blocks are connected in the drawing are only one of the connections, and the present application includes, but is not limited to, such a connection.
  • a second via 22 is provided on the second protective layer 19 in the array substrate 20, and the pixel electrode 20 is connected to the drain 25 through the second via 22.
  • each common electrode block in the same column refers to a common electrode block disposed at a position where the wire is located in the extending direction of the wire 11 with respect to the extending direction of the wire 11.
  • the direction of the column in which the common electrode blocks of the same column are located also changes accordingly.
  • At least one embodiment of the present invention further provides a touch panel including the array substrate 10, and the touch panel can be applied to a liquid crystal display panel, an electronic paper, and an organic light emitting diode panel (Organic Light-Emitting Diode) , referred to as OLED panel), mobile phones, tablets, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • a touch panel including the array substrate 10
  • the touch panel can be applied to a liquid crystal display panel, an electronic paper, and an organic light emitting diode panel (Organic Light-Emitting Diode) , referred to as OLED panel), mobile phones, tablets, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • OLED panel Organic Light-Emitting Diode
  • the touch panel in the above embodiment combines the touch function and the display function, the touch function and the display function can be implemented; in order to prevent the touch function from being used, the common electrode block is used as the touch signal received by the self-capacitance electrode.
  • the total driving time T of the 1-frame signal is 16.7 ms, T1 is 11.7 ms, T2 is 5 ms, and the first 11.7 ms of the 1-frame signal is used for the display function driving.
  • the last 5 ms of the above 1-frame signal is used for the driving of the touch function; in FIG. 6, Gate 1 to Gate n are gate line signals, Data is a data line signal, and Tx/Rx is a common electrode used as a self-capacitance electrode.
  • the block drives the signal of the touch function.
  • At least one embodiment of the present invention further provides a method for fabricating the above array substrate, the method comprising the following steps 201 to 204, which are described in detail below.
  • a plurality of gate lines 13 are formed on the base substrate 12.
  • a gate line layer is formed on the base substrate 12, and a pattern including a plurality of gate lines 13 is formed by a patterning process.
  • Step 202 forming a plurality of data lines 16 above the substrate substrate 12 (eg, over the plurality of gate lines 13). For example, a data line layer is formed first over the plurality of gate lines 13, and a pattern including the plurality of data lines 16 is formed by a patterning process.
  • Step 203 forming a common electrode layer 18 over the base substrate 12 (for example, over the plurality of data lines 16); the common electrode layer 18 includes a plurality of common electrode blocks 23 that can be reused as self-capacitance electrodes, At least one wire 11 is connected to the common electrode block 23.
  • the wires 11 are disposed in the same layer as the data lines 16, so that during the fabrication of the array substrate 10, the data lines 16 and the wires 11 can be formed by one patterning process.
  • Step 204 forming a plurality of pixel units arranged in an array; each of the pixel units includes a plurality of sub-pixel units surrounded by the gate lines 13 and the data lines 16 disposed horizontally and vertically; The wires 11 are located in the middle of each of the sub-pixel units in the same column.
  • the wires and the data lines may be disposed in the same layer to be formed in the same patterning process, thereby reducing the mask process.
  • the wires and data lines can also be arranged in different layers.
  • the wires 11 connected to the common electrode 18 are formed in the middle of each sub-pixel unit in the same column, the middle portion of the sub-pixel unit belongs to the open region, and the open region has no black matrix. Covering, the black matrix only needs to cover the data line 16 (or the gate line 13), and it is no longer necessary to cover the space between the wire 11, the data line 16 (or the gate line 13) and the wire 11, so the embodiment of the invention can be reduced. The coverage of the black matrix increases the area of the open area, thereby increasing the aperture ratio of the pixel unit.
  • the wires 11 connected to the common electrode block and the data lines 16 (or the gate lines 13) are disposed in the same layer.
  • one time can be patterned.
  • the process forms the data line 16 (or the gate line 13) and the wire 11, thereby eliminating the masking process in which the wire 11 is separately formed, that is, reducing the masking process.
  • the manufacturing process of the array substrate 10, in particular, the manufacturing method of the sub-pixel unit in the array substrate 10, as shown in FIG. 8, the method for fabricating the array substrate 10 includes the following steps 301 to 307, respectively.
  • a plurality of gate lines 13 are formed on the base substrate 12. For example, while a plurality of gate lines 13 are formed, a gate electrode in the thin film transistor 23 is also formed.
  • Step 302 forming a pattern of the gate insulating layer 14 on the plurality of gate lines 13. It should be noted that the embodiment of the present invention is described by taking the gate of the thin film transistor 23 under the gate insulating layer 14 as an example.
  • Step 303 forming a pattern of the active layer 15 on the gate insulating layer 14; the pattern of the active layer 15 includes a region corresponding to the channel between the drain 26 and the source/drain of the source 25 to be formed and to be The area of the formed wire 11 corresponding to it.
  • Step 304 forming a pattern of the data line 16, the wire 11 and the source 25/drain 26 on the active layer 15 by one patterning process.
  • the data line 16, the wire 11 and the source 25/drain 26 can be formed by one patterning process, that is, step 304 can be completed using a masking process.
  • Step 305 forming a first protective layer 17 on the data line 16, the wire 11 and the source 25 / drain 26 of the thin film transistor 23, forming a pattern including the first via 21 on the first protective layer 17 by a patterning process;
  • the common electrode block 23 is located on the first protective layer 17, and the common electrode block 23 is connected to the wire 11 through the first via hole 21.
  • Step 306 forming a second protective layer 19 on the first protective layer 17 and the common electrode block 23, and forming a pattern including the second via 22 on the second protective layer 19 and the first protective layer 17 by a patterning process.
  • step 307 a pattern of the pixel electrode 20 is formed on the second protective layer 19; the pixel electrode 20 is connected to the drain electrode 26 through the second via 22.
  • the wire 11 is disposed in the same layer as the data line 16, after the data line layer is formed over the gate insulating layer 14, the pattern of the data line 16 and the wire 11 is formed by one patterning process, and the mask 11 need not be separately masked. Thereby, a masking process is saved, the number of masks in the process of fabricating the array substrate 10 is reduced, and the manufacturing process of the array substrate 10 is simplified.

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  • General Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板、触控面板及阵列基板的制作方法，所述阵列基板包括衬底基板(12)和设置于所述衬底基板(12)上的多条栅线(13)、多条数据线(16)、公共电极层(18)和呈阵列状排列的多个像素单元(30)，每个像素单元(30)包括多个由横纵交叉设置的栅线(13)和数据线(16)围设成的子像素单元(31)；公共电极层(18)包括可复用作自容电极的多个公共电极块(23)，一个公共电极块(23)连接有至少一根导线(11)，且导线(11)位于同列的各子像素单元(31)的中部。该阵列基板用于增加像素单元(30)的开口率。

Description

阵列基板、触控面板及阵列基板的制作方法 技术领域
本发明实施例涉及一种阵列基板、触控面板及阵列基板的制作方法。
背景技术
目前，触控功能和显示功能结合形成的触控面板的应用越来越多，较常见的触控面板包括电阻式触控面板、电容式触控面板以及光学式触控面板等。电容式触控面板由于具有高准确率、多点触控以及高触控分辨率等优势，成为了主流的触控面板。电容式触控面板一般分为互容式触控面板和自容式触控面板，相对于互容式触控面板，自容式触控面板由结构较简单的单层自容电极结构实现，具有成本较低的优点，故使用较为广泛。
发明内容
本发明实施例提供一种阵列基板、触控面板及阵列基板的制作方法，以增大像素单元的开口率。
本发明的至少一个实施例提供了一种阵列基板，其包括衬底基板和设置于所述衬底基板上的多条栅线、多条数据线、公共电极层和呈阵列状排列的多个像素单元，每个所述像素单元包括多个由横纵交叉设置的栅线和数据线围设成的子像素单元；所述公共电极层包括可复用作自容电极的多个公共电极块，一个所述公共电极块连接有至少一根导线，且所述导线位于同列的各所述子像素单元的中部。
本发明的至少一个实施例还提供了一种触控面板，其包括上述技术方案中的阵列基板。
本发明的至少一个实施例还提供了一种上述技术方案中的阵列基板的制作方法，该方法包括：在衬底基板上形成多条栅线和多条数据线；在所述衬底基板上方形成公共电极层，使所述公共电极层包括可复用作自容电极的多个公共电极块，一个所述公共电极块连接有至少一根导线；以及形成呈阵列状排列的多个像素单元，使每个所述像素单元包括多个由横纵交叉设置的所 述栅线和所述数据线围设成的子像素单元，且所述导线位于同列的各所述子像素单元的中部。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1a为本发明实施例提供的一种阵列基板的结构示意图；
图1b为本发明实施例提供的一种每个像素单元包括红、蓝、绿三色子像素单元的结构示意图；
图2为图1a中导线与公共电极块的连接关系图；
图3为本发明实施例提供的另一种阵列基板的结构示意图；
图4为另一实施例中导线与公共电极块的连接关系图；
图5为图1a或图3中B-B方向的剖视图；
图6为本发明实施例提供的分时驱动触控面板的时序图；
图7为本发明实施例提供的阵列基板的制作方法的流程图；
图8为本发明实施例提供的阵列基板的制作方法的具体实现方式的流程图。
附图标记：
10-阵列基板，                  11-导线，
12-衬底基板，                  13-栅线，
14-栅极绝缘层，                15-有源层，
16-数据线，                    17-第一保护层，
18-公共电极层，                19-第二保护层，
20-像素电极，                  21-第一过孔，
22-第二过孔，                  23-公共电极块
24-栅线及栅极，                25-源极，
26-漏极，                      27-驱动IC。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在研究中，本申请的发明人注意到，自容式触控面板包括多个像素单元，在像素单元中，与自容电极连接的导线与相邻的数据线之间具有一定的空间，导线和数据线本身不透光，所以为了防止导线和数据线之间的空间发生漏光现象，自容式触控面板的黑矩阵需要覆盖数据线、导线以及数据线和导线之间的空间，这导致黑矩阵覆盖范围较大，进而导致像素单元的开口率减小。
请参阅图1a，本发明实施例提供的阵列基板10，包括：衬底基板12，设置在所述衬底基板12上的多条栅线13、多条数据线16、公共电极层18和呈阵列状排列的多个像素单元30，每个像素单元30包括多个子像素单元31，每个子像素单元31由横纵交叉设置的栅线13和数据线16围设成；公共电极层18包括可复用作自容电极的多个公共电极块23，一个公共电极块23连接有至少一根导线11，且导线11位于同列(如图1a所示)的各子像素单元31的中部。比如：如图1a所示，A列的各子像素单元共用一根导线11，且导线11位于A列的各子像素单元的中部。
需要说明的是，同列的各子像素单元是针对导线11的延伸方向而言，是 指沿导线11延伸方向上设置于该导线所在处的子像素单元。针对图1a所示的情形，当观察角度发生变化时，该同列的各子像素单元所在列的方向也相应变化。并且，各子像素单元的中部是指各子像素单元的中部区域(即开口区)，是相对于各子像素单元的周边(遮挡区域)而言。
在至少一个实施例中，导线与数据线或栅线可以同层设置，这样可以通过一次构图工艺形成导线、以及数据线或栅线；或者，导线与数据线或栅线也可以不同层设置，例如，通过一次构图工艺单独形成导线时，或者导线与阵列基板上的其他膜层(例如栅极所在的层)同步形成时，导线与栅线或数据线可以不同层设置。
本发明实施例提供的阵列基板10中，与公共电极层18连接的导线11位于同列的各子像素单元的中部(例如，导线设置于子像素单元的像素电极与公共电极块在衬底基板上有公共正投影的区域)，子像素单元的中部属于开口区，而开口区无黑矩阵覆盖，因此黑矩阵只需覆盖数据线16(或栅线13)即可；由于导线11很细，因此即使在子像素单元中也不可见，不需要用黑矩阵遮挡该导线11、以及数据线16(或栅线13)和导线11之间的空间，所以本发明实施例可以减少黑矩阵的覆盖范围，增大开口区的面积，从而增大像素单元的开口率。而且，在本发明实施例中，导线11和数据线16(或栅线13等阵列基板上原有的膜层)可以同层设置，在制作阵列基板10的过程中，通过一次构图工艺可形成导线11和数据16(或栅线13)，从而可减少了一次掩膜工序。
上述阵列基板中导线11的设置方式有多种，例如，在本发明实施例中包括、但不限于以下几种设置方式。
设置方式一，请参阅图1a，每个公共电极块23连接有一根导线11，且导线11所处的各子像素单元分别属于不同的像素单元。当导线11按照此设置方式设置时，一根导线11不会出现在同一个像素单元中的两个或者更多子像素单元中，一个像素单元中只有一个子像素单元与导线11对应。比如：如图1a所示，该图中标示阵列基板的部分像素区域，其中包括9列和5行的子像素单元，虚线表示公共电极块23对应的区域。本实施例中，标示出的区域包括上、下共两个公共电极块23，每个公共电极块23对应3*8＝24个子像素单元，下面的公共电极块23省略了一行子像素单元，可以理解的是，图1a 只是示意图。例如，每个公共电极块23均对应相同数量的子像素单元，一个公共电极块23只连接有一条导线11，第一行子像素单元中的前三个子像素单元组成一个像素单元，在该像素单元中，只有一个子像素单元中设有导线11。
需要说明的是，包括该阵列基板的显示装置还包括驱动电路，或者说该驱动电路可以直接设置在阵列基板上，驱动电路(以下简称驱动IC(Integrated circuit)27)可以如图2所示，该驱动IC 27为用于驱动实现触控功能的部件和/或实现显示功能的部件；公共电极块23通过导线11与驱动IC 27相连接。比如：请参阅图2，一个公共电极块23只连接有一根导线11，因此，一个公共电极块23通过一根导线11与驱动IC27相连。
进一步地，例如，如图1b所示，每个像素单元至少包括红(R)、蓝(B)、绿(G)三色子像素单元，在每个像素单元中，与公共电极连接的导线11设置在红、蓝、绿三色子像素单元中的一个子像素单元的中部。例如，由于蓝色子像素单元对透过率的影响最小，所以将与公共电极18连接的导线11设于红、蓝、绿三色子像素单元中的蓝色子像素单元的中部。比如，每个像素单元包括红、蓝、绿三色子像素单元，同列像素单元包括三列子像素单元，分别为一列红色子像素单元、一列蓝色子像素单元和一列绿色子像素单元，导线11设置在该列像素单元中的一列各蓝色子像素单元的中部。
设置方式二，请参阅图3，每个公共电极块23连接有多根导线11，每个像素单元中的多个子像素单元的中部分别对应有导线11。比如：如图3所示，在标示出的9列和5行的子像素单元中，每个公共电极块23对应3*8＝24个子像素单元，为了使各列子像素单元的中部都有导线11经过，因此，在8列子像素单元的中部各设有一根导线11。如此设计，可以在驱动时选用其中的一根导线11传递信号，其他的导线11作为备用导线，这样可以实现驱动电路的冗余设计，以提高驱动的可靠性。
设置方式三，请参阅图4，为了减少驱动过程中传递信号产生的延迟，例如，位于驱动IC 27远端的公共电极块23通过多根导线11与驱动IC 27连接，剩余的位于驱动IC27近端的公共电极块23通过一根导线11与驱动IC27连接。比如：请参阅图4，位于上方的虚线框中的各公共电极块23为位于驱动IC 27远端的公共电极块，通过两根导线11与驱动IC 27相连；位于 下方的虚线框中的各公共电极块23为位于驱动IC近端的公共电极块，通过一根导线11与驱动IC连接；如此设计，一方面可以减少驱动过程中传递信号产生的延迟，另一方面相对设置方式二，还可以减少导线11数量。
本实施例中的远端指公共电极块距离驱动IC 27的距离而言，距离驱动IC 27距离远的称为远端，距离IC 27距离近的称为近端；例如，如果整个阵列基板上自上而下设置有20行像素单元且设置有10行公共电极块，可以将位于中间位置的公共电极块作为参考点，将位于上面的前两行或者三行称为位于驱动IC 27远端的公共电极块，而其他行的称为位于驱动IC 27近端的公共电极块。当然，位于远端和近端的公共电极块的数量可以根据实际需要进行设置，此处不做赘述。
需要说明的是，由于公共电极块23可复用作自容电极，因此，在上述任一实施例中，一个公共电极块23对应多个子像素单元，比如：如图1a所示，一个公共电极块23对应3*8＝24个子像素单元。在至少一个实施例中，公共电极块23的形状例如可以为正方形、矩形、菱形或其它正多边形；例如，公共电极块23为边长4mm-5mm的正方形电极块。
在至少一个实施例中，导线11可以设置于公共电极层18的下方，或者，导线11也可以设置于公共电极层18的上方(例如，导线通过单独的构图工艺形成)。例如，阵列基板10还可以包括设置于导线11上的第一保护层17，公共电极层18可以设置在第一保护层17上，如图5所示；或者，阵列基板10可以包括设置于公共电极层上的第一保护层，导线设置于第一保护层上。
以图5所示的情形为例，本发明实施例中的阵列基板10除了包括上述结构外，还可以包括设置在多条栅线13上的栅极绝缘层14，设置在栅极绝缘层14上的有源层15，多条数据线16和导线11设置在有源层15上方，在多条数据线16和导线11上设有第一保护层17，公共电极层18设置在第一保护层17上，在第一保护层17和公共电极层18上设有第二保护层19，在第二保护层19上设有像素电极20。
下面以阵列基板10中的子像素单元为例，来说明上述阵列基板10的具体结构。
例如，请参考图5，子像素单元包括设置在衬底基板12上的栅极层24(由于栅线13与栅极为同一层金属同层形成，因此图中的24表示栅线13 及栅极，以下将该层24称为栅极层)，设置在栅极层24上的栅极绝缘层14，设置在栅极绝缘层14上的有源层15，设置在有源层15上的源极25/漏极26和导线11，设置在源极25/漏极26和导线11上的第一保护层17，设置在第一保护层17上的公共电极层18，设置在第一保护层17和公共电极层18上的第二保护层19，设置在第二保护层19上的像素电极20。需要说明的是，公共电极层18包括多个公共电极块。
在上述阵列基板10中，公共电极层18中的公共电极块23与导线11连接，例如，请参考图1a、图3和图5，在阵列基板中的第一保护层17上设置有第一过孔21，公共电极块23通过第一过孔21与导线11连接。附图中导线11与公共电极块连接的过孔21只是其中一种连接方式，本申请包括但不限于此种连接方式。此外，在阵列基板20中的第二保护层19上设置有第二过孔22，像素电极20通过第二过孔22与漏极25连接。
为了方便构图成型，如图2或图4所示，在至少一个实施例中，同列的各公共电极块23对应的各第一过孔21在衬底基板上的投影依次错开。如此既方便构图形成各第一过孔21，同时又方便构图形成各导线11。需要说明的是，同列的各公共电极块是针对导线11的延伸方向而言，是指沿导线11延伸方向上设置于该导线所在处的公共电极块。针对图2或图4所示的情形，当观察角度发生变化时，该同列的各公共电极块所在列的方向也相应变化。
本发明的至少一个实施例还提供了一种触控面板，触控面板包括上述阵列基板10，所述触控面板可以应用于液晶显示面板、电子纸、有机发光二极管面板(Organic Light-Emitting Diode，简称OLED面板)、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件中。
由于上述实施例中的触控面板将触控功能和显示功能结合，能够实现触控功能和显示功能；为了防止实现触控功能时，公共电极块复用作自容电极接收的触控信号被阵列基板中实现显示功能的栅线和数据线影响，通常采用分时驱动的方法来驱动该触控面板。例如，在1帧信号的驱动总时间T中，利用时间段T1进行显示功能的驱动，利用时间段T2进行触控功能的驱动，其中，T＝T1+T2。例如，请参考图6，1帧信号的驱动总时间T为16.7ms，T1为11.7ms，T2为5ms，将1帧信号中的前11.7ms用于显示功能的驱动， 将上述1帧信号的后5ms用于触控功能的驱动；在图6中，Gate 1至Gate n为栅线信号，Data为数据线信号，Tx/Rx为复用作自容电极的公共电极块驱动触控功能的信号。
如图7所示，本发明的至少一个实施例还提供了上述阵列基板的制作方法，该方法包括以下步骤201至步骤204，下面详细介绍这些步骤。
步骤201，在衬底基板12上形成多条栅线13。例如，在衬底基板12上先形成栅线层，再通过构图工艺形成包括多条栅线13的图形。
步骤202，在衬底基板12上方(例如，在多条栅线13上方)形成多条数据线16。例如，在多条栅线13上方先形成数据线层，再通过构图工艺形成包括多条数据线16的图形。
步骤203，在衬底基板12上方(例如，在多条数据线16上方)形成公共电极层18；所述公共电极层18包括可复用作自容电极的多个公共电极块23，一个所述公共电极块23连接有至少一根导线11。例如，所述导线11与所述数据线16同层设置，因此在阵列基板10的制作过程中，可以通过一次构图工艺形成数据线16和导线11。
步骤204，形成呈阵列状排列的多个像素单元；每个所述像素单元包括多个由横纵交叉设置的所述栅线13和所述数据线16围设成的子像素单元；且所述导线11位于同列的各所述子像素单元的中部。
在本发明实施例提供的阵列基板的制作方法中，导线与数据线(或栅线)可以同层设置以在同一次构图工艺中形成，从而减少一次掩膜工序。当然，导线与数据线(或栅线)也可以不同层设置。
在本发明实施例中，在制作阵列基板10的过程中，将与公共电极18连接的导线11制作在同列的各子像素单元的中部，子像素单元的中部属于开口区，开口区无黑矩阵覆盖，黑矩阵只需覆盖数据线16(或栅线13)即可，不再需要覆盖导线11、数据线16(或栅线13)和导线11之间的空间，所以本发明实施例可以减少黑矩阵的覆盖范围，增大开口区的面积，从而增大像素单元的开口率。本发明实施例中，在制作阵列基板10的过程中，与公共电极块连接的导线11和数据线16(或栅线13)同层设置，在制作阵列基板10的过程中，可以通过一次构图工艺形成数据线16(或栅线13)和导线11，从而省去导线11单独成形的掩膜工序，即减少一次掩膜工序。
下面结合图5，详细说明阵列基板10的制作过程，尤其是阵列基板10中子像素单元的制作方法，如图8所示，所述阵列基板10的制作方法，例如包括以下步骤301至307。
步骤301，在衬底基板12上形成多条栅线13。例如，在形成多条栅线13的同时，也形成了薄膜晶体管23中的栅极。
步骤302，在多条栅线13上形成栅极绝缘层14的图形。需要说明的是，本发明实施例以薄膜晶体管23中的栅极位于栅极绝缘层14下方为例进行说明。
步骤303，在栅极绝缘层14上形成有源层15的图形；有源层15的图形包括与待形成的源极25漏极26及源/漏极之间的沟道对应的区域和待形成的导线11对应的区域。
步骤304，通过一次构图工艺在有源层15上形成数据线16、导线11和源极25/漏极26的图形。可以通过一次构图工艺形成数据线16、导线11和源极25/漏极26，即利用一次掩膜工序即可完成步骤304。
步骤305，在数据线16、导线11和薄膜晶体管23的源极25/漏极26上形成第一保护层17，通过构图工艺在第一保护层17上形成包括第一过孔21的图形；所述公共电极块23位于所述第一保护层17上，所述公共电极块23通过所述第一过孔21与所述导线11连接。
步骤306，在第一保护层17和公共电极块23上形成第二保护层19，通过构图工艺在第二保护层19和第一保护层17上形成包括第二过孔22的图形。
步骤307，在第二保护层19上形成像素电极20的图形；像素电极20通过第二过孔22与漏极26连接。
由于导线11与数据线16同层设置，所以在栅极绝缘层14上方形成数据线层后，通过一次构图工艺形成了数据线16和导线11的图形，不需要对导线11单独进行掩膜工序，从而节省了一道掩膜工序，减少了制作阵列基板10过程中的掩膜次数，简化了阵列基板10的制作流程。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范 围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年1月27日递交的中国专利申请第201510041311.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种阵列基板，包括衬底基板和设置于所述衬底基板上的多条栅线、多条数据线、公共电极层和呈阵列状排列的多个像素单元，其中，
    每个所述像素单元包括多个由横纵交叉设置的栅线和数据线围设成的子像素单元；
    所述公共电极层包括可复用作自容电极的多个公共电极块，一个所述公共电极块连接有至少一根导线，且所述导线位于同列的各所述子像素单元的中部。
  2. 根据权利要求1所述的阵列基板，其中，所述导线与所述数据线或所述栅线同层设置或不同层设置。
  3. 根据权利要求1或2所述的阵列基板，其中，每个所述公共电极块连接有一根所述导线，且所述导线所在处的各所述子像素单元分别属于不同的所述像素单元。
  4. 根据权利要求3所述的阵列基板，其中，所述像素单元至少包括红、蓝、绿三色子像素单元；所述导线设于所述像素单元的红、蓝、绿三色子像素单元中的一个子像素单元中。
  5. 根据权利要求4所述的阵列基板，其中，所述导线设于红、蓝、绿三色子像素单元中的蓝色子像素单元中。
  6. 根据权利要求1或2所述的阵列基板，其中，每个所述公共电极块连接有多根所述导线，每个所述像素单元中的多个所述子像素单元的中部分别对应有所述导线。
  7. 根据权利要求1或2所述的阵列基板，其中，所述导线还用于与驱动电路相连，所述公共电极块中位于所述驱动电路远端的公共电极块通过多根所述导线与所述驱动电路连接，所述公共电极块中剩余的位于所述驱动电路近端的公共电极块通过一根所述导线与所述驱动电路连接。
  8. 根据权利要求1或2所述的阵列基板，还包括驱动电路，其中，所述导线与所述驱动电路相连，所述公共电极块中位于所述驱动电路远端的公共电极块通过多根所述导线与所述驱动电路连接，所述公共电极块中剩余的位于所述驱动电路近端的公共电极块通过一根所述导线与所述驱动电路连接。
  9. 根据权利要求1-8任一所述的阵列基板，其中，一个所述公共电极块对应多个所述子像素单元。
  10. 根据权利要求1-9任一项所述的阵列基板，其中，所述公共电极块的形状为正方形、矩形、菱形或其它正多边形。
  11. 根据权利要求1-10任一项所述的阵列基板，其中，所述公共电极块为边长4mm-5mm的正方形电极块。
  12. 根据权利要求1-11任一项所述的阵列基板，还包括：
    设置于所述导线上的第一保护层，其中，所述公共电极层设置在所述第一保护层上；或者
    设置于所述公共电极层上的第一保护层，其中，所述导线设置于所述第一保护层上。
  13. 根据权利要求1-11任一项所述的阵列基板，还包括：
    设置在所述多条栅线上的栅极绝缘层；
    设置在所述栅极绝缘层上的有源层，其中，所述多条数据线和所述导线设置在所述有源层上；
    设置在所述多条数据线和所述导线上的第一保护层，其中，所述公共电极层设置在所述第一保护层上；
    设置在所述第一保护层和所述公共电极层上设有第二保护层；以及
    设置在所述第二保护层上的像素电极。
  14. 根据权利要求12或13所述的阵列基板，其中，所述第一保护层上设有第一过孔，所述公共电极块通过所述第一过孔与所述导线连接。
  15. 根据权利要求14所述的阵列基板，其中，同列的各所述公共电极块对应的各所述第一过孔在所述衬底基板上的投影依次错开。
  16. 一种触控面板，包括权利要求1-15中任意一项所述的阵列基板。
  17. 一种阵列基板的制作方法，包括：
    在衬底基板上形成多条栅线和多条数据线；
    在所述衬底基板上方形成公共电极层，其中，所述公共电极层包括可复用作自容电极的多个公共电极块，一个所述公共电极块连接有至少一根导线；以及
    形成呈阵列状排列的多个像素单元，每个所述像素单元包括多个由横纵 交叉设置的所述栅线和所述数据线围设成的子像素单元，且所述导线位于同列的各所述子像素单元的中部。
  18. 根据权利要求17所述的阵列基板的制作方法，其中，所述导线与所述数据线或所述栅线同层设置或不同层设置。
  19. 根据权利要求17或18所述的阵列基板的制作方法，其中，形成所述子像素单元包括：
    在所述多条栅线上形成栅极绝缘层的图形；
    在所述栅极绝缘层上形成有源层的图形，所述有源层的图形包括与待形成的源极/漏极及源极/漏极之间的沟道对应的区域和待形成的导线对应的区域；
    通过一次构图工艺在所述有源层上形成数据线、导线和源极/漏极的图形；
    在所述数据线、所述导线和所述源极/漏极上形成第一保护层，通过构图工艺在所述第一保护层上形成包括第一过孔的图形，所述公共电极块位于所述第一保护层上，所述公共电极块通过所述第一过孔与所述导线连接；
    在所述第一保护层和所述公共电极块上形成第二保护层，通过构图工艺在所述第二保护层和所述第一保护层上形成包括第二过孔的图形；
    在所述第二保护层上形成像素电极的图形，所述像素电极通过所述第二过孔与所述漏极连接。
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CN104536636A (zh) * 2015-01-27 2015-04-22 京东方科技集团股份有限公司 一种阵列基板、触控面板及阵列基板的制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109856845A (zh) * 2019-03-12 2019-06-07 武汉华星光电技术有限公司 彩膜基板、柔性液晶显示面板及制备方法
CN109856845B (zh) * 2019-03-12 2024-03-22 武汉华星光电技术有限公司 彩膜基板、柔性液晶显示面板及制备方法

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