WO2016110036A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2016110036A1
WO2016110036A1 PCT/CN2015/079126 CN2015079126W WO2016110036A1 WO 2016110036 A1 WO2016110036 A1 WO 2016110036A1 CN 2015079126 W CN2015079126 W CN 2015079126W WO 2016110036 A1 WO2016110036 A1 WO 2016110036A1
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WIPO (PCT)
Prior art keywords
layer
line
array substrate
insulating layer
electrode line
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PCT/CN2015/079126
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English (en)
French (fr)
Inventor
曹占锋
张锋
姚琪
高锦成
张斌
何晓龙
李正亮
张伟
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/895,352 priority Critical patent/US10192893B2/en
Publication of WO2016110036A1 publication Critical patent/WO2016110036A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate

Definitions

  • Embodiments of the present disclosure relate to an array substrate and a display device.
  • the narrow bezel technology mainly relies on GOA (Gate Driver on Array) technology.
  • the gate driving circuit of the thin film transistor is mainly completed by a liquid crystal panel external bonding IC (Integrated Circuit); and the GOA technology directly integrates the gate driving circuit of the thin film transistor on the array substrate, so The gate driving circuit is separately formed to avoid externally bonding the gate driving circuit to the liquid crystal panel, thereby reducing the frame of the display panel, simplifying the manufacturing process and reducing the production cost.
  • An embodiment of the present disclosure provides an array substrate including a plurality of signal lines, a plurality of connection lines, and a driving module in a peripheral area outside the display area, the connection line being used to connect the signal lines and the Driving a module to transmit a signal from the signal line to the driving module, wherein at least one of the connecting line and the at least one signal line are designed to cross and insulate each other in a first region, the at least one signal line being The second region other than the first region includes a first electrode line layer and a second electrode line layer including a first electrode line layer in the first region without including a second electrode line layer.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • FIG. 1 is a schematic structural view of an array substrate provided in the related art
  • Figure 2 is a cross-sectional view of the region M of Figure 1 taken along the line AA';
  • FIG. 3 is a schematic partial structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view of the first region N in the array substrate of FIG. 3 taken along line BB';
  • Figure 5 is a cross-sectional view of the second region O in the array substrate of Figure 3 taken along line CC';
  • FIG. 6 is a partial plan structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a partial planar structural diagram of still another array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a GOA area 1 and a display area 2, wherein the display area 2 is formed with a plurality of display units 3, and the GOA area 1 includes a plurality of clock signal lines 10, a plurality of metal connection lines 20, and a plurality of GOA unit 30.
  • Each clock signal line 10 is electrically coupled to a GOA unit 30 via a metal connection 20 for providing a clock signal to the GOA unit 30.
  • the GOA unit 30 is electrically connected to the corresponding gate line 4 of the display area 2, and outputs a scan signal to the corresponding gate line 4.
  • the clock signal line 10 is generally formed simultaneously with other layer structures of the display area of the array substrate. As shown in FIG. 2, the clock signal line 10 generally includes a scanning metal line layer 101, an insulating layer 102, and a source/drain metal line layer. 103 and passivation layer 104.
  • the inventors have found that at least the following technical problems exist in the array substrate provided by the related art: since only the passivation layer 104 exists between the source/drain metal line layer 103 and the metal connection line 20, and the thickness of the passivation layer 104 is generally thin (thickness range) for Thus, in the intersection region of the metal connection line 20 with the non-corresponding clock signal line 10, static electricity accumulation between the metal connection line 20 and the source/drain metal line layer 103 in the non-corresponding clock signal line 10 is liable to occur or A short circuit causes an error in the signal input from the metal connection line 20, which in turn causes the GOA unit to receive an erroneous clock signal, eventually resulting in a display error.
  • Embodiments of the present disclosure provide an array substrate and a display device capable of solving the problem of static accumulation or short circuit of a source/drain metal line layer of a metal connection line and a non-corresponding clock signal line.
  • An embodiment of the present disclosure provides an array substrate.
  • a plurality of signal lines 40, a plurality of connecting lines 50, and a driving module 60 are included in a peripheral area outside the display area, and each connecting line is provided.
  • the 50 is configured to connect at least one corresponding signal line 40 to the drive module 60 and transmit signals from the at least one corresponding signal line 40 to the drive module 60.
  • the corresponding signal line 40 refers to a signal line designed to be electrically connected to the one connection line 50, and the non-corresponding signal line 40 is designed to be electrically insulated from the one connection line 50.
  • Signal line for one connection line 50, the corresponding signal line 40 refers to a signal line designed to be electrically connected to the one connection line 50, and the non-corresponding signal line 40 is designed to be electrically insulated from the one connection line 50.
  • connection line 50 refers to a connection line designed to be electrically connected to the one signal line 40, and the non-corresponding connection line 50 is designed to be A signal line 40 is electrically isolated.
  • a plurality of connecting lines 50 are located above the plurality of signal lines 40.
  • An insulating layer 70 is disposed on the plurality of signal lines 40. The plurality of signal lines 40 are insulated from the plurality of connecting lines 50 through the insulating layer 70, and at least one connecting line 50 is At least one of the non-corresponding signal lines 40 intersects.
  • the signal line 40 includes only the first electrode line layer 401 and the insulating layer 70 in the first region N crossing any of the non-corresponding connecting lines 50.
  • the signal line includes a first electrode line layer 401 and a second electrode line layer 402 and an insulating layer 70 in a second region O other than the first region N.
  • the second electrode line layer 402 is located, for example, above the first electrode line layer 401.
  • the number of the signal lines 40 may be greater than the number of the connection lines 50, and may be the same as the number of the connection lines 50, which is not limited in this embodiment, as long as one connection line is satisfied. 40 is connected to at least one signal line 50.
  • the connection manner of the connection line and the driving module is not limited in the embodiment of the present disclosure, and may be determined according to actual conditions, for example.
  • the embodiment of the present disclosure does not limit the material forming the connecting line 50, as long as it can be transmitted.
  • the transmission signal may be, for example, a connection line formed by a metal wire 50.
  • the insulating layer 70 is disposed on the signal line 40.
  • the thickness of the insulating layer 70 is not particularly limited as long as reliable insulation between the connecting line and the signal line can be ensured.
  • the driving module 60 may be a gate driving circuit or other driving circuit, which is not specifically limited herein.
  • the signal line 40 may be a clock signal line, that is, used to provide a clock signal to the driving module, and may be other signal lines. The embodiment of the present disclosure does not specifically limit this, and may be determined according to actual conditions.
  • An embodiment of the present disclosure provides an array substrate in which a connection line is located above a signal line, at least one connection line intersects at least one non-corresponding signal line, and the signal line is in a non-corresponding connection.
  • the first region intersecting the line includes only the first electrode line layer and the insulating layer, and the second region except the first region includes a second electrode line layer in addition to the first electrode line layer and the insulating layer, that is,
  • the signal line does not include the second electrode line layer in the first region crossing the non-corresponding connection line, thereby avoiding the problem of static accumulation or short circuit between the connection line and the second electrode line layer; and the first electrode line layer
  • An insulating layer is disposed on the upper layer to improve the insulation between the connecting line and the signal line, thereby ensuring the reliability of signal transmission.
  • the first insulating layer 701 and the second insulating layer 702 are disposed between the first electrode line layer 401 and the connecting line 50.
  • the first insulating layer 701 and the second insulating layer 702 can form two insulating layers, which is beneficial to enhance the insulation between the signal lines and the connecting lines, thereby maximally avoiding electrostatic accumulation or short circuit between the connecting lines and the signal lines.
  • the first insulating layer 701 and the second electrode layer are sequentially disposed on the first electrode line layer 401. 402, the second insulating layer 702, such that the second insulating layer 702 can serve as an insulation to prevent signal lines from being disturbed.
  • a first insulating layer is disposed between the first electrode line layer 401 and the second electrode line layer 402. 701.
  • the signals transmitted by the first electrode line layer and the second electrode line layer may be the same or different, and the embodiment of the present disclosure does not limit this.
  • the first electrode line layer and the second electrode line layer are electrically connected to transmit the same signal, thereby increasing the signal transmission speed, and further reducing the resistance of the signal line.
  • the first insulating layer 701 may insulate the two from each other, thereby preventing signals transmitted by the two from interfering with each other; In the case where the layer 401 and the second electrode line layer 402 transmit the same signal, the first electrode line layer and the second electrode line layer may be electrically connected through the via holes.
  • the first electrode line layer 401 is electrically connected to the second electrode line layer 402, and the first electrode line layer 401 and the second electrode line layer 402 transmit the same signal, which increases the transmission speed of the signal.
  • a via hole may be disposed in the first insulating layer 701, and the first electrode line layer 401 and the second electrode line layer 402 may be electrically connected to each other through the via hole.
  • the first insulating layer 701 and the second insulating layer 702 In one example, in order to improve the insulation between the first electrode line layer and the connection line, in the first region where the signal line 40 and the non-corresponding connection line 50 intersect, the first insulating layer 701 and the second insulating layer 702 The sum of the thicknesses is greater than or equal to
  • the plurality of connecting lines 50 may be distributed in at least one connection area, and the signal line 40 includes a first electrode line layer in each connection area and does not include the second electrode line layer.
  • a plurality of connection regions may be evenly distributed on the array substrate.
  • the number of connecting lines distributed in one connection region is not limited, and may be, for example, depending on the size of the display device including the array substrate. For example, as shown in FIG. 3, the three connecting lines form a connecting area; or as shown in FIG. 6, the six connecting lines form a connecting area.
  • the signal line 40 has a width ranging from 10 to 25 ⁇ m
  • the adjacent two signal lines 40 have a pitch ranging from 10 to 25 ⁇ m
  • the connecting line 50 has a width ranging from 4 to 8 ⁇ m.
  • the width of the connecting line 50 is in the range of 4-8 ⁇ m, and the spacing between the adjacent two signal lines 40 ranges from 10 to 25 ⁇ m, as shown in FIG. 7, a part of the connecting line 50 may be located in the adjacent two. Between the signal lines 40, the space resources between the adjacent two signal lines 40 can be effectively utilized, which is advantageous for connecting the signal lines and the connection lines.
  • the signal line 40 further includes an isolation layer (not shown) between the first insulating layer and the second insulating layer in a region crossing the non-corresponding connecting line 50, and between the signal line and the connecting line.
  • the thickness of the insulating layer is further increased, thereby further improving the insulation between the signal line and the connecting line.
  • the array substrate further includes a display area, where the display area includes a plurality of gate lines and a plurality of data lines, wherein the gate lines and the data lines can acquire signals through the driving module.
  • the driver module can be a GOA circuit to provide a signal to the gate line of the display area; the driver module can also be a data line Driving the circuit to provide a signal to the data line of the display area.
  • the first electrode line layer 401 is formed simultaneously with the gate line
  • the second electrode line layer 402 is formed simultaneously with the data line.
  • the display area, the driving module and the signal line are integrated on the array substrate, and the driving module can provide a signal to the gate line or the data line to realize display; on the other hand, the first electrode line layer and the gate line are simultaneously formed,
  • the second electrode line layer is formed simultaneously with the data line, which reduces the number of patterning processes and reduces the production cost.
  • the first electrode line layer is formed at the same time as the gate line.
  • the first electrode line layer and the gate line may be processed in the same layer by a patterning process including masking, exposure, development, etching, and stripping.
  • the material is formed;
  • the second electrode line layer is formed simultaneously with the data line.
  • the second electrode line layer and the data line may be formed by the same layer of the same material through a patterning process including masking, exposure, development, etching, and stripping.
  • the display region further includes a gate insulating layer between the gate line and the data line, and a passivation layer covering the gate line and the data line; the first insulating layer 701 is formed simultaneously with the gate insulating layer, and the second insulating layer 702 is The passivation layer is formed at the same time, which can further reduce the number of patterning processes and thus reduce the production cost.
  • the display region further includes an active layer between the gate insulating layer and the data line, and the isolation layer is formed simultaneously with the active layer, for example, the isolation layer and the active layer may pass through a patterning process including masking, exposure, The processes of development, etching and stripping are formed in the same layer and the same material, which can further reduce the number of patterning processes and thus reduce the production cost.
  • the thickness of the first insulating layer 701 may be The thickness of the second insulating layer 702 can be Then, in the first region where the signal line 40 and the non-corresponding connecting line 50 intersect, the thickness of the insulating layer between the first electrode line layer 401 and the connecting line 50 is the sum of the thicknesses of the first insulating layer and the second insulating layer.
  • the insulation between the first electrode line layer 401 and the connection line 50 is greatly enhanced, thereby avoiding the problem of static accumulation and short circuit between the first electrode line layer 401 and the connection line 50.
  • the first electrode line layer 401 may be 3-5 ⁇ m wider than the second electrode line layer 402, so that the difficulty in fabrication is reduced when the second insulating layer is subsequently formed.
  • An embodiment of the present disclosure provides a display device including the array substrate of any of the above.
  • An example of the display device is a liquid crystal display device in which the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • a pixel electrode of each pixel unit of the array substrate for applying an electric field to the rotation of the liquid crystal material The degree is controlled to perform the display operation.
  • the liquid crystal display further includes a backlight that provides backlighting for the array substrate.
  • the display device is an organic electroluminescence display device in which a pixel electrode of each pixel unit of the array substrate serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • the display device has the characteristics of narrow frame and long service life, and can be any product or component having a display function such as a television, a digital camera, a mobile phone, a tablet computer or the like.
  • An array substrate comprising a plurality of signal lines, a plurality of connecting lines, and a driving module in a peripheral area outside the display area, the connecting line being used to connect the signal line and the driving module to Transmitting a signal from the signal line to the driving module, wherein at least one of the connecting lines and the at least one signal line are designed to cross and insulate each other in a first region, the at least one signal line being in addition to the first
  • the second region outside the region includes a first electrode line layer and a second electrode line layer in which the first electrode line layer is included without including the second electrode line layer.
  • connection lines are distributed in one or more connection regions.
  • connection line (10) The array substrate according to (9), wherein a part of the connection line is located between adjacent two signal lines.
  • the signal line further includes an isolation layer between the first insulating layer and the second insulating layer.
  • the array substrate according to any one of (1) to (11), wherein the array substrate further includes a plurality of gate lines and a plurality of data lines located in the display area; the first electrode lines The layer is formed of the same material as the gate line, and the second electrode line layer is formed of the same material as the data line.
  • the display region further includes a gate insulating layer between the gate line and the data line, and covering the gate line and the data line a passivation layer; the first insulating layer and the gate insulating layer are formed of the same material, and the second insulating layer and the passivation layer are formed of the same material.
  • the display region further includes an active layer between the gate insulating layer and the data line, the isolation layer being the same as the active layer
  • the layers are formed from the same material.
  • a display device comprising the array substrate according to any one of (1) to (16).

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Abstract

一种阵列基板及显示装置。该阵列基板在显示区域(2)之外的周边区域(1)内包括多条信号线(40)、多条连接线(50)以及驱动模块(60)，连接线(50)用于连接信号线(40)和驱动模块(60)，以将来自信号线(40)的信号传输至驱动模块(60)，其中，至少一条连接线(50)与至少一条信号线(40)设计为在第一区域(N)彼此交叉且绝缘，至少一条信号线(40)在除该第一区域(N)之外的第二区域(O)包括第一电极线层(401)和第二电极线层(402)而在该第一区域(N)中包括第一电极线层(401)而不包括第二电极线层(402)。该阵列基板可避免连接线(50)与第二电极线层(402)之间发生静电累积或者短路的问题。

Description

阵列基板及显示装置 技术领域
本公开实施例涉及一种阵列基板及显示装置。
背景技术
随着用户对于显示品质的不断追求，窄边框的显示装置已成为商家研究的热点。尤其是在手机行业，窄边框手机比同等尺寸的手机显示屏幕更大、质量更轻，已成为消费热点。
目前，窄边框技术主要依赖GOA(Gate Driver on Array，阵列基板行驱动)技术实现。传统技术中薄膜晶体管的栅极驱动电路主要是由液晶面板外黏接IC(Integrated Circuit，集成电路)来完成；而GOA技术是直接将薄膜晶体管的栅极驱动电路集成在阵列基板上，因此无需单独形成栅极驱动电路，避免将栅极驱动电路外黏接到液晶面板上，从而减小了显示面板的边框，同时简化了制作工艺，降低了生产成本。
发明内容
本公开的实施例提供了一种阵列基板，包括在显示区域之外的周边区域内包括多条信号线、多条连接线以及驱动模块，所述连接线用于连接所述信号线和所述驱动模块，以将来自所述信号线的信号传输至所述驱动模块，其中，至少一条所述连接线与至少一条信号线设计为在第一区域彼此交叉且绝缘，所述至少一条信号线在除该第一区域之外的第二区域包括第一电极线层和第二电极线层而在该第一区域中包括第一电极线层而不包括第二电极线层。
本公开的实施例还提供了一种显示装置，包括上述阵列基板。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本公开的一些实施例，并非对本公开的限制。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中提供的一种阵列基板的结构示意图；
图2为图1区域M沿AA′向的剖视图；
图3为本公开实施例提供的一种阵列基板的局部平面结构示意图；
图4为图3的阵列基板中的第一区域N沿BB′向的剖视图；
图5为图3的阵列基板中的第二区域O沿CC′向的剖视图；
图6为本公开实施例提供的另一种阵列基板的局部平面结构示意图；
图7为本公开实施例提供的又一种阵列基板的局部平面结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在本公开实施例的描述中，需要理解的是，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
图1和2示出了相关技术中提供的一种阵列基板的结构示意图。如图1所示，阵列基板包括GOA区域1和显示区域2，其中，显示区域2形成有多个显示单元3，GOA区域1包括多条时钟信号线10、多条金属连接线20以及多个GOA单元30。每个时钟信号线10通过一条金属连接线20与一个GOA单元30电连接，用以向该GOA单元30提供时钟信号。GOA单元30与显示区域2的对应栅线4电连接，向该对应的栅线4输出扫描信号。
如图1所示，为了使金属连接线20与对应的时钟信号线10电连接，一些金属连接线20需要跨越其他非对应时钟信号线10才能与对应的时钟信号线10电连接。而为了简化制作工艺，时钟信号线10一般与阵列基板显示区域的其他层结构同时形成，如图2所示，时钟信号线10一般包括扫描金属线 层101、绝缘层102、源漏金属线层103和钝化层104。发明人发现该相关技术提供的阵列基板中至少存在以下技术问题：由于源漏金属线层103与金属连接线20之间只有钝化层104，而钝化层104的厚度一般较薄(厚度范围为
Figure PCTCN2015079126-appb-000001
)，这样在金属连接线20在与非对应时钟信号线10的交叉区域中，容易发生该金属连接线20与该非对应时钟信号线10中的源漏金属线层103之间的静电累积或者短路，从而导致金属连接线20输入的信号发生错误，进而导致GOA单元接收错误的时钟信号，最终导致显示错误。
本公开的实施例提供一种阵列基板及显示装置，能够解决金属连接线与非对应时钟信号线的源漏金属线层发生静电累积或者短路的问题。
本公开实施例提供了一种阵列基板，如图3、图4所示，在显示区域之外的周边区域内包括多条信号线40、多条连接线50以及驱动模块60，每一条连接线50构造为用于连接至少一条对应的信号线40至驱动模块60，并将来自该至少一条对应的信号线40的信号传输至驱动模块60。这里，对于一条连接线50而言，对应信号线40是指设计为与该一条连接线50电性连接的信号线，而非对应信号线40是指设计为与该一条连接线50电性绝缘的信号线。类似地，对于一条信号线40而言，与之对应的连接线50是指设计为与该一条信号线40电性连接的连接线，而与之非对应的连接线50是指设计为与该一条信号线40电性隔离的连接线。多条连接线50位于多条信号线40的上方，多条信号线40之上设置有绝缘层70，多条信号线40通过绝缘层70与多条连接线50绝缘，至少一条连接线50与至少一条与之非对应信号线40交叉。
如图4所示，信号线40在与任一非对应连接线50交叉的第一区域N中，仅包括第一电极线层401和绝缘层70。如图5所示，信号线在除该第一区域N之外的第二区域O包括第一电极线层401和第二电极线层402和绝缘层70。该第二电极线层402例如位于该第一电极线层401上方。
在本公开实施例提供的阵列基板中，信号线40的数量可以是大于连接线50的数量，也可以与连接线50的数量相同，本公开实施例对此不做限定，只要满足一条连接线40与至少一条信号线50对应相连即可。同时，本公开实施例对于连接线和驱动模块的连接方式不作限定，例如可以根据实际情况而定。另外，本公开实施例对于形成连接线50的材料不做限定，只要可以传 输电信号即可，例如连接线50由金属形成的连接线。
在本公开实施例提供的阵列基板中，信号线40之上设置有绝缘层70，这里对于绝缘层70的厚度不作特别限定，只要能够保证连接线与信号线之间的可靠绝缘即可。
在本公开实施例提供的阵列基板中，驱动模块60可以是栅极驱动电路，也可以是其他驱动电路，这里不作具体限定。另外，信号线40可以是时钟信号线，即用于向驱动模块提供时钟信号，也可以是其他信号线，本公开实施例对此不作具体限定，可以根据实际情况而定。
本公开的实施例提供了一种阵列基板，该阵列基板的周边区域中，连接线位于信号线的上方，至少一条连接线与至少一条非对应的信号线交叉，信号线在与非对应的连接线交叉的第一区域仅包括第一电极线层和绝缘层，而在除该第一区域之外的第二区域除了包括第一电极线层和绝缘层还包括第二电极线层，也就是，信号线在与非对应连接线交叉的第一区域不包括第二电极线层，这样避免了连接线与第二电极线层之间发生静电累积或者短路的问题；同时第一电极线层之上设置有绝缘层，从而提高了连接线与信号线之间的绝缘性，保证了信号传输的可靠性。
进一步的，如图4所示，在信号线与非对应连接线交叉的第一区域N中，第一电极线层401与连接线50之间设置有第一绝缘层701和第二绝缘层702，这样第一绝缘层701和第二绝缘层702可以形成两层绝缘层，有利于增强信号线与连接线之间的绝缘性，从而最大程度的避免连接线与信号线发生静电累积或者短路的问题；如图5所示，在信号线的除上述第一区域N之外的第二区域O中，在第一电极线层401之上依次设置有第一绝缘层701、第二电极线层402、第二绝缘层702，这样第二绝缘层702可以起到绝缘作用，从而防止信号线受到干扰。
进一步的，如图5所示，在信号线的除上述第一区域N之外的第二区域O中，在第一电极线层401与第二电极线层402之间设置有第一绝缘层701。
需要说明的是，第一电极线层和第二电极线层传输的信号可以相同，也可以不同，本公开实施例对此不作限定。在一个示例中，第一电极线层和第二电极线层电连接，从而传输同一信号，进而提高信号的传输速度，还可以进一步降低信号线的电阻。
在第一电极线层401与第二电极线层402传输不同信号的情况下，第一绝缘层701可以使得两者之间相互绝缘，从而防止两者传输的信号互相干扰；在第一电极线层401与第二电极线层402传输相同信号的情况下，第一电极线层与第二电极线层可以通过过孔电连接。
在一个示例中，第一电极线层401与第二电极线层402电连接，则第一电极线层401与第二电极线层402传输同一信号，这样提高了信号的传输速度。例如，第一绝缘层701中可以设置有过孔，第一电极线层401与第二电极线层402可以通过该过孔彼此电连接。
在一个示例中，为了提高第一电极线层与连接线之间的绝缘性，在信号线40与非对应连接线50交叉的第一区域中，第一绝缘层701和第二绝缘层702的厚度之和大于或等于
Figure PCTCN2015079126-appb-000002
可选的，为了降低制作难度，简化工艺，多条连接线50可以分布在至少一个连接区域，信号线40在每一连接区域包括第一电极线层而不包含第二电极线层。例如，多个连接区域可以均匀分布在阵列基板上。这里对于分布在一个连接区域内的连接线的数量不作限定，例如可以根据包括该阵列基板的显示器件的尺寸而定。示例的，可以是如图3所示，三条连接线形成一个连接区域；也可以是如图6所示，六条连接线形成一个连接区域。
可选的，为了降低成本，节约空间，信号线40的宽度范围为10-25μm，相邻的两条信号线40的间距范围为10-25μm，连接线50的宽度范围为4-8μm。
进一步的，由于连接线50的宽度范围为4-8μm，相邻的两条信号线40的间距范围为10-25μm，则参考图7所示，连接线50的一部分可以位于相邻的两条信号线40之间，这样可以有效利用相邻两条信号线40之间的空间资源，有利于连接信号线与连接线。
可选的，信号线40在与非对应连接线50交叉的区域还包括位于第一绝缘层和第二绝缘层之间的隔离层(图中未示出)，则信号线与连接线之间的绝缘层厚度进一步增加，从而进一步提高了信号线与连接线之间的绝缘性。
可选的，阵列基板还包括显示区域，显示区域包括多条栅线和多条数据线，其中，栅线和数据线可以通过驱动模块获取信号。例如，驱动模块可以是GOA电路，从而向显示区域的栅线提供信号；驱动模块还可以是数据线 驱动电路，从而向显示区域的数据线提供信号。在一个示例中，第一电极线层401与栅线同时形成，第二电极线层402与数据线同时形成。这样，一方面将显示区域、驱动模块与信号线集成在阵列基板上，驱动模块可以向栅线或者数据线提供信号，进而实现显示；另一方面，第一电极线层与栅线同时形成，第二电极线层与数据线同时形成，则减少了构图工艺次数，降低了生产成本。这里需要说明的是，第一电极线层与栅线同时形成，例如可以是指第一电极线层与栅线通过一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺同层同材料形成；第二电极线层与数据线同时形成，例如可以是指第二电极线层与数据线通过一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺同层同材料形成。
进一步的，显示区域还包括位于栅线和数据线之间的栅绝缘层，以及覆盖栅线和数据线的钝化层；第一绝缘层701与栅绝缘层同时形成，第二绝缘层702与钝化层同时形成，这样可以更进一步减少构图工艺次数，从而降低生产成本。
更进一步的，显示区域还包括位于栅绝缘层和数据线之间的有源层，隔离层与有源层同时形成，例如可以是隔离层与有源层通过一次构图工艺包括掩膜、曝光、显影、刻蚀和剥离等工艺同层同材料形成，这样可以更进一步减少构图工艺次数，从而降低生产成本。
在一个示例中，第一绝缘层701的厚度可以为
Figure PCTCN2015079126-appb-000003
第二绝缘层702的厚度可以为
Figure PCTCN2015079126-appb-000004
则在信号线40与非对应连接线50交叉的第一区域中，第一电极线层401与连接线50之间的绝缘层厚度为第一绝缘层和第二绝缘层的厚度之和即为
Figure PCTCN2015079126-appb-000005
这样，极大增强了第一电极线层401与连接线50之间的绝缘性，从而避免了第一电极线层401与连接线50之间发生静电累积和短路的问题。
例如，第一电极线层401可以比第二电极线层402宽3-5μm，这样后续形成第二绝缘层时制作难度降低。
本公开实施例提供了一种显示装置，包括上述任一项的阵列基板。该显示装置的一个示例为液晶显示装置，其中，所述阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。所述阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的 程度进行控制从而进行显示操作。在一些示例中，该液晶显示器还包括为阵列基板提供背光的背光源。该显示装置的另一个示例为有机电致发光显示装置，其中，该阵列基板的每个像素单元的像素电极作为阳极或阴极用于驱动有机发光材料发光以进行显示操作。该显示装置具有窄边框、使用寿命长的特点，可以是电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
根据上述描述，根据本公开的实施例至少可以提供以下结构和方法：
(1)一种阵列基板，包括在显示区域之外的周边区域内包括多条信号线、多条连接线以及驱动模块，所述连接线用于连接所述信号线和所述驱动模块，以将来自所述信号线的信号传输至所述驱动模块，其中，至少一条所述连接线与至少一条信号线设计为在第一区域彼此交叉且绝缘，所述至少一条信号线在除该第一区域之外的第二区域包括第一电极线层和第二电极线层而在该第一区域中包括第一电极线层而不包括第二电极线层。
(2)根据(1)所述的阵列基板，其中，在该第二区域中，所述第一电极线层与所述连接线之间设置有第一绝缘层、第二绝缘层、以及位于第一绝缘层与第二绝缘层之间的第二电极线层；在该第一区域中，所述第一电极线层与所述连接线之间设置有所述第一绝缘层和所述第二绝缘层。
(3)根据(2)所述的阵列基板，其中，在该第二区域中，所述第一绝缘层设置在所述第一电极线层与所述第二电极线层之间。
(4)、根据(2)或(3)所述的阵列基板，其中，所述第一绝缘层和所述第二绝缘层的厚度之和大于或等于
Figure PCTCN2015079126-appb-000006
(5)根据(3)所述的阵列基板，其中，所述第一电极线层与所述第二电极线层电连接。
(6)根据(5)所述的阵列基板，其中，所述第一绝缘层中设置有过孔，所述第一电极线层与所述第二电极线层通过所述第一绝缘层的过孔电连接。
(7)根据(1)至(6)中任一项所述的阵列基板，其中，多条连接线分布在一个或多个连接区域中。
(8)根据(7)所述的阵列基板，其中，多个所述连接区域是均匀分布的。
(9)根据(1)至(8)中任一项所述的阵列基板，其中，所述信号线的 宽度范围为10-25μm，相邻的两条信号线的间距范围为10-25μm，所述连接线的宽度范围为4-8μm。
(10)根据(9)所述的阵列基板，其中，所述连接线的一部分位于相邻的两条信号线之间。
(11)根据(2)所述的阵列基板，其中，在第一区域中，所述信号线还包括位于所述第一绝缘层和所述第二绝缘层之间的隔离层。
(12)根据(1)至(11)中任一项所述的阵列基板，其中，所述阵列基板还包括位于显示区域内的多条栅线和多条数据线；所述第一电极线层与所述栅线同层同材料形成，所述第二电极线层与所述数据线同层同材料形成。
(13)根据(12)所述的阵列基板，其中，所述显示区域还包括位于所述栅线和所述数据线之间的栅绝缘层，以及覆盖所述栅线和所述数据线的钝化层；所述第一绝缘层与所述栅绝缘层同层同材料形成，所述第二绝缘层与所述钝化层同层同材料形成。
(14)根据(13)所述的阵列基板，其中，所述显示区域还包括位于所述栅绝缘层和所述数据线之间的有源层，所述隔离层与所述有源层同层同材料形成。
(15)根据(13)所述的阵列基板，其中，所述第一绝缘层的厚度为
Figure PCTCN2015079126-appb-000007
所述第二绝缘层的厚度为
Figure PCTCN2015079126-appb-000008
(16)根据(12)所述的阵列基板，其中，所述第一电极线层比所述第二电极线层宽3-5μm。
(17)一种显示装置，包括(1)至(16)中任一项所述的阵列基板。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本申请要求于2015年1月9日递交的中国专利申请第201510012613.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种阵列基板，在显示区域之外的周边区域内包括多条信号线、多条连接线以及驱动模块，所述连接线用于连接所述信号线和所述驱动模块，以将来自所述信号线的信号传输至所述驱动模块，其中，至少一条所述连接线与至少一条信号线设计为在第一区域彼此交叉且绝缘，所述至少一条信号线在除该第一区域之外的第二区域包括第一电极线层和第二电极线层而在该第一区域中包括第一电极线层而不包括第二电极线层。
  2. 根据权利要求1所述的阵列基板，其中，在该第二区域中，所述第一电极线层与所述连接线之间设置有第一绝缘层、第二绝缘层、以及位于第一绝缘层与第二绝缘层之间的第二电极线层；在该第一区域中，所述第一电极线层与所述连接线之间设置有所述第一绝缘层和所述第二绝缘层。
  3. 根据权利要求2所述的阵列基板，其中，在该第二区域中，所述第一绝缘层设置在所述第一电极线层与所述第二电极线层之间。
  4. 根据权利要求2或3所述的阵列基板，其中，所述第一绝缘层和所述第二绝缘层的厚度之和大于或等于
    Figure PCTCN2015079126-appb-100001
  5. 根据权利要求3所述的阵列基板，其中，所述第一电极线层与所述第二电极线层电连接。
  6. 根据权利要求5所述的阵列基板，其中，所述第一绝缘层中设置有过孔，所述第一电极线层与所述第二电极线层通过所述第一绝缘层的过孔电连接。
  7. 根据权利要求1至6中任一项所述的阵列基板，其中，多条连接线分布在一个或多个连接区域中。
  8. 根据权利要求7所述的阵列基板，其中，多个所述连接区域是均匀分布的。
  9. 根据权利要求1至8中任一项所述的阵列基板，其中，所述信号线的宽度范围为10-25μm，相邻的两条信号线的间距范围为10-25μm，所述连接线的宽度范围为4-8μm。
  10. 根据权利要求9所述的阵列基板，其中，所述连接线的一部分位于相邻的两条信号线之间。
  11. 根据权利要求2所述的阵列基板，其中，在第一区域中，所述信号线还包括位于所述第一绝缘层和所述第二绝缘层之间的隔离层。
  12. 根据权利要求1至11中任一项所述的阵列基板，其中，所述阵列基板还包括位于显示区域内的多条栅线和多条数据线；所述第一电极线层与所述栅线同层同材料形成，所述第二电极线层与所述数据线同层同材料形成。
  13. 根据权利要求12所述的阵列基板，其中，所述显示区域还包括位于所述栅线和所述数据线之间的栅绝缘层，以及覆盖所述栅线和所述数据线的钝化层；所述第一绝缘层与所述栅绝缘层同层同材料形成，所述第二绝缘层与所述钝化层同层同材料形成。
  14. 根据权利要求13所述的阵列基板，其中，所述显示区域还包括位于所述栅绝缘层和所述数据线之间的有源层，所述隔离层与所述有源层同层同材料形成。
  15. 根据权利要求13所述的阵列基板，其中，所述第一绝缘层的厚度为
    Figure PCTCN2015079126-appb-100002
    所述第二绝缘层的厚度为
    Figure PCTCN2015079126-appb-100003
  16. 根据权利要求12所述的阵列基板，其中，所述第一电极线层比所述第二电极线层宽3-5μm。
  17. 一种显示装置，包括权利要求1至16中任一项所述的阵列基板。
PCT/CN2015/079126 2015-01-09 2015-05-15 阵列基板及显示装置 WO2016110036A1 (zh)

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