WO2017173779A1 - 阵列基板和显示装置 - Google Patents

阵列基板和显示装置 Download PDF

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Publication number
WO2017173779A1
WO2017173779A1 PCT/CN2016/098430 CN2016098430W WO2017173779A1 WO 2017173779 A1 WO2017173779 A1 WO 2017173779A1 CN 2016098430 W CN2016098430 W CN 2016098430W WO 2017173779 A1 WO2017173779 A1 WO 2017173779A1
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Prior art keywords
line
type transistor
electrostatic protection
gate
array substrate
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PCT/CN2016/098430
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English (en)
French (fr)
Inventor
程鸿飞
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/535,457 priority Critical patent/US10269788B2/en
Priority to TW105142022A priority patent/TWI622973B/zh
Publication of WO2017173779A1 publication Critical patent/WO2017173779A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • the display device generally includes an array substrate and an opposite substrate, wherein the array substrate has a complicated structure and is an important component of the display device.
  • the array substrate generally includes a base substrate and data lines, gate lines, and common electrode lines formed on the base substrate. During the manufacturing process or during use of the array substrate, a higher voltage static electricity may be generated on the gate line, which may damage the gate line.
  • the prior art provides an array substrate including a base substrate and a gate line disposed on the base substrate, an electrostatic protection unit, and an electrostatic protection line, and the electrostatic protection unit is respectively connected to the gate line and the electrostatic protection line.
  • the electrostatic protection unit usually includes an element such as an N-type transistor, and is capable of directing static electricity to the electrostatic protection wire for release when static electricity is generated on the gate line.
  • the inventors have found that the prior art has at least the problem that parasitic capacitance exists in a transistor in an electrostatic protection unit connected to a gate line, thereby affecting the normal operation of the gate line.
  • Embodiments of the present disclosure provide an array substrate and display device that are capable of at least partially alleviating or eliminating problems in the prior art.
  • an array substrate includes a substrate substrate.
  • the base substrate includes a pixel region and a peripheral region surrounding the pixel region, wherein a gate line is disposed in the pixel region and the peripheral region, and an electrostatic discharge branch, a first electrostatic protection unit, and an electrostatic protection line are disposed in the peripheral region.
  • the electrostatic discharge branch is connected in parallel with the preset segment of the gate line, wherein the predetermined segment of the gate line is located in the peripheral region.
  • the first electrostatic protection unit is respectively connected to the electrostatic discharge branch and the electrostatic protection line.
  • the first electrostatic protection unit includes a first N-type transistor and a second N-type transistor.
  • the gate and source of the first N-type transistor are both connected to the electrostatic discharge branch.
  • the drain of the first N-type transistor is connected to the electrostatic protection line.
  • the gate and the source of the second N-type transistor are both connected to the electrostatic protection line, and the drain of the second N-type transistor is connected to the electrostatic discharge branch.
  • the base substrate in the peripheral region, is provided with a first pattern including a gate of the first N-type transistor, a gate of the second N-type transistor, a gate line, and an electrostatic discharge branch.
  • the base substrate provided with the first pattern is further provided with a source and a drain including a first N-type transistor, a source and a drain of the second N-type transistor, and an electrostatic protection line The second pattern.
  • the base substrate provided with the second pattern is further provided with the first electrode and the second electrode.
  • the first electrode is respectively connected to the source of the first N-type transistor and the electrostatic discharge branch through two via holes
  • the second electrode is respectively connected to the gate of the second N-type transistor and the electrostatic protection line through the two via holes.
  • the first electrostatic protection unit is further connected to a portion of the gate line other than the preset segment of the gate line.
  • the first electrostatic protection unit includes a first N-type transistor and a second N-type transistor.
  • a gate of the first N-type transistor is connected to the electrostatic discharge branch, a drain of the first N-type transistor is connected to the electrostatic protection line, and a source and a gate line of the first N-type transistor are separated from the gate line. Part of the connection outside the preset segment.
  • the gate and the source of the second N-type transistor are both connected to the electrostatic protection line, and the drain of the second N-type transistor is connected to a portion of the gate line other than the predetermined segment of the gate line.
  • the electrostatic protection lines are arranged to vertically intersect the pre-set segments of the electrostatic discharge branches and the gate lines, respectively.
  • the peripheral region is further provided with a common electrode line and a second electrostatic protection unit.
  • the second electrostatic protection unit is connected to the electrostatic protection line and the common electrode line, respectively.
  • the common electrode lines are arranged to vertically intersect the pre-set segments of the electrostatic discharge branch and the gate line, respectively.
  • the second electrostatic protection unit includes a third N-type transistor and a fourth N-type transistor.
  • the gate and the source of the third N-type transistor are both connected to the electrostatic protection line, and the third N The drain of the transistor is connected to the common electrode line.
  • the gate and the source of the fourth N-type transistor are both connected to the common electrode line, and the drain of the fourth N-type transistor is connected to the electrostatic protection line.
  • the electrostatic discharge branch is connected to the predetermined segment of the gate line by a wire.
  • the orthographic projection of the wire on the substrate substrate is between the orthographic projection of the electrostatic protection line on the substrate substrate and the orthographic projection of the common electrode line on the substrate substrate.
  • the electrostatic discharge branch is connected to the predetermined segment of the gate line by a wire.
  • the electrostatic protection line is a common electrode line.
  • the peripheral region is further provided with a common electrode line, and the common electrode line is connected to the electrostatic protection wire by a wire.
  • a display device includes any of the array substrates provided above.
  • the prior art can be solved by connecting a preset segment of the gate line in parallel with the electrostatic discharge branch and connecting the first electrostatic protection unit to the electrostatic discharge branch.
  • the gate line works normally, the gate line signal is less affected by the electrostatic protection unit, so the gate line signal can be transmitted on the preset segment of the gate line with less impedance; and when static electricity is generated on the gate line, the static protection The unit is turned on, and thus static electricity flows from the electrostatic discharge branch to the electrostatic protection line for release.
  • FIG. 1 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic circuit diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a circuit wiring structure of an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional view along the line m1-m2 in the array substrate shown in FIG. 3;
  • Figure 5 is a schematic cross-sectional view along the line m3-m4 in the array substrate shown in Figure 3;
  • FIG. 6 is a schematic circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic circuit diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure.
  • the array substrate may include a base substrate 11.
  • the base substrate 11 includes a pixel region (not shown in FIG. 1) and a peripheral region Z surrounding the pixel region, wherein the pixel region and the peripheral region Z are provided with the gate line 12, and the peripheral region Z is provided with the electrostatic discharge branch 13, An electrostatic protection unit 14 and an electrostatic protection line 15.
  • the electrostatic discharge branch 13 is connected in parallel with the predetermined segment y of the gate line 12, and the predetermined segment y of the gate line is located in the peripheral region Z.
  • the first electrostatic protection unit 14 is connected to the electrostatic discharge branch 13 and the electrostatic protection line 15, respectively.
  • the gate line 12 extends into a pixel region (not shown in FIG. 1).
  • the gate line can be solved by connecting the preset segment of the gate line in parallel with the electrostatic discharge branch and connecting the first electrostatic protection unit to the electrostatic discharge branch.
  • the gate line signal is less affected by the electrostatic protection unit, so the gate line signal can be transmitted on the preset segment of the gate line with less impedance; and when static electricity is generated on the gate line, the static electricity The protection unit is turned on, so that static electricity flows from the electrostatic discharge branch to the electrostatic protection line for release.
  • FIG. 2 a circuit structural diagram of another array substrate provided by an embodiment of the present disclosure is shown.
  • the first electrostatic protection unit 14 includes a first N-type transistor T1 and a second N-type transistor T2.
  • the gate g1 and the source s1 of the first N-type transistor T1 are both connected to the electrostatic discharge branch 13, and the drain d1 is connected to the electrostatic protection line 15.
  • the gate g2 and the source s2 of the second N-type transistor T2 are both connected to the electrostatic protection line 15, and the drain d2 is connected to the electrostatic discharge branch 13.
  • the first N-type transistor T1 When static electricity is generated on the gate line 12, the first N-type transistor T1 is turned on, and thus static electricity on the gate line 12 passes through the electrostatic discharge branch 13 through the source s1 of the first N-type transistor T1, and the first N-type transistor T1 The drain d1 flows to the electrostatic protection line 15.
  • the second N-type transistor T2 When the static electricity flows onto the electrostatic protection line 15, the second N-type transistor T2 is turned on, and thus the static electricity on the electrostatic protection line 15 passes through the source s2 of the second N-type transistor T2 and the drain d2 of the second N-type transistor T2. Flows to the electrostatic discharge branch 13.
  • the source s1 of the first transistor T1 and the drain d2 of the second transistor T2 may be connected to the electrostatic discharge branch 13 or to the electrostatic discharge branch 13, respectively.
  • FIG. 3 is a schematic diagram of a circuit wiring structure of an array substrate according to an embodiment of the present disclosure.
  • the base substrate 11 is provided with a gate g1 including a first N-type transistor T1, a gate g2 of a second N-type transistor T2, a gate line 12, and an electrostatic discharge branch 13 The first pattern.
  • the base substrate 11 provided with the first pattern is further provided with a source s1 and a drain d1 of the first N-type transistor T1, a source s2 and a drain d2 of the second N-type transistor T2, and The second pattern of the electrostatic protection wire 15.
  • the base substrate 11 provided with the second pattern is further provided with a first electrode j1 and a second electrode j2, wherein the first electrode j1 passes through the two via holes k1 and the source of the first N-type transistor T1, respectively
  • the pole s1 is connected to the electrostatic discharge branch 13
  • the second electrode j2 is connected to the gate g2 of the second N-type transistor T2 and the electrostatic protection line 15 through the two vias k2, respectively.
  • the material of the first electrode j1 and the second electrode j2 may include Indium Tin Oxides (abbreviation: ITO).
  • FIG. 4 is a schematic cross-sectional view of the circuit wiring structure diagram of the array substrate shown in FIG. 3 taken along the line m1-m2, wherein k1 indicates a via, j1 indicates a first electrode, and 13 indicates electrostatic discharge.
  • the branch, d2 indicates the drain of the second N-type transistor T2, 11 indicates the base substrate, 32 indicates the gate insulating layer, and 31 indicates the passivation layer.
  • FIG. 5 is a schematic cross-sectional view of the circuit wiring structure diagram of the array substrate shown in FIG. 3 taken along the line m3-m4, wherein g1 indicates the gate of the first N-type transistor T1, and g2 indicates the gate of the second N-type transistor T2, s1 Indicates the source of the first N-type transistor T1, d1 indicates the drain of the first N-type transistor T1, b1 indicates the active layer of the first N-type transistor T1, s2 indicates the source of the second N-type transistor T2, and d2 indicates The drain of the second N-type transistor T2, b2 indicates the active layer of the second N-type transistor T2, 11 indicates the substrate substrate, 31 indicates the passivation layer, and 32 indicates the gate insulating layer.
  • FIG. 6 is a schematic diagram of a circuit structure provided by an embodiment of the present disclosure.
  • the first electrostatic protection unit 14 is also connected to a portion of the gate line 12 other than the predetermined segment y of the gate line, and the first electrostatic protection unit 14 includes the first N-type transistor. T1 and a second N-type transistor T2.
  • the gate g1 of the first N-type transistor T1 is connected to the electrostatic discharge branch 13
  • the drain d1 is connected to the electrostatic protection line 15, and the predetermined segment of the source s1 and the gate line 12 except the gate line Partial connections other than y.
  • the gate g2 and the source s2 of the second N-type transistor T2 are both connected to the electrostatic protection line 15, and the drain d2 and the portion of the gate line 12 other than the predetermined segment y of the gate line 12 connection.
  • the source s1 of the first transistor T1 and the drain d2 of the second transistor T2 may be connected and then connected to a portion of the gate line 12 other than the preset segment y of the gate line, or respectively, and the gate line A portion of 12 other than the preset segment y of the gate line is connected.
  • the electrostatic protection lines 15 are arranged to vertically intersect the electrostatic discharge branch 13 and the predetermined segment y of the gate line 12, respectively.
  • the vertically intersecting arrangement can reduce the overlapping area of the electrostatic protection lines 15 with the preset sections y of the electrostatic discharge branches 13 and the gate lines 12, thereby reducing the preset of the electrostatic protection lines 15 and the electrostatic discharge branches 13 and the gate lines 12, respectively.
  • the coupling capacitance of segment y reduces the effect of the coupling capacitance on the circuit and improves the performance of the circuit.
  • the electrostatic discharge branch 13 and the predetermined segment y of the gate line 12 may be connected by wires (not shown).
  • the wire can reduce the resistance of the gate line signal when it is transmitted on the preset section y of the electrostatic discharge branch 13 and the gate line 12, thereby improving the performance of the circuit.
  • the electrostatic protection lines 15 in FIGS. 1, 2, 3, and 6 Can be a common electrode line.
  • FIG. 7 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure, wherein the peripheral region Z is further provided with a common electrode line 16 and a second electrostatic protection unit 17.
  • the second electrostatic protection unit 17 is connected to the electrostatic protection line 15 and the common electrode line 16, respectively.
  • FIG. 7 For the meanings of other marks in FIG. 7, reference may be made to FIG. 2, and details are not described herein again.
  • the static electricity flowing into the electrostatic protection line 15 can flow into the common electrode line 16 through the second electrostatic protection unit 17, and is released by the common electrode line 16.
  • FIG. 8 is a block diagram showing the circuit configuration of a second electrostatic protection unit 17 in the circuit configuration diagram shown in FIG.
  • the second electrostatic protection unit 17 includes a third N-type transistor T3 and a fourth N-type transistor T4.
  • the gate g3 and the source s3 of the third N-type transistor T3 are both connected to the electrostatic protection line 15, and the drain d3 is connected to the common electrode line 16.
  • the gate g4 and the source s4 of the fourth N-type transistor T4 are both connected to the common electrode line 16, and the drain d4 is connected to the electrostatic protection line 15.
  • the drain d4 is connected to the electrostatic protection line 15.
  • the common electrode line 16 and the electrostatic protection line 15 may also be directly connected without providing the second electrostatic protection unit 17. As shown in FIG. 9, the peripheral region Z is also provided with a common electrode line 16. The common electrode line 16 and the electrostatic protection line 15 are connected by a wire 19. For the meanings of other marks in FIG. 9, reference may be made to FIG. 7, and details are not described herein again.
  • FIG. 10 is a schematic diagram of a circuit structure of an array substrate according to an embodiment of the present disclosure.
  • the electrostatic discharge branch 13 and the predetermined segment y of the gate line 12 are connected by a wire 18, and the orthographic projection of the wire 18 on the base substrate 11 is located on the base substrate 11 of the electrostatic protection wire 15.
  • Projection and common electrode lines 16 are between the orthographic projections on the substrate substrate 11.
  • the electrostatic discharge branch 13 intersects the electrostatic protection line 15 and the common electrode line 16, respectively, and the predetermined segment y of the gate line 12 intersects the electrostatic protection line 15 and the common electrode line 16, respectively.
  • Connecting the wire 18 between the electrostatic discharge branch 13 and the predetermined segment y of the gate line 12 can reduce the resistance of the gate line signal when it is transmitted on the preset section y of the electrostatic discharge branch 13 and the gate line, thereby further enhancing the array substrate The performance of the circuit structure.
  • the specific structure of the first electrostatic protection unit 14 in FIG. 10 can be referred to FIG. 2 or FIG. 6.
  • the specific structure of the second electrostatic protection unit 17 can be referred to FIG. 8, and details are not described herein again.
  • the common electrode lines 16 are arranged to vertically intersect the electrostatic discharge branch 13 and the preset segment y of the gate line 12, respectively.
  • the vertical cross arrangement can reduce the predetermined segment y of the common electrode line 16 and the electrostatic discharge branch 13 and the gate line 12, respectively.
  • the overlapping area reduces the coupling capacitance of the common electrode line 16 with the predetermined period y of the electrostatic discharge branch 13 and the gate line 12, respectively, which in turn reduces the influence of the coupling capacitance on the circuit and improves the performance of the circuit.
  • electrostatic protection lines 15 on the respective array substrates may be electrostatic protection lines of a plurality of gate lines on the array substrate.
  • the gate line in parallel with the electrostatic discharge branch and connecting the first electrostatic protection unit thereto, it can be solved in the prior art that when the gate line is in normal operation, There is a problem that parasitic capacitance exists in the transistor in the electrostatic protection unit to affect the normal operation of the gate line.
  • the gate line signal is less affected by the electrostatic protection unit, so the gate line signal can be transmitted on the preset segment of the gate line with less impedance; and when static electricity is generated on the gate line, the static protection The unit is turned on, and thus static electricity flows from the electrostatic discharge branch to the electrostatic protection line for release.
  • the embodiment of the present disclosure further provides a display device, which may include any of the array substrates shown in FIGS. 1 to 10.

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Abstract

一种阵列基板和显示装置。阵列基板包括衬底基板（11），衬底基板（11）包括像素区域和围绕像素区域的周边区域（Z），其中像素区域和周边区域（Z）设置有栅线（12），并且周边区域（Z）设置有静电释放支路（13）、第一静电保护单元（14）和静电保护线（15），静电释放支路（13）与栅线（12）的预设段并联，并且栅线（12）的预设段位于周边区域（Z），第一静电保护单元（14）分别与静电释放支路（13）和静电保护线（15）连接。

Description

阵列基板和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板和显示装置。
背景技术
显示装置通常包括阵列基板和对向基板，其中，阵列基板的结构复杂，是显示装置的重要组成部分。阵列基板通常包括衬底基板和形成于衬底基板上的数据线、栅线和公共电极线。在阵列基板的制造过程或使用过程中，可能会在栅线上产生电压较高的静电，该静电可能会损坏栅线。
现有技术提供了一种阵列基板，该阵列基板包括衬底基板以及设置在衬底基板上的栅线、静电保护单元和静电保护线，并且静电保护单元分别与栅线和静电保护线连接。静电保护单元通常包括N型晶体管等元件，并且能够在栅线上产生静电时，将静电导向静电保护线以进行释放。
然而，本发明人发现现有技术至少存在以下问题：在与栅线连接的静电保护单元中的晶体管中存在寄生电容，从而对栅线的正常工作产生了影响。
发明内容
本公开实施例提供了一种阵列基板和显示装置，其能够至少部分地缓解或消除现有技术中的问题。
根据本公开的一个方面，提供了一种阵列基板。该阵列基板包括衬底基板。衬底基板包括像素区域和围绕像素区域的周边区域，其中在像素区域和周边区域中设置有栅线，并且在周边区域中设置有静电释放支路、第一静电保护单元和静电保护线。
静电释放支路与栅线的预设段并联，其中栅线的预设段位于周边区域。
第一静电保护单元分别与静电释放支路和静电保护线连接。
根据一些实施例，第一静电保护单元包括第一N型晶体管和第二N型晶体管。第一N型晶体管的栅极和源极均与静电释放支路连接， 并且第一N型晶体管的漏极与静电保护线连接。第二N型晶体管的栅极和源极均与静电保护线连接，并且第二N型晶体管的漏极与静电释放支路连接。
根据一些实施例，在周边区域中，衬底基板设置有包括第一N型晶体管的栅极、第二N型晶体管的栅极、栅线和静电释放支路的第一图案。
根据一些实施例，在周边区域中，设置有第一图案的衬底基板还设置有包括第一N型晶体管的源极和漏极、第二N型晶体管的源极和漏极以及静电保护线的第二图案。
根据一些实施例，在周边区域中，设置有第二图案的衬底基板还设置有第一电极和第二电极。第一电极通过两个过孔分别与第一N型晶体管的源极和静电释放支路连接，并且第二电极通过两个过孔分别与第二N型晶体管的栅极和静电保护线连接。
根据一些实施例，在周边区域中，第一静电保护单元还与栅线的除栅线的预设段之外的部分连接。
根据一些实施例，第一静电保护单元包括第一N型晶体管和第二N型晶体管。
在周边区域中，第一N型晶体管的栅极与静电释放支路连接，第一N型晶体管的漏极与静电保护线连接，并且第一N型晶体管的源极与栅线的除栅线的预设段之外的部分连接。
在周边区域中，第二N型晶体管的栅极和源极均与静电保护线连接，并且第二N型晶体管的漏极与栅线的除栅线的预设段之外的部分连接。
根据一些实施例，在周边区域中，静电保护线被布置成分别与静电释放支路和栅线的预设段垂直交叉。
根据一些实施例，周边区域还设置有公共电极线和第二静电保护单元。第二静电保护单元分别与静电保护线和公共电极线连接。
根据一些实施例，在周边区域中，公共电极线被布置成分别与静电释放支路和栅线的预设段垂直交叉。
根据一些实施例，第二静电保护单元包括第三N型晶体管和第四N型晶体管。
第三N型晶体管的栅极和源极均与静电保护线连接，并且第三N 型晶体管的漏极与公共电极线连接。
第四N型晶体管的栅极和源极均与公共电极线连接，并且第四N型晶体管的漏极与静电保护线连接。
根据一些实施例，静电释放支路与栅线的预设段通过导线连接。导线在衬底基板上的正投影位于静电保护线在衬底基板上的正投影和公共电极线在衬底基板上的正投影之间。
根据一些实施例，静电释放支路与栅线的预设段通过导线连接。
根据一些实施例，静电保护线为公共电极线。
根据一些实施例，周边区域还设置有公共电极线，公共电极线与静电保护线通过导线连接。
根据本公开的另一方面，提供一种显示装置。显示装置包括以上提供的任一阵列基板。
在本公开的实施例提供的阵列基板和显示装置中，通过将栅线的预设段与静电释放支路并联，并将第一静电保护单元连接到该静电释放支路，可以解决现有技术中在栅线正常工作时，在静电保护单元中的晶体管中存在寄生电容从而对栅线的正常工作产生影响的问题。当栅线正常工作时，栅线信号受静电保护单元的影响较小，因而栅线信号能够在阻抗较小的栅线的预设段上传递；而当在栅线上产生静电时，静电保护单元导通，因而静电由静电释放支路流向静电保护线以进行释放。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本公开实施例提供的一种阵列基板的电路结构示意图；
图2是本公开实施例提供的另一种阵列基板的电路结构示意图；
图3是本公开实施例提供的一种阵列基板的电路布线结构示意图；
图4是图3所示阵列基板中沿m1-m2线的截面示意图；
图5是图3所示阵列基板中沿m3-m4线的截面示意图；
图6是本公开实施例提供的一种阵列基板的电路结构示意图；
图7是本公开实施例提供的一种阵列基板的电路结构示意图；
图8是本公开实施例提供的一种阵列基板的电路结构示意图；
图9是本公开实施例提供的一种阵列基板的电路结构示意图；
图10是本公开实施例提供的一种阵列基板的电路结构示意图。
在上述各个附图中，附图标记的含义可以为：
11-衬底基板
Z-周边区域
12-栅线
13-静电释放支路
14-第一静电保护单元
15-静电保护线
y-栅线的预设段
T1-第一N型晶体管
g1-第一N型晶体管的栅极
s1-第一N型晶体管的源极
d1-第一N型晶体管的漏极
T2-第二N型晶体管
g2-第二N型晶体管的栅极
s2-第二N型晶体管的源极
d2-第二N型晶体管的漏极
j1-第一电极
j2-第二电极
k1和k2-过孔
16-公共电极线
17-第二静电保护单元
T3-第三N型晶体管
g3-第三N型晶体管的栅极
s3-第三N型晶体管的源极
d3-第三N型晶体管的漏极
T4-第四N型晶体管
g4-第四N型晶体管的栅极
s4-第四N型晶体管的源极
d4-第四N型晶体管的漏极
18和19-导线
b1-第一N型晶体管的有源层
b2-第二N型晶体管的有源层
31-钝化层
32-栅绝缘层。
这些附图和对应的文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开实施例提供的一种阵列基板的电路结构示意图。该阵列基板可以包括衬底基板11。衬底基板11包括像素区域(图1中未示出)和围绕像素区域的周边区域Z，其中像素区域和周边区域Z设置有栅线12，并且周边区域Z设置有静电释放支路13、第一静电保护单元14和静电保护线15。
静电释放支路13与栅线12的预设段y并联，并且栅线的预设段y位于周边区域Z中。
第一静电保护单元14分别与静电释放支路13和静电保护线15连接。
在本公开实施例中，栅线12延伸到像素区域(图1中未示出)中。
在本公开实施例提供的阵列基板中，通过将栅线的预设段与静电释放支路并联，并将第一静电保护单元连接到该静电释放支路，可以解决现有技术中在栅线正常工作时，在静电保护单元中的晶体管中存在寄生电容从而对栅线的正常工作产生影响的问题。当栅线在正常工作时，栅线信号受静电保护单元的影响较小，因而栅线信号能够在阻抗较小的栅线的预设段上传递；而当在栅线上产生静电时，静电保护单元导通，因而静电由静电释放支路流向静电保护线以进行释放。
进一步的，参考图2，其示出了本公开实施例提供的另一种阵列基板的电路结构示意图。
如图2所示，第一静电保护单元14包括第一N型晶体管T1和第二N型晶体管T2。
第一N型晶体管T1的栅极g1和源极s1均与静电释放支路13连接，并且漏极d1与静电保护线15连接。
第二N型晶体管T2的栅极g2和源极s2均与静电保护线15连接，并且漏极d2与静电释放支路13连接。
当在栅线12上产生静电时，第一N型晶体管T1导通，因而栅线12上的静电通过静电释放支路13经第一N型晶体管T1的源极s1、第一N型晶体管T1的漏极d1流向静电保护线15。当静电流到静电保护线15上时，第二N型晶体管T2导通，因而静电保护线15上的静电经第二N型晶体管T2的源极s2、第二N型晶体管T2的漏极d2流向静电释放支路13。
在图2中，第一晶体管T1的源极s1和第二晶体管T2的漏极d2可以连接后再与静电释放支路13连接，或者分别与静电释放支路13连接。
图3为本公开实施例提供的一种阵列基板的电路布线结构示意图。如图3所示，在周边区域Z中，衬底基板11设置有包括第一N型晶体管T1的栅极g1、第二N型晶体管T2的栅极g2、栅线12和静电释放支路13的第一图案。
在周边区域Z中，设置有第一图案的衬底基板11还设置有包括第一N型晶体管T1的源极s1和漏极d1、第二N型晶体管T2的源极s2和漏极d2以及静电保护线15的第二图案。
在周边区域Z中，设置有第二图案的衬底基板11还设置有第一电极j1和第二电极j2，其中第一电极j1通过两个过孔k1分别与第一N型晶体管T1的源极s1和静电释放支路13连接，并且第二电极j2通过两个过孔k2分别与第二N型晶体管T2的栅极g2和静电保护线15连接。第一电极j1和第二电极j2的材料可以包括氧化铟锡(Indium TinOxides；简称：ITO)。
要指出的是，为使图示更加清楚，在图3中没有示出第一N型晶体管T1和第二N型晶体管T2的有源层的图案。
图4为图3所示的阵列基板的电路布线结构示意图沿m1-m2线的截面示意图，其中，k1指示过孔，j1指示第一电极，13指示静电释放 支路，d2指示第二N型晶体管T2的漏极，11指示衬底基板，32指示栅绝缘层，并且31指示钝化层。
图5为图3所示的阵列基板的电路布线结构示意图沿m3-m4线的截面示意图，其中g1指示第一N型晶体管T1的栅极，g2指示第二N型晶体管T2的栅极，s1指示第一N型晶体管T1的源极，d1指示第一N型晶体管T1的漏极，b1指示第一N型晶体管T1的有源层，s2指示第二N型晶体管T2的源极，d2指示第二N型晶体管T2的漏极，b2指示第二N型晶体管T2的有源层，11指示衬底基板，31指示钝化层，并且32指示栅绝缘层。
图6示出了本公开实施例提供的一种电路结构示意图。在衬底基板11的周边区域Z中，第一静电保护单元14还与栅线12的除栅线的预设段y之外的部分连接，并且第一静电保护单元14包括第一N型晶体管T1和第二N型晶体管T2。
在周边区域Z中，第一N型晶体管T1的栅极g1与静电释放支路13连接，漏极d1与静电保护线15连接，并且源极s1与栅线12的除栅线的预设段y之外的部分连接。
在周边区域Z中，第二N型晶体管T2的栅极g2和源极s2均与静电保护线15连接，并且漏极d2与栅线12的除栅线12的预设段y之外的部分连接。
在图6中，第一晶体管T1的源极s1和第二晶体管T2的漏极d2可以连接后再与栅线12的除栅线的预设段y之外的部分连接，或者分别与栅线12的除栅线的预设段y之外的部分连接。
在图1、图2、图3和图6中，在周边区域Z中，静电保护线15被布置成分别与静电释放支路13和栅线12的预设段y垂直交叉。垂直交叉的布置能够减少静电保护线15分别与静电释放支路13和栅线12的预设段y的重叠面积，从而减少静电保护线15分别与静电释放支路13和栅线12的预设段y的耦合电容，继而减小耦合电容对电路产生的影响，提升电路的性能。
需要说明的是，在图1、图2、图3和图6中，静电释放支路13与栅线12的预设段y可以通过导线(未示出)连接。该导线能够减小栅线信号在静电释放支路13与栅线12的预设段y上传递时的电阻，提升电路的性能。此外，图1、图2、图3和图6中的静电保护线15 可以为公共电极线。
图7为本公开实施例提供的一种阵列基板的电路结构示意图，其中周边区域Z还设置有公共电极线16和第二静电保护单元17。
第二静电保护单元17分别与静电保护线15和公共电极线16连接。图7中其它标记的含义可以参考图2，在此不再赘述。
流入静电保护线15的静电可以通过第二静电保护单元17流入公共电极线16，并且由公共电极线16来释放。
图8图示了图7示出的电路结构示意图中的一种第二静电保护单元17的电路结构示意图。第二静电保护单元17包括：第三N型晶体管T3和第四N型晶体管T4。第三N型晶体管T3的栅极g3和源极s3均与静电保护线15连接，并且漏极d3与公共电极线16连接。
第四N型晶体管T4的栅极g4和源极s4均与公共电极线16连接，并且漏极d4与静电保护线15连接。图8中的其它标记的含义可以参考图7，在此不再赘述。
公共电极线16和静电保护线15也可以直接进行连接，而不设置第二静电保护单元17。如图9所示，周边区域Z还设置有公共电极线16。公共电极线16与静电保护线15通过导线19连接。图9中的其它标记的含义可以参考图7，在此不再赘述。
图10为本公开实施例提供的一种阵列基板的电路结构示意图。如图10所示，静电释放支路13与栅线12的预设段y通过导线18连接，并且导线18在衬底基板11上的正投影位于静电保护线15在衬底基板11上的正投影和公共电极线16在衬底基板11上的正投影之间。静电释放支路13分别与静电保护线15和公共电极线16交叉，并且栅线12的预设段y分别与静电保护线15和公共电极线16交叉。在静电释放支路13与栅线12的预设段y之间连接导线18能够降低栅线信号在静电释放支路13与栅线的预设段y上传递时的电阻，从而进一步提升阵列基板的电路结构的性能。图10中的第一静电保护单元14的具体结构可以参考图2或图6，第二静电保护单元17的具体结构可以参考图8，在此不再赘述。
在图7至图10中，在周边区域Z中，公共电极线16被布置成分别与静电释放支路13和栅线12的预设段y垂直交叉。垂直交叉布置能够减少公共电极线16分别与静电释放支路13和栅线12的预设段y 的重叠面积，从而减少公共电极线16分别与静电释放支路13和栅线12的预设段y的耦合电容，继而减小耦合电容对电路产生的影响，提升电路的性能。
需要说明的是，本公开实施例提供的各个阵列基板上的静电保护线15可以为阵列基板上多条栅线的静电保护线。
在本公开实施例提供的阵列基板中，通过将栅线的预设段与静电释放支路并联，并将第一静电保护单元连接到该，可以解决现有技术中在栅线正常工作时，在静电保护单元中的晶体管中存在寄生电容从而对栅线的正常工作产生影响的问题。当栅线正常工作时，栅线信号受静电保护单元的影响较小，因而栅线信号能够在阻抗较小的栅线的预设段上传递；而当在栅线上产生静电时，静电保护单元导通，因而静电由静电释放支路流向静电保护线以进行释放。
本公开实施例还提供一种显示装置，该显示装置可以包括图1至图10示出的任一阵列基板。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板；
    所述衬底基板包括像素区域和围绕像素区域的周边区域，所述像素区域和所述周边区域设置有栅线，并且所述周边区域设置有静电释放支路、第一静电保护单元和静电保护线；
    所述静电释放支路与所述栅线的预设段并联，所述栅线的预设段位于所述周边区域；
    所述第一静电保护单元分别与所述静电释放支路和所述静电保护线连接。
  2. 根据权利要求1所述的阵列基板，其中，所述第一静电保护单元包括：第一N型晶体管和第二N型晶体管，
    所述第一N型晶体管的栅极和源极均与所述静电释放支路连接，并且第一N型晶体管的漏极与所述静电保护线连接；
    所述第二N型晶体管的栅极和源极均与所述静电保护线连接，并且第二N型晶体管的漏极与所述静电释放支路连接。
  3. 根据权利要求2所述的阵列基板，其中，
    在所述周边区域中，所述衬底基板设置有包括所述第一N型晶体管的栅极、所述第二N型晶体管的栅极、所述栅线和所述静电释放支路的第一图案。
  4. 根据权利要求3所述的阵列基板，其中，
    在所述周边区域中，设置有所述第一图案的所述衬底基板设置有包括所述第一N型晶体管的源极和漏极、所述第二N型晶体管的源极和漏极以及所述静电保护线的第二图案。
  5. 根据权利要求4所述的阵列基板，其中，
    在所述周边区域中，设置有所述第二图案的所述衬底基板设置有第一电极和第二电极，所述第一电极通过两个过孔分别与所述第一N型晶体管的源极和所述静电释放支路连接，并且所述第二电极通过两个过孔分别与所述第二N型晶体管的栅极和所述静电保护线连接。
  6. 根据权利要求1所述的阵列基板，其中，在所述周边区域中，所述第一静电保护单元还与所述栅线的除所述栅线的预设段之外的部 分连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第一静电保护单元包括第一N型晶体管和第二N型晶体管，
    在所述周边区域中，所述第一N型晶体管的栅极与所述静电释放支路连接，所述第一N型晶体管的漏极与所述静电保护线连接，并且所述第一N型晶体管的源极与所述栅线的除所述栅线的预设段之外的部分连接；
    在所述周边区域中，所述第二N型晶体管的栅极和源极均与所述静电保护线连接，并且所述第二N型晶体管的漏极与所述栅线的除所述栅线的预设段之外的部分连接。
  8. 根据权利要求1所述的阵列基板，其中，
    在所述周边区域中，所述静电保护线被布置成分别与所述静电释放支路和所述栅线的预设段垂直交叉。
  9. 根据权利要求1至8任一所述的阵列基板，其中，所述周边区域还设置有公共电极线和第二静电保护单元，并且
    所述第二静电保护单元分别与所述静电保护线和所述公共电极线连接。
  10. 根据权利要求9所述的阵列基板，其中，
    在所述周边区域中，所述公共电极线被布置成分别与所述静电释放支路和所述栅线的预设段垂直交叉。
  11. 根据权利要求9所述的阵列基板，其中，所述第二静电保护单元包括第三N型晶体管和第四N型晶体管，
    所述第三N型晶体管的栅极和源极均与所述静电保护线连接，并且所述第三N型晶体管的漏极与所述公共电极线连接；
    所述第四N型晶体管的栅极和源极均与所述公共电极线连接，并且所述第四N型晶体管的漏极与所述静电保护线连接。
  12. 根据权利要求9所述的阵列基板，其中，所述静电释放支路与所述栅线的预设段通过导线连接，所述导线在所述衬底基板上的正投影位于所述静电保护线在所述衬底基板上的正投影和所述公共电极线在所述衬底基板上的正投影之间。
  13. 根据权利要求1至8任一所述的阵列基板，其中，所述静电释放支路与所述栅线的预设段通过导线连接。
  14. 根据权利要求1所述的阵列基板，其中，所述静电保护线为公共电极线。
  15. 根据权利要求1至8任一所述的阵列基板，其中，所述周边区域还设置有公共电极线，并且
    所述公共电极线与所述静电保护线通过导线连接。
  16. 一种显示装置，包括权利要求1至15任一所述的阵列基板。
PCT/CN2016/098430 2016-04-06 2016-09-08 阵列基板和显示装置 WO2017173779A1 (zh)

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