WO2015016017A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2015016017A1 WO2015016017A1 PCT/JP2014/068174 JP2014068174W WO2015016017A1 WO 2015016017 A1 WO2015016017 A1 WO 2015016017A1 JP 2014068174 W JP2014068174 W JP 2014068174W WO 2015016017 A1 WO2015016017 A1 WO 2015016017A1
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Definitions
- This power semiconductor device 100 includes a semiconductor chip 2, a conductive plate 1, an insulating plate 4, and a ceramic case 11, and the ceramic case 11 and the insulating plate 4 constitute a casing. Furthermore, the sealing material 15 is also provided.
- the semiconductor chip 2 is a vertical switching element such as an IGBT or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and has a front electrode 2a and a back electrode 2b.
- the back electrode 2b of the semiconductor chip 2 is electrically and mechanically connected to the main surface 1a of the conductive plate 1 using a conductive bonding material 3 such as solder.
- An insulating plate 4 is fixed to a surface 1 b opposite to the main surface 1 a of the conductive plate 1.
- the ceramic case 11 includes a ceramic 20 in which the second terminal 6 and the first terminals 7 and 8 are embedded.
- the ceramic case 11 has a first cavity 9 and a second cavity 10 that are concave. Compared to the opening 9a of the first cavity 9, the second cavity 10 has a smaller opening 10a. Furthermore, the ceramic case 11 has an electrode surface 11 a located on the opposite side of the openings 9 a and 10 a of the first cavity 9 and the second cavity 10.
- connection terminals with the outside are arranged on the outer periphery of the case 68.
- the end portions (end surfaces 7 b, 8 b, 6 b) of the first terminals 7, 8 and the second terminals 6 used for connection to the outside are provided at arbitrary locations on the electrode surface 11 a of the ceramic case 11. Can be provided.
- the power semiconductor device 100 can be miniaturized and the wiring length can be greatly reduced.
- the cross-sectional area of the wiring can be increased as compared with the bonding wire 67 (FIG. 19). As a result, the inductance of the wiring can be reduced, and the Joule heat generated in the wiring can be greatly reduced.
- the third to fifth openings 27 to 29 are filled with a conductive paste 30 such as a copper paste or a silver paste (FIG. 2B). This may use a printing process or the like.
- a conductive paste 30 such as a copper paste or a silver paste.
- This may use a printing process or the like.
- the sheets 21 to 24 are stacked (FIG. 2C).
- the main surface 1 a of the conductive plate 1 and the back surface electrode 2 b of the semiconductor chip 2 are bonded by the conductive bonding material 3. Further, the insulating plate 4 is joined to the surface 1b opposite to the main surface 1a of the conductive plate 1 (FIG. 6A). Further, the ceramic case 11 is prepared by the manufacturing method shown in FIG. 2 (FIG. 6B).
- the ceramic case 11 is placed on the support base 40 with the opening 9 a of the first cavity 9 facing upward.
- the bonding material 12 such as a solder plate is placed on the surfaces of the end surfaces 7a and 8a of the first terminals 7 and 8 exposed in the first and second cavities 9 and 10 and the end surface 6a of the second terminal 6 ( FIG. 7).
- FIG. 16 is a cross-sectional view of a power semiconductor device which is a fifth modification.
- the power semiconductor device 502 is different from the power semiconductor device 500 in that the ceramic case 31 is provided with a recess 35 and the wiring board 32 is provided with a protrusion 36 corresponding to the recess 35, and the ceramic case 31 and the wiring are connected to each other while fitting them together. This is the point where the substrate 32 is fixed.
- the length of the interface 37 where the ceramic case 31 and the wiring board 32 are in contact can be increased by providing the concave portion 35 and the convex portion 36 so as to surround the semiconductor chip 2.
- FIG. 17 is a configuration diagram of the power semiconductor device of the seventh embodiment. 17A is a plan view
- FIG. 17B is a cross-sectional view taken along line XX of FIG. 17A.
- FIG. 17A is a plan view of FIG.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Thermistors And Varistors (AREA)
Abstract
Description
絶縁基板64は、絶縁板61、回路板62および金属板63が積層されて構成されており、回路板62にハンダなどの接合材65を介して半導体チップ66が固定されている。また、半導体チップ66は、IGBT(絶縁ゲート型バイポーラトランジスタ)チップやダイオードチップなどのパワー半導体チップである。
(1)外部端子69は半導体チップ66の上部に配置するのが困難であり、ケース68など外周部に配置せざるを得ず、筐体の小型化が困難である。
(2)封止樹脂71は通常ゲルであることから、外形維持のため、ケース68や上蓋72が別途必要になる。
(3)半導体チップ66の搭載数が20個程度であるとすると、各半導体チップ66にそれぞれ10本程度のボンディングワイヤ67を配線するには、ボンディングワイヤ67の数は相当な本数になり、配線工程に時間がかかる。
本発明の上記および他の目的、特徴および利点は本発明の例として好ましい実施の形態を表す添付の図面と関連した以下の説明により明らかになるであろう。
なお、以下に用いられる「電気的かつ機械的に接続されている」という用語は、対象物同士が直接接合により接続されている場合に限らず、ハンダや金属焼結材などの導電性の接合材を介して対象物同士が接続されている場合も含むものとする。
<第1実施例>
図1は、第1実施例のパワー半導体装置の構成図である。図1(a)は平面図、図1(b)は図1(a)のX-X線で切断した断面図である。また、図1(a)は、図1(b)の矢印A方向から見た透視平面図である。
本実施例のパワー半導体装置100は、半導体チップ2が格納されるセラミックケース11に第1端子7,8および第2端子6を配置することで、外部との接続端子を半導体チップ2直上に配置することができる。また、セラミックケース11の第1キャビティ9および第2キャビティ10に半導体チップ2と導電板1を格納するため、パワー半導体装置100の占有面積を小さくすることができる。また、セラミックケース11に第1端子7,8および第2端子6を埋設させ、この第1端子7,8及び第2端子6を直接半導体チップ2や導電板1に電気的かつ機械的に接続している。そのため、パワー半導体装置100の厚さを数mm程度に薄くすることができる。これらにより、パワー半導体装置100の小型化を図ることができる。
図2は、第1実施例のキャビティおよび端子を有するセラミックケースの製造方法を示す図である。
つぎに、シート21~24を積層する(図2(c))。
(第1変形例)
図3は、第1変形例であるパワー半導体装置の断面図である。
(第2変形例)
図4は、第2変形例であるパワー半導体装置の断面図である。
(第3変形例)
図5は、第3変形例であるパワー半導体装置の断面図である。
<第2実施例>
図6~図9は、第2実施例のパワー半導体装置の製造工程を示す図である。
パワー半導体装置1000(図19)では、ジュール熱の発生が大きくなるため、半導体チップ66のおもて面電極に複数本のボンディングワイヤ67を配置していた。一方、本実施例のパワー半導体装置100では、第1端子7,8および第2端子6の断面積を大きくできるため、半導体チップ2のおもて面電極2aに1つの端子を設ければよく、組み立てを単純化することができる。このため、組立時間の短縮、歩留まりの改善、品質管理項目の削減などを図ることができ、パワー半導体装置100の低コスト化を実現できる。
<第3実施例>
図11は、第3実施例のパワー半導体装置の断面図である。
2つの半導体チップ2は、例えば、IGBTチップと還流ダイオード(FWD)チップである。IGBTチップのコレクタ電極とFWDチップのカソード電極は導電板1に電気的かつ機械的に接続されている。また、IGBTチップのエミッタ電極とFWDのアノード電極は、セラミックケース11に埋設された2本の第1端子7の一端にそれぞれ電気的かつ機械的に接続されている。そして、2本の第1端子7の他端を電気的に接続することにより、IGBTとFWDの逆並列回路を構成することができる。
<第4実施例>
図12は、第4実施例のパワー半導体装置の断面図である。
<第5実施例>
図13は、第5実施例のパワー半導体装置の断面図である。
<第6実施例>
図14は、第6実施例のパワー半導体装置の断面図である。図1に示したパワー半導体装置100と同一の部材については同一の符号を付しており、以下では重複する記載を省略する。
セラミックケース31は、セラミック20を備え、第1端子7,8および第2端子6が埋設されている。また、セラミックケース31は、凹形状である第2キャビティ10を有している。さらにセラミックケース31は、第2キャビティ10の開口部と反対側に位置する電極面31aを有する。
そして、第2キャビティ10に格納された半導体チップ2のおもて面電極2aと、セラミックケース31に埋設された第1端子7,8の一端(端面7a,8a)が、電気的かつ機械的に接続されている。また、第1端子7,8の他端は、セラミックケース31の電極面31aから露出している。
つぎに、パワー半導体装置500の変形例について説明する。
(第4変形例)
図15は、第4変形例であるパワー半導体装置の断面図である。
(第5変形例)
図16は、第5変形例であるパワー半導体装置の断面図である。
<第7実施例>
図17は、第7実施例のパワー半導体装置の構成図である。図17(a)は平面図、図17(b)は図17(a)のX-X線で切断した断面図である。図17(a)は図17(b)を矢印Aから見た平面図である。
<第8実施例>
図18は、第8実施例のパワー半導体装置の断面図である。
1a 主面
1b 主面と反対側の面
2 半導体チップ
2a おもて面電極
2b 裏面電極
3,12,12a 接合材
4 絶縁板
4b 裏面
5 金属板
6,39 第2端子
6a,6b,7a,7b,8a,8b 端面
7,8 第1端子
9 第1キャビティ
9a,10a 開口部
10 第2キャビティ
11,31 セラミックケース
11a,31a 電極面
11b 底面
13 リフロー炉
14 隙間
15 封止材
16 ディスペンサ
17 注入口
18 DCB基板
19 アタッチメント
19a 導体
20 セラミック
21~24 シート
25 第1開口部
26 第2開口部
27 第3開口部
28 第4開口部
29 第5開口部
30 導電ペースト
31c 側面
32 配線基板
33 配線板
33a 露出面
34 ダミー導電膜
35 凹部
36 凸部
37 界面
38 キャビティ
40 支持台
100,101,102,103,200,300,400,500,501,502,600,700 パワー半導体装置
Claims (12)
- おもて面電極および裏面電極を有する半導体チップと、
主面に前記半導体チップの裏面電極が接続される導電板と、
前記導電板の前記主面と反対側の面に固定される絶縁板と、
埋設された第1端子および第2端子と、前記半導体チップ、前記導電板および前記絶縁板が格納されるキャビティと、前記キャビティの開口部と反対側に位置する電極面を有するセラミックケースと、
を備え、
前記第1端子の一端が前記半導体チップのおもて面電極と接続されるとともに、他端が前記電極面から露出し、
前記第2端子の一端が前記導電板の前記主面に接続されるとともに、他端が前記電極面から露出し、
前記セラミックケースおよび前記絶縁板で筐体を構成する半導体装置。 - 前記キャビティが、前記導電板が格納される第1キャビティと、前記第1キャビティと繋がり前記半導体チップが格納され前記第1キャビティより開口部の小さな第2キャビティとから構成される請求項1記載の半導体装置。
- 前記絶縁板の前記導電板が固定された面の反対側の面に、さらに金属板を有する請求項1記載の半導体装置。
- 前記セラミックケースに複数の前記キャビティを有する請求項1記載の半導体装置。
- おもて面電極および裏面電極を有する半導体チップと、
埋設された導電性の配線板を有し、前記配線板の露出面に前記半導体チップの裏面電極が接続される配線基板と、
埋設された第1端子および第2端子と、前記半導体チップが格納されるキャビティと、前記キャビティの開口部と反対側に位置する電極面を有するセラミックケースと、
を備え、
前記第1端子の一端が前記半導体チップのおもて面電極と接続されるとともに、他端が前記電極面から露出し、
前記第2端子の一端が前記配線板の露出面と接続されるとともに、他端が前記電極面から露出し、
前記セラミックケースおよび前記配線基板で筐体を構成する半導体装置。 - おもて面電極および裏面電極を有する半導体チップと、
埋設された導電性の配線板を有し、前記配線板の露出面に前記半導体チップの裏面電極が接続される配線基板と、
埋設された第1端子および第2端子と、前記半導体チップが格納されるキャビティと、前記キャビティの開口部と反対側に位置する電極面を有するセラミックケースと、
を備え、
前記第1端子の一端が前記半導体チップのおもて面電極と接続されるとともに、他端が前記電極面から露出し、
前記第2端子の一端が前記配線板の露出面と接続されるとともに、他端が前記電極面と直交する面から突出し、
前記セラミックケースおよび前記配線基板で筐体を構成する半導体装置。 - 前記セラミックケースが、低温同時焼成セラミックで構成されている請求項1記載の半導体装置。
- 前記半導体チップと前記セラミックケースの間が封止材で埋められている請求項1記載の半導体装置。
- 前記封止材が、エポキシ樹脂である請求項8記載の半導体装置。
- 前記第1端子および前記第2端子の厚さが、100μm以上である請求項1記載の半導体装置。
- 前記セラミックケースと前記配線基板の接合面に凹凸を有する請求項5記載の半導体装置。
- 前記配線板の露出面が、前記配線基板に備えられたキャビティの底面に配置されている請求項5記載の半導体装置。
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DE112014000862.1T DE112014000862T8 (de) | 2013-07-31 | 2014-07-08 | Halbleitervorrichtung |
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WO2019171795A1 (ja) * | 2018-03-08 | 2019-09-12 | 住友電気工業株式会社 | 半導体モジュール |
WO2022185522A1 (ja) * | 2021-03-05 | 2022-09-09 | 株式会社メイコー | 部品内蔵基板、及びその製造方法 |
WO2024062649A1 (ja) * | 2022-09-22 | 2024-03-28 | 株式会社レゾナック | 積層体、積層体の製造方法、及び導電積層体 |
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JP2018049938A (ja) * | 2016-09-21 | 2018-03-29 | 株式会社東芝 | 半導体装置 |
DE102020205043A1 (de) * | 2020-04-21 | 2021-10-21 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung eingetragener Verein | Verfahren zur Herstellung einer Leistungshalbleiterbauelementanordnung oder Leistungshalbleiterbauelementeinhausung |
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