WO2010131573A1 - 絶縁ゲート型バイポーラトランジスタ - Google Patents
絶縁ゲート型バイポーラトランジスタ Download PDFInfo
- Publication number
- WO2010131573A1 WO2010131573A1 PCT/JP2010/057445 JP2010057445W WO2010131573A1 WO 2010131573 A1 WO2010131573 A1 WO 2010131573A1 JP 2010057445 W JP2010057445 W JP 2010057445W WO 2010131573 A1 WO2010131573 A1 WO 2010131573A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- silicon carbide
- substrate
- sic
- base layer
- Prior art date
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 413
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 367
- 239000000758 substrate Substances 0.000 claims abstract description 279
- 239000012535 impurity Substances 0.000 claims abstract description 61
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 239000013078 crystal Substances 0.000 claims description 41
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052799 carbon Inorganic materials 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 40
- 239000010410 layer Substances 0.000 description 363
- 238000004519 manufacturing process Methods 0.000 description 61
- 238000000034 method Methods 0.000 description 33
- 238000010438 heat treatment Methods 0.000 description 22
- 239000002994 raw material Substances 0.000 description 18
- 239000012298 atmosphere Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 230000009467 reduction Effects 0.000 description 9
- 238000000859 sublimation Methods 0.000 description 9
- 230000008022 sublimation Effects 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000002243 precursor Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000011261 inert gas Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000001294 propane Substances 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- WSFSSNUMVMOOMR-NJFSPNSNSA-N methanone Chemical compound O=[14CH2] WSFSSNUMVMOOMR-NJFSPNSNSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021470 non-graphitizable carbon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000011343 solid material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Definitions
- the present invention relates to an insulated gate bipolar transistor (IGBT), and more particularly to an IGBT capable of achieving a reduction in on-resistance while suppressing defects such as micropipes, stacking faults, and dislocations.
- IGBT insulated gate bipolar transistor
- silicon carbide (SiC) is being adopted as a material constituting a semiconductor device in order to enable a semiconductor device to have a high breakdown voltage, low loss, and use in a high temperature environment.
- Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device.
- a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.
- a process of preparing a substrate made of silicon carbide (silicon carbide substrate) and forming an epitaxial growth layer made of SiC on the silicon carbide substrate is adopted. It is valid.
- the ON resistance of IGBT can be reduced by reducing the resistivity in the thickness direction of a substrate as much as possible.
- a method of introducing impurities into the substrate at a high concentration can be adopted (for example, RC GLASS et al., “SiC Seed Crystal Growth”). Phys. Stat. Sol. (B), 1997, 202, p149-162 (Non-Patent Document 1)).
- a high quality epitaxial growth layer with few dislocations and defects is required.
- p-type impurities are introduced into the substrate at a high concentration to reduce the resistivity of the substrate.
- the density of defects such as micropipes, stacking faults, and dislocations increases.
- the epitaxial growth layer which consists of SiC is formed on the said silicon carbide substrate, the said defect propagates also in an epitaxial growth layer.
- the defects in the epitaxial growth layer function as minority carrier traps and reduce the carrier lifetime.
- conductivity modulation is hindered due to a high defect density, which causes a problem that forward characteristics of the IGBT are deteriorated.
- an object of the present invention is to provide a vertical IGBT that can achieve a reduction in on-resistance while suppressing the occurrence of defects.
- An insulated gate bipolar transistor (IGBT) comprises a silicon carbide substrate, a single crystal silicon carbide, a conductivity type n-type drift layer disposed on one main surface of the silicon carbide substrate, The conductivity type arranged to include the first main surface opposite to the silicon carbide substrate in the drift layer has a p-type well region and the conductivity type arranged to include the first main surface in the well region.
- An n-type emitter region, an emitter electrode disposed on the first main surface so as to be in contact with the emitter region, and an insulator are disposed on the first main surface so as to be in contact with the well region.
- the silicon carbide substrate includes a base layer made of silicon carbide and having a conductivity type of p-type, and a SiC layer made of single crystal silicon carbide and disposed on the base layer.
- the p-type impurity concentration of the base layer exceeds 1 ⁇ 10 18 cm ⁇ 3 .
- the present inventor has conducted detailed studies on a measure for reducing the resistivity in the thickness direction while suppressing the occurrence of defects such as micropipes, stacking faults, and dislocations in the silicon carbide substrate. As a result, the following findings were obtained. That is, the resistivity is reduced so that the p-type impurity concentration (p-type impurity density) in the base layer of the silicon carbide substrate exceeds 1 ⁇ 10 18 cm ⁇ 3, and micropipes and stacking faults are formed on the base layer. By disposing a SiC layer containing impurities that can suppress the occurrence of defects such as dislocations, at least the generation of stacking faults can be suppressed in the SiC layer.
- an epitaxial growth layer (layer constituting the active layer) made of SiC is formed on the SiC layer to produce an IGBT, thereby achieving a reduction in resistivity of the silicon carbide substrate due to the presence of the base layer. It is possible to suppress the influence of defects such as micropipes, stacking faults, and dislocations that can occur in the layer on the characteristics of the IGBT.
- impurity refers to an impurity introduced to generate majority carriers in the silicon carbide substrate.
- the p-type impurity concentration in the base layer can be 1 ⁇ 10 21 cm ⁇ 3 or less.
- the p-type impurity concentration in the base layer may be 1 ⁇ 10 20 cm ⁇ 3 or more.
- the impurity introduced into the base layer for example, Al (aluminum), B (boron), or the like can be employed.
- the base layer and the SiC layer are bonded, for example.
- a silicon carbide substrate on which an SiC layer is arranged can be easily obtained while suppressing the propagation of defects in the base layer.
- the base layer and the SiC layer may be directly bonded or may be bonded via an intermediate layer.
- the impurities contained in the base layer and the impurities contained in the SiC layer may be different. Thereby, IGBT provided with the silicon carbide substrate containing the suitable impurity according to the objective can be provided.
- Al aluminum
- Al aluminum
- SiC silicon
- the base layer is made of single crystal silicon carbide, and the half width of the X-ray rocking curve of the SiC layer may be smaller than the half width of the X-ray rocking curve of the base layer.
- SiC does not have a liquid phase at normal pressure.
- the crystal growth temperature in a sublimation recrystallization method performed as a bulk single crystal SiC crystal growth method is very high, 2000 ° C. or more, and it is difficult to control growth conditions and stabilize them. Therefore, it is difficult to increase the diameter of a substrate made of single crystal SiC while maintaining high quality.
- a substrate having a uniform shape and size is required. Therefore, even when a high quality silicon carbide single crystal (for example, single crystal silicon carbide having high crystallinity) is obtained, a region that cannot be processed into a predetermined shape by cutting or the like may not be used effectively.
- the half width of the X-ray rocking curve is smaller than the base layer on the base layer processed into the predetermined shape and size, that is, the crystal A SiC layer that has high properties but does not have a desired shape or the like can be disposed. Since such a silicon carbide substrate is unified in a predetermined shape and size, the production of the IGBT can be made efficient. Moreover, since it is possible to manufacture IGBT using such a high quality SiC layer of a silicon carbide substrate, high quality single crystal silicon carbide can be used effectively. As a result, it is possible to reduce the manufacturing cost of the IGBT.
- the SiC layer may have a p-type conductivity and an impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or less.
- production of defects such as a micropipe in a SiC layer, a stacking fault, and a dislocation, can be suppressed more reliably.
- the insulating film may be made of silicon dioxide. Thereby, the insulating film can be easily formed.
- the main surface of the SiC layer opposite to the base layer may have an off angle of 50 ° to 65 ° with respect to the ⁇ 0001 ⁇ plane.
- Hexagonal single crystal silicon carbide can be produced in a ⁇ 0001> direction to efficiently produce a high quality single crystal. And from the silicon carbide single crystal grown in the ⁇ 0001> direction, a silicon carbide substrate having a ⁇ 0001 ⁇ plane as a main surface can be efficiently collected.
- a high performance IGBT may be manufactured by using a silicon carbide substrate having a main surface with an off angle of 50 ° or more and 65 ° or less with respect to the plane orientation ⁇ 0001 ⁇ .
- the silicon carbide substrate used for manufacturing the IGBT generally has a main surface with an off angle of about 8 ° or less with respect to the plane orientation ⁇ 0001 ⁇ . Then, an epitaxial growth layer (active layer) is formed on the main surface, and an insulating film (oxide film), an electrode, and the like are formed on the active layer, and an IGBT is obtained. In this IGBT, a channel region is formed in a region including the interface between the active layer and the insulating film.
- the off-angle of the main surface of the SiC layer opposite to the base layer with respect to the ⁇ 0001 ⁇ plane is 50 ° or more and 65 ° or less, thereby reducing the formation of the interface state.
- an IGBT with reduced on-resistance can be manufactured.
- the angle formed between the off orientation of the main surface of the SiC layer opposite to the base layer and the ⁇ 1-100> direction may be 5 ° or less.
- the ⁇ 1-100> direction is a typical off orientation in the silicon carbide substrate. Then, by setting the variation in the off orientation due to the variation in slicing in the substrate manufacturing process to 5 ° or less, it is possible to easily form the epitaxial growth layer (active layer) on the silicon carbide substrate.
- the off-angle of the main surface of the SiC layer opposite to the base layer with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction is not less than ⁇ 3 ° and not more than 5 °. Good.
- the channel mobility in the case of manufacturing an IGBT using a silicon carbide substrate can be further improved.
- the off angle with respect to the plane orientation ⁇ 03-38 ⁇ is set to ⁇ 3 ° or more and + 5 ° or less.
- the channel mobility is particularly high within this range. Is based on the obtained.
- the “off angle with respect to the ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction” is an orthogonal projection of the normal of the principal surface to the plane extending in the ⁇ 1-100> direction and the ⁇ 0001> direction, This is an angle formed with the normal of the ⁇ 03-38 ⁇ plane, and its sign is positive when the orthographic projection approaches parallel to the ⁇ 1-100> direction, and the orthographic projection is in the ⁇ 0001> direction. The case of approaching parallel to is negative.
- the plane orientation of the main surface is substantially ⁇ 03-38 ⁇ .
- the surface orientation of the main surface is substantially ⁇ 03-38 ⁇ , taking into account the processing accuracy of the substrate, etc., the substrate is within an off-angle range where the surface orientation can be substantially regarded as ⁇ 03-38 ⁇ .
- the off angle range is, for example, a range of ⁇ 2 ° with respect to ⁇ 03-38 ⁇ .
- the angle formed between the off orientation of the main surface of the SiC layer opposite to the base layer and the ⁇ 11-20> direction may be 5 ° or less.
- ⁇ 11-20> is a typical off orientation in the silicon carbide substrate, similarly to the above ⁇ 1-100> direction. Then, by setting the variation in the off orientation due to the variation in the slice processing in the substrate manufacturing process to ⁇ 5 °, it is possible to facilitate the formation of the epitaxial growth layer (active layer) on the SiC substrate.
- the base layer may be made of single crystal silicon carbide.
- the defect density of the SiC layer is preferably lower than the defect density of the base layer.
- the micropipe density of the SiC layer is smaller than the micropipe density of the base layer.
- the dislocation density of the SiC layer is lower than the dislocation density of the base layer.
- the threading screw dislocation density of the SiC layer is smaller than the threading screw dislocation density of the base layer.
- the threading edge dislocation density of the SiC layer is smaller than the threading edge dislocation density of the base layer.
- the basal plane dislocation density of the SiC layer is smaller than the basal plane dislocation density of the base layer.
- the mixed dislocation density of the SiC layer is smaller than the mixed dislocation density of the base layer.
- the stacking fault density of the SiC layer is smaller than the stacking fault density of the base layer.
- the point defect density of the SiC layer is smaller than the point defect density of the base layer.
- a high quality active layer can be formed on the SiC layer.
- the active layer can be formed, for example, by combining epitaxial growth and impurity ion implantation.
- a plurality of SiC layers may be laminated. Thereby, IGBT provided with the silicon carbide substrate containing the some SiC layer according to the target function can be obtained.
- the silicon carbide substrate further includes an intermediate layer made of a conductor or a semiconductor, which is disposed between the base layer and the SiC layer, and the intermediate layer joins the base layer and the SiC layer. Also good.
- the intermediate layer may be made of metal. A part of the metal constituting the intermediate layer may be silicided. In the IGBT, the intermediate layer may be made of carbon. The intermediate layer may be made of amorphous silicon carbide. Thereby, the electroconductivity in the thickness direction of a board
- the base layer may include a single crystal layer made of single crystal silicon carbide so as to include a main surface on the side facing the SiC layer.
- a difference in physical properties for example, a difference in linear expansion coefficient
- the region other than the single crystal layer of the base layer may be a non-single crystal layer such as polycrystalline silicon carbide, amorphous silicon carbide, or silicon carbide sintered body. Thereby, the manufacturing cost of the semiconductor device can be reduced.
- the half width of the X-ray rocking curve of the SiC layer is smaller than the half width of the X-ray rocking curve of the single crystal layer.
- the micropipe density of a SiC layer is lower than the micropipe density of a single crystal layer.
- the dislocation density of the SiC layer is preferably lower than the dislocation density of the single crystal layer.
- the IGBT of the present invention it is possible to provide a vertical IGBT that can achieve a reduction in on-resistance while suppressing the occurrence of defects.
- FIG. 12 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in a third embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
- FIG. 6 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a fourth embodiment.
- FIG. 6 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a fifth embodiment.
- 10 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in a fifth embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the third embodiment.
- FIG. 6 is a schematic cross sectional view showing a
- FIG. 10 is a schematic cross sectional view showing a structure of a silicon carbide substrate in a sixth embodiment.
- 17 is a flowchart showing an outline of a method for manufacturing a silicon carbide substrate in a sixth embodiment.
- FIG. 11 is a schematic cross sectional view for illustrating the method for manufacturing the silicon carbide substrate in the seventh embodiment. It is a figure which shows the relationship between the impurity concentration and mobility in p-type 4H-SiC.
- IGBT 100 which is an insulated gate bipolar transistor in the present embodiment, includes a silicon carbide substrate 1 having a p-type conductivity and a buffer layer 2 (the conductivity type may be n-type or p-type).
- a drift layer 3 made of silicon carbide and having a conductivity type of n, a pair of well regions 4 having a conductivity type of p type, an n + region 5 as an emitter region having a conductivity type of n type, and a conductivity type of p.
- a p + region 6 as a high-concentration p-type region of the mold.
- Buffer layer 2 is formed on one main surface of silicon carbide substrate 1 and contains a higher concentration of impurities than drift layer 3.
- Drift layer 3 is formed on buffer layer 2 and has an n-type conductivity by including an n-type impurity.
- the pair of well regions 4 are formed separately from each other in the drift layer 3 so as to include a main surface 3A opposite to the main surface on the silicon carbide substrate 1 side, and have a conductivity type by including p-type impurities. It is p-type.
- the p-type impurity contained in the well region 4 is, for example, aluminum (Al), boron (B), or the like.
- the n + region 5 is formed inside each of the pair of well regions 4 so as to include the main surface 3 ⁇ / b > A and be surrounded by the well region 4.
- the n + region 5 contains an n-type impurity, such as P, at a higher concentration (density) than the n-type impurity contained in the drift layer 3.
- the p + region 6 includes the main surface 3 A, is surrounded by the well region 4, and is formed inside each of the pair of well regions 4 so as to be adjacent to the n + region 5.
- the p + region 6 contains a p-type impurity such as Al at a higher concentration (density) than the p-type impurity contained in the well region 4.
- the buffer layer 2, drift layer 3, well region 4, n + region 5 and p + region 6 constitute an active layer 7.
- the IGBT 100 includes a gate oxide film 91 as a gate insulating film, a gate electrode 93, a pair of emitter contact electrodes 92, an interlayer insulating film 94, an emitter wiring 95, and a collector electrode 96. And.
- Gate oxide film 91 is formed on main surface 3A of drift layer 3 so as to be in contact with main surface 3A and to extend from the upper surface of one n + region 5 to the upper surface of the other n + region 5.
- it is made of silicon dioxide (SiO 2 ).
- Gate electrode 93 is arranged in contact with gate oxide film 91 so as to extend from one n + region 5 to the other n + region 5.
- the gate electrode 93 is made of a conductor such as polysilicon or Al to which impurities are added.
- the emitter contact electrode 92 extends from each of the pair of n + regions 5 to the p + region 6 and is disposed in contact with the main surface 3A.
- the emitter contact electrode 92 is made of a material that can make ohmic contact with both the n + region 5 and the p + region 6, such as NiSi (nickel silicide).
- Interlayer insulating film 94 is formed on main surface 3A of drift layer 3 so as to surround gate electrode 93 and to extend from one well region 4 to the other well region 4, and is, for example, an insulator. It consists of silicon dioxide (SiO 2 ).
- Emitter wiring 95 surrounds interlayer insulating film 94 on main surface 3 ⁇ / b> A of drift layer 3 and extends to the upper surface of emitter contact electrode 92.
- the emitter wiring 95 is made of a conductor such as Al and is electrically connected to the n + region 5 through the emitter contact electrode 92.
- the collector electrode 96 is formed in contact with the main surface of the silicon carbide substrate 1 opposite to the side on which the drift layer 3 is formed.
- the collector electrode 96 is made of a material capable of making ohmic contact with the silicon carbide substrate 1 such as NiSi, and is electrically connected to the silicon carbide substrate 1.
- silicon carbide substrate 1 constituting IGBT 100 in the present embodiment is made of single crystal silicon carbide, is made of base layer 10 having a conductivity type of p type, and single crystal silicon carbide, SiC layer 20 having a conductivity type of p type disposed on base layer 10 is included.
- the p-type impurity concentration of the base layer 10 exceeds 1 ⁇ 10 18 cm ⁇ 3 . Therefore, the IGBT 100 in the present embodiment is a vertical IGBT that can achieve a reduction in on-resistance while suppressing the occurrence of defects.
- Base layer 10 may be made of, for example, single crystal silicon carbide, polycrystalline silicon carbide, amorphous silicon carbide, a silicon carbide sintered body, or a combination thereof.
- the operation of the IGBT 100 will be described.
- a positive voltage is applied to gate electrode 93 and the positive voltage exceeds a threshold value, an inversion layer is formed in well region 4 in contact with gate oxide film 91 under gate electrode 93, and n The + region 5 and the drift layer 3 are electrically connected.
- electrons are injected from n + region 5 into drift layer 3, and holes are supplied to drift layer 3 from silicon carbide substrate 1 through buffer layer 2 correspondingly.
- the IGBT 100 is turned on, conductivity modulation occurs in the drift layer 3, and a current flows with the resistance between the emitter contact electrode 92 and the collector electrode 96 lowered.
- the inversion layer is not formed, so that a reverse bias state is maintained between the drift layer 3 and the well region 4. As a result, the IGBT 100 is turned off and no current flows.
- the base layer 10 may be made of single crystal silicon carbide.
- the micropipe density of SiC layer 20 is preferably smaller than the micropipe density of base layer 10.
- the threading screw dislocation density of the SiC layer 20 is smaller than the threading screw dislocation density of the base layer 10.
- the threading edge dislocation density of SiC layer 20 is smaller than the threading edge dislocation density of base layer 10.
- the basal plane dislocation density of SiC layer 20 is preferably smaller than the basal plane dislocation density of base layer 10.
- the mixed dislocation density of SiC layer 20 is preferably smaller than the mixed dislocation density of base layer 10.
- the stacking fault density of SiC layer 20 is preferably smaller than the stacking fault density of base layer 10.
- the point defect density of SiC layer 20 is preferably smaller than the point defect density of base layer 10.
- the SiC layer in which the defect density such as the micropipe density, the threading screw dislocation density, the threading edge dislocation density, the basal plane dislocation density, the mixed dislocation density, the stacking fault density, and the point defect density is reduced as compared with the base layer 10.
- the high-quality active layer 7 can be formed on the SiC layer 20.
- the p-type impurity concentration of the SiC layer 20 may be 1 ⁇ 10 18 cm ⁇ 3 or less.
- base layer 10 is made of single crystal silicon carbide, and the half width of the X-ray rocking curve of SiC layer 20 is smaller than the half width of the X-ray rocking curve of base layer 10. Also good.
- the SiC layer 20 has high crystallinity.
- Single crystal silicon carbide in which a desired shape or the like is not realized can be used effectively. As a result, the manufacturing cost of the IGBT 100 can be reduced.
- main surface 20A of SiC layer 20 opposite to base layer 10 in silicon carbide substrate 1 has an off angle of 50 ° or more and 65 ° or less with respect to the ⁇ 0001 ⁇ plane. preferable.
- the angle formed between the off orientation of main surface 20A of SiC layer 20 opposite to base layer 10 and ⁇ 1-100> direction is 5 ° or less. Is preferred.
- the ⁇ 1-100> direction is a typical off orientation in the silicon carbide substrate. Then, the variation in the off orientation caused by the variation in the slice processing in the manufacturing process of the substrate is set to 5 ° or less, thereby facilitating the formation of the epitaxial growth layer (active layer 7) on the silicon carbide substrate 1. it can.
- IGBT 100 in silicon carbide substrate 1, off-angle with respect to ⁇ 03-38 ⁇ plane in the ⁇ 1-100> direction of main surface 20A of SiC layer 20 opposite to base layer 10 is ⁇ 3 °.
- the angle is preferably 5 ° or less.
- IGBT 100 in silicon carbide substrate 1, even if the angle formed between the off orientation of main surface 20A of SiC layer 20 opposite to base layer 10 and ⁇ 11-20> direction is 5 ° or less. Good.
- ⁇ 11-20> is a typical off orientation in the silicon carbide substrate, similarly to the above ⁇ 1-100> direction. Then, the variation of the off orientation caused by the variation of the slice processing in the manufacturing process of the substrate is set to ⁇ 5 °, whereby the formation of the epitaxial growth layer (active layer 7) on the SiC layer 20 can be facilitated. .
- the impurity contained in base layer 10 and the impurity contained in SiC layer 20 may be different. Thereby, IGBT100 provided with the silicon carbide substrate 1 containing the suitable impurity according to the intended purpose can be obtained.
- a silicon carbide substrate preparation step is first performed as a step (S ⁇ b> 110).
- step (S110) referring to FIG. 4, base layer 10 made of single crystal silicon carbide and having a conductivity type of p type, and conductivity type made of single crystal silicon carbide and arranged on base layer 10 are made of p.
- a silicon carbide substrate 1 including a SiC layer 20 that is a type and having a p-type impurity concentration of base layer 10 exceeding 1 ⁇ 10 18 cm ⁇ 3 is prepared.
- single crystal is included so as to include main surface 10A on the side facing SiC layer 20 instead of base layer 10 made entirely of single crystal silicon carbide.
- Base layer 10 including single crystal layer 10B made of silicon carbide and other region 10C made of polycrystalline silicon carbide, amorphous silicon carbide, or silicon carbide sintered body may be employed.
- base layer 10 made entirely of single crystal silicon carbide base layer 10 made entirely of polycrystalline silicon carbide, amorphous silicon carbide, or silicon carbide sintered body may be employed. A method for manufacturing silicon carbide substrate 1 will be described later.
- buffer layer 2 and drift layer 3 made of silicon carbide and having an n conductivity type are sequentially formed on one main surface of silicon carbide substrate 1 by epitaxial growth.
- an ion implantation step is performed as a step (S130).
- ion implantation for forming well region 4 is performed. Specifically, for example, Al (aluminum) ions are implanted into drift layer 3 to form well region 4.
- ion implantation for forming the n + region 5 is performed. More specifically, for example, P (phosphorus) ions are implanted into the well region 4 to form an n + region 5 in the well region 4.
- ion implantation for forming the p + region 6 is performed. Specifically, for example, Al ions are implanted into the well region 4, thereby forming a p + region 6 in the well region 4.
- the ion implantation can be performed by, for example, forming a mask layer made of silicon dioxide (SiO 2 ) on the main surface of the drift layer 3 and having an opening in a desired region where ion implantation is to be performed.
- an activation annealing step is performed as a step (S140).
- this step (S140) for example, heat treatment is performed by heating to 1700 ° C. in an inert gas atmosphere such as argon and holding for 30 minutes. Thereby, the impurities implanted in the step (S130) are activated.
- an oxide film forming step is performed as a step (S150).
- this step (S150) referring to FIGS. 5 and 6, for example, an oxide film (gate oxide film) 91 is formed by performing a heat treatment in an oxygen atmosphere by heating to 1300 ° C. and holding for 60 minutes. Is done.
- an electrode formation step is performed as a step (S160).
- a step (S160) after forming gate electrode 93 made of polysilicon which has been doped with an impurity by, for example, CVD, an insulator is formed by, for example, CVD.
- An interlayer insulating film 94 made of SiO 2 is formed so as to surround the gate electrode 93 on the main surface 3A.
- a nickel (Ni) film formed by, for example, a vapor deposition method is heated and silicided, whereby the emitter contact electrode 92 and the collector electrode 96 are formed.
- an emitter wiring 95 made of Al as a conductor surrounds the interlayer insulating film 94 on the main surface 3A and extends to the upper surfaces of the n + region 5 and the emitter contact electrode 92 by, for example, vapor deposition. Formed to exist.
- the IGBT 100 in the present embodiment is completed by the above procedure.
- step (S110) single crystal layer 10B made of single crystal silicon carbide is included so as to include main surface 10A on the side facing SiC layer 20, and other region 10C is polycrystalline silicon carbide, amorphous silicon carbide, or
- base layer 10 made of a silicon carbide sintered body When base layer 10 made of a silicon carbide sintered body is employed, a step of removing other region 10C may be performed. Thereby, IGBT100 provided with the base layer 10 which consists of single crystal silicon carbide can be obtained (refer FIG. 1). On the other hand, the step of removing the region 10C may not be performed. In this case, polycrystalline silicon carbide, amorphous silicon carbide, or a main surface opposite to SiC layer 20 of base layer 10 of IGBT 1 shown in FIG.
- a non-single crystal layer (corresponding to the region 10C) made of a silicon carbide sintered body is formed.
- This non-single crystal layer does not significantly affect the characteristics of the IGBT 100 as long as its resistivity is low. Therefore, by adopting such a manufacturing process, the manufacturing cost of the IGBT 100 can be reduced without significantly affecting the characteristics.
- the half width of the X-ray rocking curve of the SiC layer 20 may be smaller than the half width of the X-ray rocking curve of the single crystal layer 10B.
- the high-quality active layer 7 can be formed by disposing the SiC layer 20 having a small half width of the X-ray rocking curve, that is, high crystallinity, as compared with the single crystal layer 10B of the base layer 10. it can.
- the micropipe density of SiC layer 20 may be lower than the micropipe density of single crystal layer 10B.
- the dislocation density of SiC layer 20 may be lower than the dislocation density of single crystal layer 10B.
- the threading screw dislocation density of SiC layer 20 may be smaller than the threading screw dislocation density of single crystal layer 10B.
- the threading edge dislocation density of SiC layer 20 may be smaller than the threading edge dislocation density of single crystal layer 10B.
- the basal plane dislocation density of SiC layer 20 may be smaller than the basal plane dislocation density of single crystal layer 10B.
- the mixed dislocation density of SiC layer 20 may be smaller than the mixed dislocation density of single crystal layer 10B.
- the stacking fault density of SiC layer 20 may be smaller than the stacking fault density of single crystal layer 10B.
- the point defect density of SiC layer 20 may be smaller than the point defect density of single crystal layer 10B.
- the defect density such as micropipe density, threading screw dislocation density, threading edge dislocation density, basal plane dislocation density, mixed dislocation density, stacking fault density, point defect density, etc. is compared with the single crystal layer 10B of the base layer 10.
- the IGBT 100 including the high-quality active layer 7 can be obtained.
- a substrate preparation step is first performed as a step (S10).
- base substrate 10 and SiC substrate 20 made of, for example, single crystal silicon carbide and having a p-type conductivity are prepared.
- main surface 20A of SiC substrate 20 is the main surface of silicon carbide substrate 1 obtained by this manufacturing method, and therefore, the plane orientation of main surface 20A of SiC substrate 20 in accordance with the plane orientation of the desired main surface.
- SiC substrate 20 whose main surface is a ⁇ 03-38 ⁇ plane is prepared.
- the base substrate 10 a substrate having a p-type impurity concentration higher than 1 ⁇ 10 18 cm ⁇ 3 is employed.
- the SiC substrate 20 is a substrate having a p-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or less.
- the base substrate 10 and the SiC substrate 20 containing the p-type impurity supply for example, a solid material of Al or a gas material (TMA; Trimethyl Aluminum) as an impurity in crystal growth by sublimation recrystallization based on the modified Rayleigh method. It can produce by slicing the raw material crystal obtained by doing.
- TMA Trimethyl Aluminum
- a substrate flattening step is performed as a step (S20).
- This step (S20) is not an essential step, but can be performed when the flatness of the base substrate 10 or the SiC substrate 20 prepared in the step (S10) is insufficient. Specifically, for example, the main surface of base substrate 10 or SiC substrate 20 is polished.
- the step (S20) may be performed without omitting the step (S20) and polishing the main surfaces of the base substrate 10 and the SiC substrate 20 to be in contact with each other. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced. Further, from the viewpoint of removing the damaged layer near the surface formed by slicing or the like during the production of the base substrate 10 and the SiC substrate 20, for example, the step of removing the damaged layer by etching is replaced with the step (S20). Or after performing after the said process (S20), the process (S30) mentioned later may be implemented.
- step (S30) a stacking step is performed as a step (S30).
- step (S30) referring to FIG. 2, base substrate 10 and SiC substrate 20 are stacked so that their main surfaces 10A and 20B are in contact with each other, and a laminated substrate is manufactured.
- a joining step is performed as a step (S40).
- base substrate 10 and SiC substrate 20 are joined by heating the laminated substrate to a temperature range equal to or higher than the sublimation temperature of silicon carbide, for example.
- silicon carbide substrate 1 including base layer 10 and SiC layer 20 is completed.
- the step (S20) is omitted.
- the substrate 10 and the SiC substrate 20 can be easily joined.
- the laminated substrate may be heated in an atmosphere obtained by reducing the atmospheric pressure. Thereby, the manufacturing cost of silicon carbide substrate 1 can be reduced.
- the heating temperature of the multilayer substrate in the step (S40) is preferably 1800 ° C. or higher and 2500 ° C. or lower.
- the heating temperature is lower than 1800 ° C., it takes a long time to join base substrate 10 and SiC substrate 20, and the manufacturing efficiency of silicon carbide substrate 1 decreases.
- the heating temperature exceeds 2500 ° C., the surfaces of base substrate 10 and SiC substrate 20 are roughened, and there is a risk that the number of crystal defects in silicon carbide substrate 1 to be manufactured increases.
- the heating temperature of the laminated substrate in step (S40) is preferably 1900 ° C. or higher and 2100 ° C. or lower.
- the laminated substrate may be heated under a pressure higher than 10 ⁇ 1 Pa and lower than 10 4 Pa.
- the atmosphere during heating in the step (S40) may be an inert gas atmosphere.
- the said atmosphere is an inert gas atmosphere containing at least 1 selected from the group which consists of argon, helium, and nitrogen.
- this silicon carbide substrate 1 is used, and IGBT100 is manufactured.
- IGBT 100 in the second embodiment basically has the same structure as IGBT 100 of the first embodiment described with reference to FIGS. 1 and 2, and has the same effects.
- IGBT 100 in the second embodiment is different from that in the first embodiment in that SiC layer 20 of silicon carbide substrate 1 has an n-type conductivity by including an n-type impurity. . Therefore, in the operation of IGBT 100 in the present embodiment, base layer 10 performs the same function as silicon carbide substrate 1 in the first embodiment, and SiC layer 20 is the same as part of drift layer 3 in the first embodiment. Fulfills the function.
- the SiC layer 20 functions as a part of the active layer 7.
- the IGBT 100 can be manufactured in the same manner as in the first embodiment, except that the conductivity type of the SiC substrate 20 prepared in the step (S10) is n-type.
- a substrate preparation step is first performed as a step (S10).
- SiC substrate 20 is prepared in the same manner as in the first embodiment, and source substrate 11 made of silicon carbide is prepared.
- This raw material substrate 11 may be made of single crystal silicon carbide, may be made of polycrystalline silicon carbide or porous silicon carbide, and may be a sintered body of silicon carbide. Moreover, it can replace with the raw material board
- the raw material substrate made of polycrystalline silicon carbide can be produced, for example, as follows. First, in a low pressure CVD (Chemical Vapor Deposition) method, a hydrocarbon gas (methane, propane, acetylene, etc.) as a carbon source and a silane gas, silicon tetrachloride, etc. as a silicon source are supplied and heated to about 1300 to 1600 ° C. Polycrystalline silicon carbide is produced on the carbon base material. At this time, an Al raw material (TMA or the like) as an impurity is supplied. And the said raw material board
- a hydrocarbon gas methane, propane, acetylene, etc.
- silicon source are supplied and heated to about 1300 to 1600 ° C.
- Polycrystalline silicon carbide is produced on the carbon base material. At this time, an Al raw material (TMA or the like) as an impurity is supplied
- a base substrate made of a sintered body of silicon carbide can be produced by sintering raw material powder containing a predetermined amount of Al as an impurity.
- a proximity arrangement step is performed as a step (S50).
- SiC substrate 20 and raw material substrate 11 are held by first heater 81 and second heater 82 arranged to face each other.
- the appropriate value of the distance between the SiC substrate 20 and the raw material substrate 11 is related to the average free path of the sublimation gas during heating in the step (S60) described later.
- the average value of the distance between the SiC substrate 20 and the raw material substrate 11 can be set to be smaller than the average free path of the sublimation gas during heating in the step (S60) described later.
- the mean free path of atoms and molecules strictly depends on the atomic radius and molecular radius, but is about several to several tens of centimeters. Is preferably several cm or less. More specifically, SiC substrate 20 and raw material substrate 11 are arranged close to each other with their main surfaces 11A and 20B facing each other with an interval of 1 ⁇ m or more and 1 cm or less. Furthermore, by setting the average value of the intervals to 1 cm or less, the film thickness distribution of the base layer 10 formed in the step (S60) described later can be reduced.
- the sublimation gas is a gas formed by sublimation of solid silicon carbide, and includes, for example, Si, Si 2 C, and SiC 2 .
- a sublimation step is performed as a step (S60).
- SiC substrate 20 is heated to a predetermined substrate temperature by first heater 81.
- the raw material substrate 11 is heated to a predetermined raw material temperature by the second heater 82.
- SiC is sublimated from the surface of the material substrate 11 by heating the material substrate 11 to the material temperature.
- the substrate temperature is set lower than the raw material temperature. Specifically, for example, the substrate temperature is set to be about 1 ° C. or more and 100 ° C. or less lower than the raw material temperature.
- the substrate temperature is, for example, 1800 ° C. or higher and 2500 ° C. or lower.
- SiC that is sublimated from the raw material substrate 11 to become a gas reaches the surface of the SiC substrate 20 and becomes a solid, thereby forming the base layer 10.
- the step (S60) is completed, and silicon carbide substrate 1 shown in FIG. 2 is completed.
- the IGBT in the fourth embodiment basically has the same structure as that in the first embodiment. However, the IGBT of the fourth embodiment is different from that of the first embodiment in its manufacturing method.
- a silicon carbide substrate having a structure different from that in the first embodiment is prepared in the silicon carbide substrate preparing step performed as step (S110).
- step (S110) a silicon carbide substrate having a structure different from that in the first embodiment is prepared in the silicon carbide substrate preparing step performed as step (S110).
- a plurality of SiC layers 20 are arranged side by side in plan view. That is, a plurality of SiC layers 20 are arranged side by side along main surface 10 ⁇ / b> A of base layer 10. More specifically, the plurality of SiC layers 20 are arranged in a matrix so that adjacent SiC layers 20 on base layer 10 are in contact with each other.
- silicon carbide substrate 1 in the present embodiment is silicon carbide substrate 1 that can be handled as a large-diameter substrate having high-quality SiC layer 20. And the manufacturing process of IGBT can be made efficient by using this silicon carbide substrate 1.
- FIG. 13 end surface 20 ⁇ / b> C of adjacent SiC layer 20 is substantially perpendicular to main surface 20 ⁇ / b> A of SiC layer 20.
- silicon carbide substrate 1 of the present embodiment can be easily manufactured.
- the angle formed by the end surface 20C and the main surface 20A is 85 ° or more and 95 ° or less, the end surface 20C and the main surface 20A can be determined to be substantially perpendicular.
- Silicon carbide substrate 1 in the fourth embodiment has a plurality of SiC substrates 20 whose end face 20C is substantially perpendicular to main surface 20A on base substrate 10 in step (S30) in the first embodiment.
- this silicon carbide substrate 1 is used, and IGBT100 is manufactured.
- a plurality of IGBTs 100 are produced by forming the active layer 7 and the like on the SiC layer 20 of the silicon carbide substrate 1 shown in FIG. At this time, each IGBT 100 is fabricated so as not to cross the boundary region between adjacent SiC layers 20.
- Embodiment 5 which is still another embodiment of the present invention will be described.
- the IGBT 100 in the fifth embodiment has basically the same structure as the IGBT 100 in the first embodiment and has the same effects. However, IGBT 100 of the fifth embodiment is different from that of the first embodiment in the structure of silicon carbide substrate 1.
- amorphous SiC layer 40 as an intermediate layer made of amorphous SiC is arranged between base layer 10 and SiC layer 20. ing. Base layer 10 and SiC layer 20 are connected by this amorphous SiC layer 40. Due to the presence of amorphous SiC layer 40, it is possible to easily produce a silicon carbide substrate on which SiC layer 20 is disposed while suppressing the propagation of defects in base layer 10.
- a method for manufacturing silicon carbide substrate 1 in the fifth embodiment will be described. Referring to FIG. 15, in the method for manufacturing silicon carbide substrate 1 in the fifth embodiment, first, a substrate preparation step is performed as in step (S10) in the same manner as in the first embodiment. 20 are prepared.
- a Si layer forming step is performed as a step (S11).
- a Si layer having a thickness of, for example, about 100 nm is formed on one main surface of the base substrate 10 prepared in the step (S10).
- the Si layer can be formed by, for example, a sputtering method.
- step (S30) a lamination step is performed as a step (S30).
- the SiC substrate 20 prepared in step (S10) is placed on the Si layer formed in step (S11).
- a laminated substrate in which the SiC substrate 20 is laminated on the base substrate 10 with the Si layer interposed therebetween is obtained.
- a heating step is performed as a step (S70).
- the laminated substrate produced in the step (S30) is heated to about 1500 ° C. in a mixed gas atmosphere of hydrogen gas and propane gas having a pressure of 1 ⁇ 10 3 Pa, for example, for about 3 hours. Retained.
- carbon is supplied to the Si layer mainly by diffusion from the base substrate 10 and the SiC substrate 20, and an amorphous SiC layer 40 is formed as shown in FIG.
- silicon carbide substrate 1 on which SiC layer 20 is arranged can be easily manufactured while suppressing the propagation of defects in base layer 10.
- Embodiment 6 which is still another embodiment of the present invention will be described.
- the IGBT 100 in the sixth embodiment basically has the same structure as the IGBT 100 in the first embodiment, and has the same effects. However, IGBT 100 of the sixth embodiment is different from that of the first embodiment in the structure of silicon carbide substrate 1.
- silicon carbide substrate 1 in the sixth embodiment an intermediate layer formed by siliciding at least a part of a metal layer between base layer 10 and SiC layer 20 is used.
- This is different from the first embodiment in that the ohmic contact layer 50 is formed.
- Base layer 10 and SiC layer 20 are connected by this ohmic contact layer 50. Due to the presence of the ohmic contact layer 50, silicon carbide substrate 1 on which SiC layer 20 is disposed can be easily fabricated while suppressing the propagation of defects in base layer 10.
- a method for manufacturing silicon carbide substrate 1 in the sixth embodiment will be described. Referring to FIG. 17, in the method for manufacturing silicon carbide substrate 1 in the sixth embodiment, first, a substrate preparation step is performed as in step (S10) in the same manner as in the first embodiment. 20 are prepared.
- a metal film forming step is performed as a step (S12).
- a metal film is formed, for example, by vapor-depositing a metal on one main surface of the base substrate 10 prepared in the step (S10).
- This metal film contains, for example, a metal that forms silicide by being heated, specifically, at least one selected from nickel, molybdenum, titanium, aluminum, and tungsten.
- step (S30) a lamination step is performed as a step (S30).
- SiC substrate 20 prepared in step (S10) is placed on the metal film formed in step (S12).
- a laminated substrate in which the SiC substrate 20 is laminated on the base substrate 10 with the metal film interposed therebetween is obtained.
- a heating step is performed as a step (S70).
- the laminated substrate produced in step (S30) is heated to about 1000 ° C. in an inert gas atmosphere such as argon.
- an inert gas atmosphere such as argon.
- the metal film the region in contact with the base substrate 10 and the region in contact with the SiC substrate 20
- the ohmic contact layer 50 that makes ohmic contact with the base layer 10 and the SiC layer 20 is formed.
- Embodiment 7 which is still another embodiment of the present invention will be described.
- the IGBT 100 in the seventh embodiment has basically the same structure as the IGBT 100 in the first embodiment and has the same effects. However, IGBT 100 of the seventh embodiment is different from that of the first embodiment in the structure of silicon carbide substrate 1.
- the embodiment is that carbon layer 60 as an intermediate layer is formed between base layer 10 and SiC layer 20. This is different from the case of 1. Base layer 10 and SiC layer 20 are connected by this carbon layer 60. Due to the presence of carbon layer 60, silicon carbide substrate 1 on which SiC layer 20 is disposed can be easily fabricated while suppressing the propagation of defects in base layer 10.
- step (S10) is performed in the same manner as in the first embodiment, and then step (S20) is performed in the same manner as in the first embodiment as necessary.
- precursor layer 61 is formed, for example, by applying a carbon adhesive on the main surface of base substrate 10.
- a carbon adhesive what consists of resin, graphite fine particles, and a solvent can be employ
- the resin a resin that becomes non-graphitizable carbon when heated, such as a phenol resin, can be employed.
- the solvent for example, phenol, formaldehyde, ethanol, or the like can be used.
- the coating amount of the carbon adhesive is preferably 10 mg / cm 2 or more and 40 mg / cm 2 or less, and more preferably 20 mg / cm 2 or more and 30 mg / cm 2 or less.
- the thickness of the carbon adhesive to be applied is preferably 100 ⁇ m or less, and more preferably 50 ⁇ m or less.
- a stacking step is performed as a step (S30).
- SiC substrate 20 is placed so as to be in contact with precursor layer 61 formed in contact with the main surface of base substrate 10, and the laminated substrate is Produced.
- a pre-baking step is performed.
- the solvent component is removed from the carbon adhesive constituting the precursor layer 61 by heating the laminated substrate.
- the multilayer substrate is gradually heated to a temperature range exceeding the boiling point of the solvent component while applying a load to the multilayer substrate in the thickness direction. This heating is preferably performed while the base substrate 10 and the SiC substrate 20 are pressure-bonded using a clamp or the like. Further, by performing pre-baking (heating) as much as possible, degassing from the adhesive proceeds, and the strength of bonding can be improved.
- a firing step is performed as a step (S90).
- the laminated substrate heated in step (S80) and pre-baked with precursor layer 61 is heated to a high temperature, preferably 900 ° C. to 1100 ° C., for example 1000 ° C., preferably 10 minutes to 10 minutes.
- the precursor layer 61 is fired by being held for a period of time, for example, 1 hour.
- an atmosphere at the time of firing an inert gas atmosphere such as argon is adopted, and the pressure of the atmosphere can be set to atmospheric pressure, for example.
- the precursor layer 61 becomes the carbon layer 60 made of carbon.
- silicon carbide substrate 1 in the seventh embodiment in which base substrate (base layer) 10 and SiC substrate (SiC layer) 20 are bonded by carbon layer 60 is obtained.
- the crystal structure of silicon carbide constituting SiC layer 20 is preferably a hexagonal system, and more preferably 4H—SiC.
- Base layer 10 and SiC layer 20 are preferably composed of silicon carbide single crystals having the same crystal structure (when there are a plurality of SiC layers 20, the adjacent SiC layers 20 are also adjacent to each other).
- silicon carbide single crystal having the same crystal structure for base layer 10 and SiC layer 20 physical properties such as a thermal expansion coefficient are unified, and silicon carbide substrate 1 and silicon carbide substrate 1 are formed.
- warpage of silicon carbide substrate 1, separation between base layer 10 and SiC layer 20, or separation between SiC layers 20 can be suppressed.
- the angle formed by the c-axis of the silicon carbide single crystal constituting each is less than 1 °. It is preferable that the angle is less than 0.1 °. Furthermore, it is preferable that the c-plane of the silicon carbide single crystal is not rotated in the plane.
- the diameter of the base layer (base substrate) 10 of the silicon carbide substrate 1 used for manufacturing the IGBT is preferably 2 inches or more, and more preferably 6 inches or more.
- the thickness of silicon carbide substrate 1 is preferably 200 ⁇ m or more and 1000 ⁇ m or less, and more preferably 300 ⁇ m or more and 700 ⁇ m or less.
- the resistivity of SiC layer 20 is preferably 50 m ⁇ cm or less, and more preferably 20 m ⁇ cm or less.
- Example 1 will be described below. The calculation which estimates the reduction effect of the resistance of the silicon carbide substrate which comprises IGBT of this invention was implemented. Specifically, a base layer 10 having a thickness of 200 ⁇ m and a p-type impurity density of 1 ⁇ 10 20 cm ⁇ 3 corresponding to the first embodiment, and an SiC layer having a thickness of 200 ⁇ m and a p-type impurity density of 1 ⁇ 10 18 cm ⁇ 3 . Substrate resistance (the sum of the resistance of base layer 10 and the resistance of SiC layer 20) (Example A), and a thickness of 400 ⁇ m and p-type impurity density 1 corresponding to Embodiment 2 above.
- the resistance (substrate resistance) (Example B) of the base layer 10 of ⁇ 10 20 cm ⁇ 3 was calculated.
- the resistance (substrate resistance) (Comparative Example A) of a silicon carbide substrate having a thickness of 400 ⁇ m and a p-type impurity density of 1 ⁇ 10 18 cm ⁇ 3 corresponding to a silicon carbide substrate constituting a conventional IGBT was calculated for comparison. .
- the calculation was performed as follows.
- the substrate resistance of Example A corresponding to Embodiment 1 can be reduced by about 36% compared to the conventional Comparative Example A. Further, the substrate resistance of Example B corresponding to the second embodiment can be reduced by about 77% compared to the conventional Comparative Example A. As described above, according to the IGBT of the present invention, it was confirmed that the substrate resistance can be significantly reduced as compared with the conventional case.
- Example 2 Next, Example 2 will be described.
- the calculation which estimates the reduction effect of the contact resistance of the collector electrode (back surface electrode) and silicon carbide substrate in IGBT of this invention was implemented.
- (1) Use a metal with a large work function ⁇ to lower the Schottky barrier.
- (2) Increase the impurity density of the semiconductor to reduce the depletion layer width, thereby reducing the Schottky barrier. Conceivable.
- the IGBT of the present invention that employs a silicon carbide substrate including a base layer having a high impurity concentration, calculation results regarding the contact resistance between the electrode and the base layer will be described.
- the contact resistance R c depends exponentially on ⁇ bn / N d 1/2 . Then, by raising the impurity concentration (impurity concentration) N d, it is possible to reduce the contact resistance R c.
- the contact resistance (Example C) between the substrate (base layer) and the electrode having a p-type impurity concentration of 1 ⁇ 10 20 cm ⁇ 3 assuming the IGBT of the present invention and the conventional IGBT was assumed.
- the contact resistance (Comparative Example B) between the substrate and the electrode having a p-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 was calculated.
- Al aluminum
- the calculation results are shown in Table 2.
- the contact resistance in Example C assuming the IGBT of the present invention is reduced by about 70% with respect to the contact resistance in Comparative Example B assuming the conventional IGBT.
- heat treatment is often performed after electrode formation for the purpose of reducing the contact resistance.
- the heat treatment is omitted or the heat treatment temperature, which is usually about 1000 ° C., is greatly increased. There is a possibility that it can be lowered.
- the IGBT of the present invention can be particularly advantageously applied to a vertical IGBT that requires a reduction in on-resistance.
- base substrate base substrate
- 10A main surface, 10B single crystal Layer 11 material substrate, 11A main surface, 20 SiC layer (SiC substrate), 20A, 20B main surface, 20C end surface, 40 amorphous SiC layer, 50 ohmic contact layer, 60 carbon layer, 61 precursor layer, 81 first heater , 82
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
まず、本発明の一実施の形態である実施の形態1について説明する。図1を参照して、本実施の形態における絶縁ゲート型バイポーラトランジスタであるIGBT100は、導電型がp型である炭化珪素基板1と、バッファ層2(導電型はn型でもp型でもよい)と、炭化珪素からなり導電型がn型のドリフト層3と、導電型がp型の一対のウェル領域4と、導電型がn型のエミッタ領域としてのn+領域5と、導電型がp型の高濃度p型領域としてのp+領域6とを備えている。
次に、本発明の他の実施の形態である実施の形態2について説明する。図8を参照して、実施の形態2におけるIGBT100は、基本的には図1および図2に基づいて説明した実施の形態1のIGBT100と同様の構造を有し、同様の効果を奏する。しかし、実施の形態2におけるIGBT100では、炭化珪素基板1のSiC層20が、n型不純物を含むことにより導電型がn型となっている点において、実施の形態1の場合とは異なっている。そのため、本実施の形態におけるIGBT100の動作においては、ベース層10が実施の形態1における炭化珪素基板1と同様の機能を果たし、SiC層20が実施の形態1におけるドリフト層3の一部と同様の機能を果たす。すなわち、SiC層20は、活性層7の一部として機能する。また、上記IGBT100は、上記工程(S10)において準備されるSiC基板20の導電型がn型であることを除き、実施の形態1の場合と同様に製造することができる。
次に、実施の形態3として、本発明のIGBTを構成する炭化珪素基板の他の製造方法について、図9~図12を参照して説明する。実施の形態3における炭化珪素基板の製造方法は、基本的には上記実施の形態1の場合と同様に実施される。しかし、実施の形態3における炭化珪素基板の製造方法は、ベース層10の形成プロセスにおいて実施の形態1の場合とは異なっている。
次に、本発明のさらに他の実施の形態である実施の形態4について説明する。実施の形態4におけるIGBTは、基本的には実施の形態1と同様の構造を有している。しかし、実施の形態4のIGBTは、その製造方法において実施の形態1の場合とは異なっている。
次に、本発明のさらに他の実施の形態である実施の形態5について説明する。実施の形態5におけるIGBT100は、基本的には実施の形態1におけるIGBT100と同様の構造を有し、同様の効果を奏する。しかし、実施の形態5のIGBT100は、炭化珪素基板1の構造において実施の形態1の場合とは異なっている。
次に、本発明のさらに他の実施の形態である実施の形態6について説明する。実施の形態6におけるIGBT100は、基本的には実施の形態1におけるIGBT100と同様の構造を有し、同様の効果を奏する。しかし、実施の形態6のIGBT100は、炭化珪素基板1の構造において実施の形態1の場合とは異なっている。
次に、本発明のさらに他の実施の形態である実施の形態7について説明する。実施の形態7におけるIGBT100は、基本的には実施の形態1におけるIGBT100と同様の構造を有し、同様の効果を奏する。しかし、実施の形態7のIGBT100は、炭化珪素基板1の構造において実施の形態1の場合とは異なっている。
以下、実施例1について説明する。本発明のIGBTを構成する炭化珪素基板の抵抗の低減効果を見積もる計算を実施した。具体的には、上記実施の形態1に対応する厚み200μm、p型不純物密度1×1020cm-3のベース層10と、厚み200μm、p型不純物密度1×1018cm-3のSiC層20とを含む炭化珪素基板1における基板抵抗(ベース層10の抵抗とSiC層20の抵抗との和)(実施例A)と、上記実施の形態2に対応する厚み400μm、p型不純物密度1×1020cm-3のベース層10の抵抗(基板抵抗)(実施例B)とを算出した。また、従来のIGBTを構成する炭化珪素基板に対応する厚み400μm、p型不純物密度1×1018cm-3の炭化珪素基板の抵抗(基板抵抗)(比較例A)を比較のために算出した。算出は以下のように行なった。
次に、実施例2について説明する。本発明のIGBTにおけるコレクタ電極(裏面電極)と炭化珪素基板との接触抵抗の低減効果を見積もる計算を実施した。ここで、金属である電極とp型半導体である炭化珪素基板との接触抵抗を低減し、オーミックコンタクトを得るためには、
(1)仕事関数Φの大きい金属を採用してショットキー障壁を低くする
(2)半導体の不純物密度を高くして空乏層幅を小さくすることにより、ショットキー障壁を薄くする
という2つの方策が考えられる。しかし、実際には(1)の方策を採用することは容易ではなく、(2)の方策を採用してトンネル電流を増大させ、オーミックコンタクトを得る方策が有効である。以下、高い不純物濃度を有するベース層を含む炭化珪素基板を採用した本発明のIGBTを想定し、電極とベース層との接触抵抗に関する計算結果について説明する。
Claims (15)
- 炭化珪素基板(1)と、
単結晶炭化珪素からなり、前記炭化珪素基板(1)の一方の主面上に配置された導電型がn型のドリフト層(3)と、
前記ドリフト層(3)において前記炭化珪素基板(1)とは反対側の第1主面(3A)を含むように配置された導電型がp型のウェル領域(4)と、
前記ウェル領域(4)内の前記第1主面(3A)を含むように配置された導電型がn型のエミッタ領域(5)と、
前記エミッタ領域(5)に接触するように、前記第1主面(3A)上に配置されたエミッタ電極(92)と、
絶縁体からなり、前記第1主面(3A)上に前記ウェル領域(4)に接触するように配置された絶縁膜(91)と、
前記絶縁膜(91)上に配置されたゲート電極(93)と、
前記炭化珪素基板(1)の他方の主面上に配置されたコレクタ電極(96)とを備え、
前記炭化珪素基板(1)は、
炭化珪素からなり、導電型がp型であるベース層(10)と、
単結晶炭化珪素からなり、前記ベース層(10)上に配置されたSiC層(20)とを含み、
前記ベース層(10)のp型不純物濃度は1×1018cm-3を超えている、絶縁ゲート型バイポーラトランジスタ(100)。 - 前記ベース層(10)には、不純物としてアルミニウムが導入されている、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記SiC層(20)は、導電型がp型であり、不純物濃度が1×1018cm-3以下となっている、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記SiC層(20)の、前記ベース層(10)とは反対側の主面(20A)は、{0001}面に対するオフ角が50°以上65°以下となっている、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記SiC層(20)の、前記ベース層(10)とは反対側の主面(20A)のオフ方位と<1-100>方向とのなす角は5°以下となっている、請求の範囲第4項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記SiC層(20)の、前記ベース層(10)とは反対側の主面(20A)の、<1-100>方向における{03-38}面に対するオフ角は-3°以上5°以下である、請求の範囲第5項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記SiC層(20)の、前記ベース層(10)とは反対側の主面(20A)のオフ方位と<11-20>方向とのなす角は5°以下となっている、請求の範囲第4項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記炭化珪素基板は(1)、前記ベース層(10)と前記SiC層(20)との間に配置され、導電体または半導体からなる中間層(40,50,60)をさらに含み、
前記中間層(40,50,60)は、前記ベース層(10)と前記SiC層(20)とを接合している、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。 - 前記中間層(50)は金属からなっている、請求の範囲第8項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記中間層は炭素(60)からなっている、請求の範囲第8項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記中間層は非晶質炭化珪素(40)からなっている、請求の範囲第8項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
- 前記ベース層(10)は単結晶炭化珪素からなり、
前記SiC層(20)のX線ロッキングカーブの半値幅は、前記ベース層(10)のX線ロッキングカーブの半値幅よりも小さくなっている、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。 - 前記ベース層(10)は単結晶炭化珪素からなり、
前記SiC層(20)のマイクロパイプ密度は、前記ベース層(10)のマイクロパイプ密度よりも低い、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。 - 前記ベース層(10)は単結晶炭化珪素からなり、
前記SiC層(20)の転位密度は、前記ベース層(10)の転位密度よりも低い、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。 - 前記ベース層(10)は、前記SiC層(20)に対向する側の主面(10A)を含むように単結晶炭化珪素からなる単結晶層(10B)を含んでいる、請求の範囲第1項に記載の絶縁ゲート型バイポーラトランジスタ(100)。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP10774831A EP2432022A1 (en) | 2009-05-11 | 2010-04-27 | Insulating gate type bipolar transistor |
US13/320,243 US20120056201A1 (en) | 2009-05-11 | 2010-04-27 | Insulated gate bipolar transistor |
JP2011513304A JPWO2010131573A1 (ja) | 2009-05-11 | 2010-04-27 | 絶縁ゲート型バイポーラトランジスタ |
KR1020117028517A KR20120011059A (ko) | 2009-05-11 | 2010-04-27 | 절연 게이트형 바이폴러 트랜지스터 |
CA2761246A CA2761246A1 (en) | 2009-05-11 | 2010-04-27 | Insulated gate bipolar transistor |
CN2010800206964A CN102422425A (zh) | 2009-05-11 | 2010-04-27 | 绝缘栅双极晶体管 |
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-114737 | 2009-05-11 | ||
JP2009114737 | 2009-05-11 | ||
JP2009-219065 | 2009-09-24 | ||
JP2009219065 | 2009-09-24 | ||
JP2009229764 | 2009-10-01 | ||
JP2009-229764 | 2009-10-01 | ||
JP2009248621 | 2009-10-29 | ||
JP2009-248621 | 2009-10-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010131573A1 true WO2010131573A1 (ja) | 2010-11-18 |
Family
ID=43084945
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057442 WO2010131570A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板および半導体装置 |
PCT/JP2010/057444 WO2010131572A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体装置 |
PCT/JP2010/057445 WO2010131573A1 (ja) | 2009-05-11 | 2010-04-27 | 絶縁ゲート型バイポーラトランジスタ |
PCT/JP2010/057441 WO2010131569A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体基板の製造方法 |
PCT/JP2010/057439 WO2010131568A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057442 WO2010131570A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板および半導体装置 |
PCT/JP2010/057444 WO2010131572A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体装置 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/057441 WO2010131569A1 (ja) | 2009-05-11 | 2010-04-27 | 半導体基板の製造方法 |
PCT/JP2010/057439 WO2010131568A1 (ja) | 2009-05-11 | 2010-04-27 | 炭化珪素基板、半導体装置および炭化珪素基板の製造方法 |
Country Status (8)
Country | Link |
---|---|
US (5) | US8168515B2 (ja) |
EP (5) | EP2432020A4 (ja) |
JP (5) | JP5344037B2 (ja) |
KR (5) | KR20120014024A (ja) |
CN (5) | CN102422388A (ja) |
CA (5) | CA2761430A1 (ja) |
TW (5) | TW201104861A (ja) |
WO (5) | WO2010131570A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8168515B2 (en) | 2009-05-11 | 2012-05-01 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor substrate |
WO2021005903A1 (ja) * | 2019-07-11 | 2021-01-14 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG183740A1 (en) * | 2009-02-20 | 2012-09-27 | Semiconductor Energy Lab | Semiconductor device and manufacturing method of the same |
CN102379026A (zh) * | 2009-11-13 | 2012-03-14 | 住友电气工业株式会社 | 用于制造半导体衬底的方法 |
US8435866B2 (en) * | 2010-02-05 | 2013-05-07 | Sumitomo Electric Industries, Ltd. | Method for manufacturing silicon carbide substrate |
JP2011246315A (ja) * | 2010-05-28 | 2011-12-08 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
JP5447206B2 (ja) * | 2010-06-15 | 2014-03-19 | 住友電気工業株式会社 | 炭化珪素単結晶の製造方法および炭化珪素基板 |
DE112011105073T5 (de) * | 2011-03-22 | 2013-12-24 | Sumitomo Electric Industries, Ltd. | Siliziumkarbidsubstrat |
JP2012201543A (ja) * | 2011-03-25 | 2012-10-22 | Sumitomo Electric Ind Ltd | 炭化珪素基板 |
JP2013018693A (ja) * | 2011-06-16 | 2013-01-31 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
CN105755534B (zh) * | 2011-08-05 | 2019-01-08 | 住友电气工业株式会社 | 衬底、半导体器件及其制造方法 |
JPWO2013073216A1 (ja) * | 2011-11-14 | 2015-04-02 | 住友電気工業株式会社 | 炭化珪素基板、半導体装置およびこれらの製造方法 |
KR101984698B1 (ko) * | 2012-01-11 | 2019-05-31 | 삼성전자주식회사 | 기판 구조체, 이로부터 제조된 반도체소자 및 그 제조방법 |
JP6119100B2 (ja) | 2012-02-01 | 2017-04-26 | 住友電気工業株式会社 | 炭化珪素半導体装置 |
TWI456737B (zh) * | 2012-03-05 | 2014-10-11 | Richtek Technology Corp | 垂直式半導體元件及其製造方法 |
CN103325747A (zh) * | 2012-03-19 | 2013-09-25 | 立锜科技股份有限公司 | 垂直式半导体元件及其制造方法 |
JP5884585B2 (ja) | 2012-03-21 | 2016-03-15 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
US9466552B2 (en) * | 2012-03-30 | 2016-10-11 | Richtek Technology Corporation | Vertical semiconductor device having a non-conductive substrate and a gallium nitride layer |
KR101386119B1 (ko) * | 2012-07-26 | 2014-04-21 | 한국전기연구원 | SiC MOSFET의 오믹 접합 형성방법 |
US9184229B2 (en) * | 2012-07-31 | 2015-11-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
US8860040B2 (en) | 2012-09-11 | 2014-10-14 | Dow Corning Corporation | High voltage power semiconductor devices on SiC |
US9018639B2 (en) | 2012-10-26 | 2015-04-28 | Dow Corning Corporation | Flat SiC semiconductor substrate |
US9017804B2 (en) | 2013-02-05 | 2015-04-28 | Dow Corning Corporation | Method to reduce dislocations in SiC crystal growth |
US9797064B2 (en) | 2013-02-05 | 2017-10-24 | Dow Corning Corporation | Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a support shelf which permits thermal expansion |
US9738991B2 (en) | 2013-02-05 | 2017-08-22 | Dow Corning Corporation | Method for growing a SiC crystal by vapor deposition onto a seed crystal provided on a supporting shelf which permits thermal expansion |
JP6297783B2 (ja) * | 2013-03-08 | 2018-03-20 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
US8940614B2 (en) | 2013-03-15 | 2015-01-27 | Dow Corning Corporation | SiC substrate with SiC epitaxial film |
JP6119564B2 (ja) | 2013-11-08 | 2017-04-26 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
JP6356428B2 (ja) * | 2014-02-17 | 2018-07-11 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN103855206A (zh) * | 2014-02-18 | 2014-06-11 | 宁波达新半导体有限公司 | 绝缘栅双极晶体管及其制造方法 |
JP2015176995A (ja) * | 2014-03-14 | 2015-10-05 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP6180978B2 (ja) * | 2014-03-20 | 2017-08-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
US9279192B2 (en) | 2014-07-29 | 2016-03-08 | Dow Corning Corporation | Method for manufacturing SiC wafer fit for integration with power device manufacturing technology |
CN107078032A (zh) * | 2014-10-14 | 2017-08-18 | 三菱电机株式会社 | 碳化硅外延晶片的制造方法 |
CN104465721B (zh) * | 2014-12-05 | 2019-05-14 | 国家电网公司 | 一种碳化硅外延材料及其制备方法 |
JP2017059600A (ja) | 2015-09-14 | 2017-03-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
US10490634B2 (en) * | 2015-11-24 | 2019-11-26 | Sumitomo Electric Industries, Ltd. | Silicon carbide epitaxial substrate having a silicon carbide layer and method of manufacturing silicon carbide semiconductor device |
CN105679647B (zh) * | 2015-12-31 | 2018-06-29 | 清华大学 | 具有原子级平整表面的衬底的制备方法 |
JP6271104B1 (ja) * | 2016-07-21 | 2018-01-31 | 三菱電機株式会社 | 炭化珪素半導体装置、および、炭化珪素半導体装置の製造方法 |
JP6703915B2 (ja) * | 2016-07-29 | 2020-06-03 | 富士電機株式会社 | 炭化珪素半導体基板、炭化珪素半導体基板の製造方法、半導体装置および半導体装置の製造方法 |
KR101866869B1 (ko) * | 2016-08-18 | 2018-06-14 | 주식회사 티씨케이 | SiC 소재 및 SiC 복합 소재 |
US10825903B2 (en) * | 2017-01-31 | 2020-11-03 | Sumitomo Electric Industries, Ltd. | Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device |
CN110214363B (zh) * | 2017-01-31 | 2023-07-28 | 住友电气工业株式会社 | 碳化硅外延衬底和制造碳化硅半导体器件的方法 |
JP6883745B2 (ja) * | 2017-03-24 | 2021-06-09 | パナソニックIpマネジメント株式会社 | 半導体装置およびその製造方法 |
US11233141B2 (en) | 2018-01-16 | 2022-01-25 | Ipower Semiconductor | Self-aligned and robust IGBT devices |
US20190245070A1 (en) * | 2018-02-07 | 2019-08-08 | Ipower Semiconductor | Igbt devices with 3d backside structures for field stop and reverse conduction |
KR102649978B1 (ko) | 2018-05-03 | 2024-03-22 | 엘지전자 주식회사 | 정수기의 제어 방법 |
EP3666935B1 (en) * | 2018-10-16 | 2024-05-22 | Sicc Co., Ltd. | High-purity silicon carbide single crystal substrate and preparation method therefor |
JP7143769B2 (ja) * | 2019-01-10 | 2022-09-29 | 三菱電機株式会社 | 炭化珪素半導体基板の製造方法及び炭化珪素半導体装置の製造方法 |
WO2021092862A1 (zh) * | 2019-11-14 | 2021-05-20 | 华为技术有限公司 | 半导体衬底及其制造方法、半导体器件 |
CN113981537A (zh) * | 2020-07-27 | 2022-01-28 | 环球晶圆股份有限公司 | 碳化硅晶种及其制造方法、碳化硅晶体的制造方法 |
TWI831512B (zh) * | 2022-12-09 | 2024-02-01 | 鴻揚半導體股份有限公司 | 半導體裝置和其形成方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223835A (ja) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH113842A (ja) * | 1997-06-11 | 1999-01-06 | Nippon Pillar Packing Co Ltd | 半導体電子素子用基板およびその製造方法 |
JPH1187200A (ja) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | 半導体基板及び半導体装置の製造方法 |
WO2001018872A1 (fr) * | 1999-09-07 | 2001-03-15 | Sixon Inc. | TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC |
JP2002280531A (ja) * | 2001-03-19 | 2002-09-27 | Denso Corp | 半導体基板及びその製造方法 |
JP2006228961A (ja) * | 2005-02-17 | 2006-08-31 | Toyota Central Res & Dev Lab Inc | 半導体装置 |
WO2006114999A1 (ja) * | 2005-04-18 | 2006-11-02 | Kyoto University | 化合物半導体装置及び化合物半導体製造方法 |
WO2008111269A1 (ja) * | 2007-03-09 | 2008-09-18 | Sumitomo Electric Industries, Ltd. | 第1電極と第2電極とを備える半導体装置およびその製造方法 |
Family Cites Families (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637276B2 (ja) * | 1988-01-18 | 1994-05-18 | 株式会社豊田自動織機製作所 | 上下移動機構付プッシャー装置 |
JP2846986B2 (ja) | 1991-10-30 | 1999-01-13 | 三菱マテリアル株式会社 | 半導体ウェーハの製造方法 |
JPH0748198A (ja) * | 1993-08-05 | 1995-02-21 | Sumitomo Electric Ind Ltd | ダイヤモンドの合成法 |
EP0922792A4 (en) * | 1997-06-27 | 2000-08-16 | Nippon Pillar Packing | SINGLE CRYSTAL SIC AND PROCESS FOR PREPARING THE SIC |
JP3254559B2 (ja) * | 1997-07-04 | 2002-02-12 | 日本ピラー工業株式会社 | 単結晶SiCおよびその製造方法 |
JP2939615B2 (ja) | 1998-02-04 | 1999-08-25 | 日本ピラー工業株式会社 | 単結晶SiC及びその製造方法 |
US6246076B1 (en) * | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
JP2000277405A (ja) * | 1999-03-29 | 2000-10-06 | Meidensha Corp | 半導体素子の製造方法 |
JP2002015619A (ja) | 2000-06-29 | 2002-01-18 | Kyocera Corp | 導電性材及びそれを用いた耐プラズマ部材及び半導体製造用装置 |
JP4843854B2 (ja) * | 2001-03-05 | 2011-12-21 | 住友電気工業株式会社 | Mosデバイス |
US6909119B2 (en) * | 2001-03-15 | 2005-06-21 | Cree, Inc. | Low temperature formation of backside ohmic contacts for vertical devices |
DE10247017B4 (de) * | 2001-10-12 | 2009-06-10 | Denso Corp., Kariya-shi | SiC-Einkristall, Verfahren zur Herstellung eines SiC-Einkristalls, SiC-Wafer mit einem Epitaxiefilm und Verfahren zur Herstellung eines SiC-Wafers, der einen Epitaxiefilm aufweist |
JP3559971B2 (ja) * | 2001-12-11 | 2004-09-02 | 日産自動車株式会社 | 炭化珪素半導体装置およびその製造方法 |
FR2834123B1 (fr) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report |
US6562127B1 (en) * | 2002-01-16 | 2003-05-13 | The United States Of America As Represented By The Secretary Of The Navy | Method of making mosaic array of thin semiconductor material of large substrates |
US8080826B1 (en) * | 2002-02-14 | 2011-12-20 | Rf Micro Devices, Inc. | High performance active and passive structures based on silicon material bonded to silicon carbide |
US20040144301A1 (en) * | 2003-01-24 | 2004-07-29 | Neudeck Philip G. | Method for growth of bulk crystals by vapor phase epitaxy |
JP5160032B2 (ja) * | 2003-01-28 | 2013-03-13 | 住友電気工業株式会社 | ダイヤモンド複合基板及びその製造方法 |
US7321142B2 (en) * | 2003-06-13 | 2008-01-22 | Sumitomo Electric Industries, Ltd. | Field effect transistor |
JP4238357B2 (ja) | 2003-08-19 | 2009-03-18 | 独立行政法人産業技術総合研究所 | 炭化珪素エピタキシャルウエハ、同ウエハの製造方法及び同ウエハ上に作製された半導体装置 |
JP4219800B2 (ja) | 2003-12-22 | 2009-02-04 | 株式会社豊田中央研究所 | SiC単結晶の製造方法 |
CN100433256C (zh) * | 2004-03-18 | 2008-11-12 | 克里公司 | 减少堆垛层错成核位置的顺序光刻方法和具有减少的堆垛层错成核位置的结构 |
JP4874527B2 (ja) | 2004-04-01 | 2012-02-15 | トヨタ自動車株式会社 | 炭化珪素半導体基板及びその製造方法 |
JP4442366B2 (ja) | 2004-08-27 | 2010-03-31 | 住友電気工業株式会社 | エピタキシャルSiC膜とその製造方法およびSiC半導体デバイス |
JP4733485B2 (ja) * | 2004-09-24 | 2011-07-27 | 昭和電工株式会社 | 炭化珪素単結晶成長用種結晶の製造方法、炭化珪素単結晶成長用種結晶、炭化珪素単結晶の製造方法、および炭化珪素単結晶 |
US7314520B2 (en) * | 2004-10-04 | 2008-01-01 | Cree, Inc. | Low 1c screw dislocation 3 inch silicon carbide wafer |
JP4775102B2 (ja) * | 2005-05-09 | 2011-09-21 | 住友電気工業株式会社 | 半導体装置の製造方法 |
US7391058B2 (en) * | 2005-06-27 | 2008-06-24 | General Electric Company | Semiconductor devices and methods of making same |
JP2008004726A (ja) | 2006-06-22 | 2008-01-10 | Matsushita Electric Ind Co Ltd | 半導体素子およびその製造方法 |
JP4916247B2 (ja) * | 2006-08-08 | 2012-04-11 | トヨタ自動車株式会社 | 炭化珪素半導体装置及びその製造方法 |
CN100438083C (zh) * | 2006-12-23 | 2008-11-26 | 厦门大学 | δ掺杂4H-SiC PIN结构紫外光电探测器及其制备方法 |
JP4748067B2 (ja) | 2007-01-15 | 2011-08-17 | 株式会社デンソー | 炭化珪素単結晶の製造方法および製造装置 |
JP2008235776A (ja) | 2007-03-23 | 2008-10-02 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US7718519B2 (en) * | 2007-03-29 | 2010-05-18 | Panasonic Corporation | Method for manufacturing silicon carbide semiconductor element |
JP4348408B2 (ja) * | 2007-03-29 | 2009-10-21 | パナソニック株式会社 | 半導体装置の製造方法 |
FR2914488B1 (fr) * | 2007-03-30 | 2010-08-27 | Soitec Silicon On Insulator | Substrat chauffage dope |
JP2008280207A (ja) | 2007-05-10 | 2008-11-20 | Matsushita Electric Ind Co Ltd | SiC単結晶基板の製造方法 |
JP2009117533A (ja) * | 2007-11-05 | 2009-05-28 | Shin Etsu Chem Co Ltd | 炭化珪素基板の製造方法 |
JP5157843B2 (ja) * | 2007-12-04 | 2013-03-06 | 住友電気工業株式会社 | 炭化ケイ素半導体装置およびその製造方法 |
JP5504597B2 (ja) * | 2007-12-11 | 2014-05-28 | 住友電気工業株式会社 | 炭化ケイ素半導体装置およびその製造方法 |
JP2010184833A (ja) * | 2009-02-12 | 2010-08-26 | Denso Corp | 炭化珪素単結晶基板および炭化珪素単結晶エピタキシャルウェハ |
JPWO2010131571A1 (ja) | 2009-05-11 | 2012-11-01 | 住友電気工業株式会社 | 半導体装置 |
KR20120014024A (ko) | 2009-05-11 | 2012-02-15 | 스미토모덴키고교가부시키가이샤 | 탄화규소 기판 및 반도체 장치 |
JPWO2011037079A1 (ja) | 2009-09-24 | 2013-02-21 | 住友電気工業株式会社 | 炭化珪素インゴット、炭化珪素基板、それらの製造方法、坩堝、および半導体基板 |
US20110221039A1 (en) * | 2010-03-12 | 2011-09-15 | Sinmat, Inc. | Defect capping for reduced defect density epitaxial articles |
JP2011233638A (ja) * | 2010-04-26 | 2011-11-17 | Sumitomo Electric Ind Ltd | 炭化珪素基板およびその製造方法 |
JP2011243848A (ja) * | 2010-05-20 | 2011-12-01 | Sumitomo Electric Ind Ltd | 炭化珪素基板の製造方法 |
JP2011256053A (ja) * | 2010-06-04 | 2011-12-22 | Sumitomo Electric Ind Ltd | 複合基板およびその製造方法 |
-
2010
- 2010-04-27 KR KR1020117028915A patent/KR20120014024A/ko not_active Application Discontinuation
- 2010-04-27 WO PCT/JP2010/057442 patent/WO2010131570A1/ja active Application Filing
- 2010-04-27 EP EP10774830.3A patent/EP2432020A4/en not_active Withdrawn
- 2010-04-27 TW TW099113382A patent/TW201104861A/zh unknown
- 2010-04-27 EP EP10774826A patent/EP2432000A4/en not_active Withdrawn
- 2010-04-27 KR KR1020117028635A patent/KR20120014017A/ko not_active Application Discontinuation
- 2010-04-27 TW TW099113383A patent/TW201101482A/zh unknown
- 2010-04-27 TW TW099113381A patent/TW201101484A/zh unknown
- 2010-04-27 KR KR1020117005798A patent/KR20120024526A/ko not_active Application Discontinuation
- 2010-04-27 US US13/062,057 patent/US8168515B2/en not_active Expired - Fee Related
- 2010-04-27 CA CA2761430A patent/CA2761430A1/en not_active Abandoned
- 2010-04-27 JP JP2011513301A patent/JP5344037B2/ja not_active Expired - Fee Related
- 2010-04-27 US US13/320,243 patent/US20120056201A1/en not_active Abandoned
- 2010-04-27 WO PCT/JP2010/057444 patent/WO2010131572A1/ja active Application Filing
- 2010-04-27 US US13/319,560 patent/US20120061686A1/en not_active Abandoned
- 2010-04-27 JP JP2011513304A patent/JPWO2010131573A1/ja not_active Withdrawn
- 2010-04-27 CN CN2010800205196A patent/CN102422388A/zh active Pending
- 2010-04-27 CA CA2761245A patent/CA2761245A1/en not_active Abandoned
- 2010-04-27 CN CN2010800205020A patent/CN102422424A/zh active Pending
- 2010-04-27 KR KR1020117028245A patent/KR20120023710A/ko not_active Application Discontinuation
- 2010-04-27 EP EP10774827A patent/EP2432001A4/en not_active Ceased
- 2010-04-27 CA CA2761428A patent/CA2761428A1/en not_active Abandoned
- 2010-04-27 CN CN2010800205181A patent/CN102422387A/zh active Pending
- 2010-04-27 US US13/320,247 patent/US20120056202A1/en not_active Abandoned
- 2010-04-27 CN CN2010800026675A patent/CN102160143B/zh not_active Expired - Fee Related
- 2010-04-27 EP EP10774828A patent/EP2432002A4/en not_active Withdrawn
- 2010-04-27 CA CA2735975A patent/CA2735975A1/en not_active Abandoned
- 2010-04-27 CN CN2010800206964A patent/CN102422425A/zh active Pending
- 2010-04-27 JP JP2011513303A patent/JPWO2010131572A1/ja not_active Withdrawn
- 2010-04-27 CA CA2761246A patent/CA2761246A1/en not_active Abandoned
- 2010-04-27 WO PCT/JP2010/057445 patent/WO2010131573A1/ja active Application Filing
- 2010-04-27 KR KR1020117028517A patent/KR20120011059A/ko not_active Application Discontinuation
- 2010-04-27 TW TW099113377A patent/TW201104865A/zh unknown
- 2010-04-27 TW TW099113380A patent/TW201120939A/zh unknown
- 2010-04-27 WO PCT/JP2010/057441 patent/WO2010131569A1/ja active Application Filing
- 2010-04-27 JP JP2011513300A patent/JP5477380B2/ja not_active Expired - Fee Related
- 2010-04-27 EP EP10774831A patent/EP2432022A1/en not_active Withdrawn
- 2010-04-27 WO PCT/JP2010/057439 patent/WO2010131568A1/ja active Application Filing
- 2010-04-27 US US13/319,599 patent/US20120061687A1/en not_active Abandoned
- 2010-04-27 JP JP2011513299A patent/JPWO2010131568A1/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223835A (ja) * | 1997-02-05 | 1998-08-21 | Hitachi Ltd | 半導体装置とその製造方法 |
JPH113842A (ja) * | 1997-06-11 | 1999-01-06 | Nippon Pillar Packing Co Ltd | 半導体電子素子用基板およびその製造方法 |
JPH1187200A (ja) * | 1997-09-05 | 1999-03-30 | Toshiba Corp | 半導体基板及び半導体装置の製造方法 |
WO2001018872A1 (fr) * | 1999-09-07 | 2001-03-15 | Sixon Inc. | TRANCHE DE SiC, DISPOSITIF A SEMI-CONDUCTEUR DE SiC, ET PROCEDE DE PRODUCTION D'UNE TRANCHE DE SiC |
JP2002280531A (ja) * | 2001-03-19 | 2002-09-27 | Denso Corp | 半導体基板及びその製造方法 |
JP2006228961A (ja) * | 2005-02-17 | 2006-08-31 | Toyota Central Res & Dev Lab Inc | 半導体装置 |
WO2006114999A1 (ja) * | 2005-04-18 | 2006-11-02 | Kyoto University | 化合物半導体装置及び化合物半導体製造方法 |
WO2008111269A1 (ja) * | 2007-03-09 | 2008-09-18 | Sumitomo Electric Industries, Ltd. | 第1電極と第2電極とを備える半導体装置およびその製造方法 |
Non-Patent Citations (2)
Title |
---|
R. C. GLASS ET AL.: "SiC Seeded Crystal Growth", PHYS. STAT. SOL .(B, vol. 202, 1997, pages 149 - 162 |
R. C. GLASS ET AL.: "SiC Seeded Crystal Growth", PHYS. STAT. SOL. (B, vol. 202, 1997, pages 149 - 162 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8168515B2 (en) | 2009-05-11 | 2012-05-01 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor substrate |
WO2021005903A1 (ja) * | 2019-07-11 | 2021-01-14 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP2021015880A (ja) * | 2019-07-11 | 2021-02-12 | 国立研究開発法人産業技術総合研究所 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
JP7410478B2 (ja) | 2019-07-11 | 2024-01-10 | 富士電機株式会社 | 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 |
Also Published As
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2010131573A1 (ja) | 絶縁ゲート型バイポーラトランジスタ | |
WO2011046020A1 (ja) | 炭化珪素基板の製造方法、炭化珪素基板および半導体装置 | |
JP2011243770A (ja) | 炭化珪素基板、半導体装置、炭化珪素基板の製造方法 | |
WO2011052320A1 (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
WO2011142158A1 (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
JPWO2011052321A1 (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
WO2010131571A1 (ja) | 半導体装置 | |
WO2011077797A1 (ja) | 炭化珪素基板 | |
WO2011092893A1 (ja) | 炭化珪素基板の製造方法 | |
WO2012127748A1 (ja) | 炭化珪素基板 | |
JP2011243618A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
JP2011243640A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
WO2011086734A1 (ja) | 炭化珪素基板の製造方法 | |
JP2011243771A (ja) | 炭化珪素基板の製造方法、半導体装置の製造方法、炭化珪素基板および半導体装置 | |
JP2011086660A (ja) | 炭化珪素基板の製造方法および炭化珪素基板 | |
JP2011068504A (ja) | 半導体基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080020696.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10774831 Country of ref document: EP Kind code of ref document: A1 |
|
DPE1 | Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101) | ||
ENP | Entry into the national phase |
Ref document number: 2011513304 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2761246 Country of ref document: CA |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13320243 Country of ref document: US |
|
ENP | Entry into the national phase |
Ref document number: 20117028517 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010774831 Country of ref document: EP |