WO2008095337A1 - Procédé pour la fabrication d'une structure d'assemblage commune entre des panneaux multicouche et structure associée - Google Patents

Procédé pour la fabrication d'une structure d'assemblage commune entre des panneaux multicouche et structure associée Download PDF

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Publication number
WO2008095337A1
WO2008095337A1 PCT/CN2007/000378 CN2007000378W WO2008095337A1 WO 2008095337 A1 WO2008095337 A1 WO 2008095337A1 CN 2007000378 W CN2007000378 W CN 2007000378W WO 2008095337 A1 WO2008095337 A1 WO 2008095337A1
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WIPO (PCT)
Prior art keywords
dielectric layer
layer
substrate
multilayer substrate
edge
Prior art date
Application number
PCT/CN2007/000378
Other languages
English (en)
French (fr)
Inventor
Chihkuang Yang
Original Assignee
Princo Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Princo Corp. filed Critical Princo Corp.
Priority to EP07702269.7A priority Critical patent/EP2120521B1/en
Priority to KR1020097018481A priority patent/KR101150385B1/ko
Priority to JP2009548557A priority patent/JP5005043B2/ja
Priority to PCT/CN2007/000378 priority patent/WO2008095337A1/zh
Publication of WO2008095337A1 publication Critical patent/WO2008095337A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/361—Assembling flexible printed circuits with other printed circuits
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    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/058—Direct connection between two or more FPCs or between flexible parts of rigid PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/09109—Locally detached layers, e.g. in multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the PCB or at the walls of large holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards

Definitions

  • the present invention relates to a method of manufacturing an inter-substrate inter-connecting structure and an inter-connecting structure thereof, and more particularly to a method for manufacturing an inter-connected structure of any kind of multi-layer substrate and an interactive connecting structure thereof, which can be applied to soft
  • the package is suitable for various types of chip components.
  • an integrated system with a basic architecture may include a variety of different chip components' (eg, logic components, memory components, analog components, optoelectronic components, MEMS components, or illuminating components, etc.), and these different types of chips
  • chip components eg, logic components, memory components, analog components, optoelectronic components, MEMS components, or illuminating components, etc.
  • the package density can be further increased and the system can be miniaturized.
  • a stacked chip scale package (SCSP) for chip-to-chip packages has been developed, the so-called 3D package.
  • SCSP stacked chip scale package
  • the packaging technology is still limited to the packaging concept of a rigid system.
  • the package substrate may be a flexible multi-layer substrate (for example: Control board and screen control connection), or the package substrate may also be a non-planar, irregular The form of sexuality.
  • the interaction between the two multi-layer substrates must be realized through a connection other than the substrate itself or a package external to the substrate itself.
  • the current multi-layer substrate packaging technology is improved to more effectively increase the package density.
  • the connection density between various chip components in a hybrid system, even in so-called system-level packaging, has become an extremely important issue and challenge in today's packaging-related technologies. Therefore, if a structure in which an inter-substrate is inter-connected and a method of manufacturing the same can be developed, each of the multi-layer substrates for encapsulating any type of chip is used to increase the interconnection density between the substrate and the substrate, and at the same time, as a flexible multilayer substrate. By connecting the package, the package density can be further increased and the system can be miniaturized.
  • a primary object of the present invention is to provide a method for fabricating an inter-substrate inter-connecting structure and an inter-connecting structure thereof, which can directly interconnect a plurality of any kind of chip components without sharing a single package substrate. , increase package density and miniaturize the system.
  • Another object of the present invention is to provide a method for manufacturing an inter-substrate inter-connecting structure and an inter-connecting structure thereof, wherein the interconnected structure can increase the packing density and miniaturize the system, and provide deformable or flexible The features are thus available as soft system applications.
  • a method for manufacturing an inter-substrate inter-connecting structure of the present invention comprises the following steps:
  • step (a) is further included, that is, a carrier is provided for forming one of the multilayer substrates, wherein forming the multilayer substrate comprises the following steps:
  • step (c) after forming a metal layer and a necessary via hole (VIA) on the dielectric layer, and then coating the dielectric layer; (d) repeating step (c) to form a multilayer substrate;
  • the method further includes a step of performing an interface adhesion strengthening treatment along the region of the carrier to increase the adhesion strength between the dielectric layer and the carrier along the region.
  • an interface adhesion strengthening treatment is performed on the surface of the carrier to increase the adhesion strength between the dielectric layer and the carrier, and another dielectric layer is coated on the surface on the dielectric layer. If the other dielectric layer is coated on the surface of the dielectric layer, the multi-layer substrate is removed from the dielectric layer and the other dielectric layer in step (e). Stripped.
  • the manufacturing method of the present invention further includes a step of bonding the second outer layer of the multilayer substrate to the first outer layer before or after the step (2) of bonding.
  • the connection package encloses a plurality of chip components and a third substrate and the multilayer substrates.
  • the inter-connecting structure between the multi-layer substrates of the present invention comprises at least a first multi-layer substrate and a second multi-layer substrate.
  • the first multi-layer substrate has a plurality of first metal layers and a plurality of first dielectric layers, wherein an edge of at least one of the first metal layers is connected to an end edge of the corresponding first dielectric layer, and Opposite the edges of the other adjacent first metal layers and the first dielectric layer.
  • the second multi-layer substrate has a plurality of second metal layers and a plurality of second dielectric layers, wherein an end edge of the at least one second metal layer is connected to an end edge of the corresponding second dielectric layer, and Separating from an edge of the other adjacent second metal layer and the second dielectric layer; then, at least one first metal layer of the first multilayer substrate and at least a second metal layer of the second multilayer substrate are mutually
  • the bonding further forms a joint portion, thereby completing the interconnection structure between the multilayer substrates.
  • the inter-connecting structure of the present invention further includes a first chip component for bonding and packaging with the first outer layer of the first multilayer substrate; and a second chip component for the first outer layer of the second multilayer substrate The layer is encapsulated.
  • the inter-connecting structure between the multi-layer substrates of the present invention further includes a third substrate for The layer substrate and the second multilayer substrate are indirectly connected and packaged.
  • the first multilayer substrate, the second multilayer substrate, and the third substrate may each be a flexible multilayer interconnect substrate.
  • the method for manufacturing the inter-substrate inter-connecting structure and the cross-connect structure thereof can directly interconnect a plurality of any kind of chip components, and the cross-connect structure can further enhance the package. Density and miniaturization of the system. Therefore, the multi-substrate inter-linkage structure of the present invention can further provide deformable or flexible characteristics, thereby being applicable as a soft system.
  • the invention will be further described below in conjunction with the drawings and embodiments.
  • FIGS. 1A to 1 are schematic diagrams showing the steps corresponding to steps (a) to (h) of a first embodiment of a method for fabricating an inter-substrate inter-connecting structure according to the present invention
  • FIGS. 2A to 21 are layers in accordance with the present invention.
  • the second embodiment of the manufacturing method of the inter-substrate interconnection structure corresponds to the structural diagram of the steps (a) to (h);
  • FIGS. 3A to 3H show the third method of manufacturing the inter-substrate interconnection structure according to the present invention.
  • the embodiment corresponds to the structural schematic diagram of the steps (a) to (h); FIGS.
  • FIGS. 6A to 6H are diagrams according to the present invention.
  • the sixth embodiment of the method for manufacturing the inter-substrate inter-connecting structure corresponds to the structural diagram of the steps (a) to (h); and FIGS. 7A to 71 show the seventh embodiment of the manufacturing method of the inter-substrate inter-connecting structure according to the present invention.
  • Figure 8 is a cross-sectional view showing the inter-substrate interconnection structure of the first, second, fourth, and fifth embodiments according to the present invention;
  • Figure 9 is a multilayered embodiment of the third embodiment according to the third embodiment of the present invention.
  • FIGS. 1A to 1G there are corresponding steps of a first embodiment of a method for manufacturing an inter-substrate inter-connecting structure according to the present invention.
  • the first embodiment of the method for manufacturing an inter-substrate inter-connecting structure of the present invention comprises the following steps: FIG. 1A shows a step (a), and a carrier 102 is provided for forming a multi-layer substrate (in the first multi-layer substrate) 300 is an example; FIG.
  • FIG. 1B shows a step (b) of performing an interface adhesion strengthening process along the region 119 of the carrier to increase the gap between the edge 119 of the first dielectric layer 19 corresponding to the carrier 102 and the carrier 102.
  • Adhesion strength FIG. 1C shows a step (c) of forming a first metal layer 18 on the first dielectric layer 19 and a necessary via layer 9 (shown in FIG. 1D), and then coating another A dielectric layer 16;
  • FIG. 1D shows the step (d), and the step (c) is repeated to form the first multilayer substrate 300.
  • the regions 17, 17-1 in this embodiment are not subjected to the adhesion strengthening treatment; Representing step (e), dividing the carrier edge region 119 and its corresponding multilayer substrate edge 120 along the separation edge (ie, along the vertical dividing lines d1, d2 in FIG.
  • FIG. 1A shows a step (g) of bonding the separated end edges of the metal layers 12, 15 and 18 of the first multilayer substrate 300 to the second multilayer substrate 400.
  • the second multi-layer substrate 400 has been inverted upside down with respect to the first multi-layer substrate 300, so that in these manufacturing steps, the original and dielectric layers 20, 23 and 26 correspond, and the metal layers 22, 25 and 27 located underneath are placed upside down.
  • the bonding between the metal layers 12, 15 and 18 of the first multilayer substrate 300 and the metal layers 22, 25 and 27 of the second multilayer substrate 400 can be immersed and bonded to Eutectic bonding, bonding with an anisotropic conductive film, or gold-gold bonding, gold-copper bonding, etc. a structure in which the layer substrates are alternately connected; and FIG.
  • step II shows a step (h), in which the second outer layer and the first outer layer (ie, the upper and lower layers) of the multilayer substrate are the first chip component 100 and the second chip component 200, A third substrate is bonded to the multilayer substrates.
  • the method of connecting the packages may be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • BGA ball grid array package
  • LGA planar gate grid array
  • PGA pin grid array package
  • Wire Bond wire bond
  • 2D which is a structural diagram of steps (c) and (d) which are different from the first embodiment in the second embodiment of the manufacturing method of the inter-substrate interconnection structure according to the present invention. Except for the steps (c) and (d), the other steps shown in Figs. 2A, 2B, and 2E to 21 in the second embodiment are the same as those in the first embodiment.
  • 2C shows the step (c), before the first dielectric layer 16 is applied, in the second embodiment, an adhesion strengthening treatment is performed in the region 17 to increase the first dielectric layer 16 and the coating in the step (b). The adhesion strength between the first dielectric layers 19 can be further maintained in the state of being fixed in the step (d) shown in FIG. 2D later.
  • step (g) and step (h) are structural diagrams of steps (c) to (g) which are different from the first embodiment in the third embodiment of the manufacturing method of the inter-substrate interconnection structure according to the present invention. Except for the foregoing steps, the steps shown in Figs. 3A and 3B in the third embodiment are the same as those in the second embodiment.
  • step (c) shown in FIG. 3D shows the step (c), before the first dielectric layer 16 is applied, in the second embodiment, the adhesion strengthening treatment is performed in the regions 17, 17-1 to increase the adhesion strength of these regions, which may be further
  • step (d) shown in FIG. 3D the state of being fixed is maintained, and the possibility of occurrence of a non-closed situation due to separation or deformation between dielectric layers is reduced, thereby improving the process yield; after performing step (e) shown in FIG. 3E, Skip step (e '), directly performing step (f) shown in FIG. 3F without removing the first dielectric layer 19 adjacent to the carrier; and FIG.
  • step (f) making the first multilayer
  • the edge of the dielectric layer on the substrate 300 and the corresponding metal layer are separated from the edges of the other adjacent dielectric layers and their corresponding metal layers (10 and 12, 13 and 15, 16 and 18) to form a preliminary a connecting portion 120 interconnected with the other multilayer substrate, and removing the edge 19-1 of the first dielectric layer 19 to expose the edge of the first metal layer 18 corresponding to the first dielectric layer 19 for preparation
  • step (g) shown in FIG. 3G a separate edge is formed with another multilayer substrate (taking the second multilayer substrate 400 as an example) The second metal layer 22, 25 and 27 bond.
  • 3G shows the step ( g ) of bonding the separated end edges of the metal layers 12, 15 and 18 of the first multilayer substrate 300 to the metal layers 22, 25 and 27 having the separated end edges of the second multilayer substrate 400.
  • the second multi-layer substrate 400 has been inverted upside down with respect to the first multi-layer substrate 300.
  • the original and dielectric layers 20, 23 and 26 correspond to the metal layers 22, 25 and 27 located underneath.
  • the bonding between the metal layers 12, 15 and 18 of the first multilayer substrate 300 and the metal layers 22, 25 and 27 of the second multilayer substrate 400 can be immersed and bonded to Eutectic bonding, bonding with an anisotropic conductive film, or gold-gold bonding, gold-copper bonding, etc.
  • 3H shows a step (h) of the second outer layer and the first outer layer (ie, the upper and lower layers) of the multilayer substrate, the first chip component 100, the second chip component 200, a third substrate, and the multilayer substrate.
  • the method of connecting the packages may be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • BGA ball grid array package
  • LGA planar gate grid array
  • PGA pin grid array package
  • Wire Bond wire bond
  • FIG. 4A shows a step (a), and a carrier 102 is provided for forming a multi-layer substrate (in the first multi-layer substrate) 300 is an example
  • FIG. 4B shows a step (b) of performing an interface adhesion strengthening treatment on the surface of the carrier 102 to increase the adhesion strength between the dielectric layer 104 and the carrier 102, and hardening the After the dielectric layer 104, another dielectric layer 19 is coated on the surface of the dielectric layer 104.
  • FIG. 4C shows a step (c), forming a first metal layer 18 on the dielectric layer and necessary After a plurality of via holes 9 (shown in FIG.
  • FIG. 4D shows step (d), and step (c) is repeated to form the first multilayer substrate 300, however, The regions 17, 17-1 in this embodiment are not subjected to the adhesion strengthening treatment;
  • Fig. 4E shows the step (e), dividing the carrier along the separation edge (i.e., along the vertical dividing lines d1, d2 in Fig. 4D) 119 (shown in Figure 4C) and its corresponding multilayer substrate end edge 120, and from the first dielectric layer 19 and the dielectric layer 104 (shown in Figure 4B)
  • the first multilayer substrate 300 is peeled off from the carrier 102 (shown in FIG. 4B);
  • FIG. 4B shows the separation edge
  • FIG. 4F shows the step (V), the first dielectric layer 19 is removed, and the first dielectric layer 19 is exposed.
  • a metal layer 18 FIG. 4G shows a step (f) of separating the end edges of the dielectric layer on the first multilayer substrate and the corresponding metal layer from the edges of the other adjacent dielectric layers and their corresponding metal layers. (10 and 12, 13 and 15, 16 and 18) to form a connection portion 120 which is prepared to be interconnected with other multilayer substrates; and
  • FIG. 4H shows a step (g) of the metal layer of the first multilayer substrate 300. The separation edges of 15 and 18 are bonded to the metal layers 22, 25 and 27 of the second multilayer substrate 400 having separate edges.
  • the second multi-layer substrate 400 has been inverted upside down with respect to the first multi-layer substrate 300.
  • the original and dielectric layers 20, 23 and 26 correspond to the metal layers 22, 25 and 27 located underneath.
  • the bonding between the metal layers 12, 15 and 18 of the first multilayer substrate 300 and the metal layers '22, 25 and 27 of the second multilayer substrate 400 can be immersed and bonded,
  • the invention is completed by Eutectic bonding, adhesion by an anisotropic conductive film, or gold-gold bonding, gold-copper bonding, or the like. a structure in which the multi-layer substrates are interconnected; and FIG.
  • a third substrate is bonded to the multilayer substrate.
  • the method of connecting the packages may be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • BGA ball grid array package
  • LGA planar gate grid array
  • PGA pin grid array package
  • Wire Bond wire bond
  • Steps (c) and (d) are excluded.
  • 5A, 5B, and 5E to 51 are the same as the fourth embodiment.
  • Fig. 5C shows the step (c), before the first dielectric layer 16 is applied,
  • the adhesion strengthening treatment is performed in the region 17 to increase the adhesion strength between the first dielectric layer 16 and the first dielectric layer 19 coated in the step (b), which can be further represented by FIG. 5D later.
  • the step (d) the state of the solid state is maintained, and the possibility of occurrence of a non-closed state due to separation or deformation between the dielectric layers is reduced, thereby improving the process yield.
  • This embodiment can also interchange the order of step (g) and step (h) without changing the interactive structure of the present invention or affecting its function.
  • FIG. 6C to 6G are structural diagrams showing steps (c) to (g) which are different from the fourth embodiment in the sixth embodiment of the method for manufacturing the inter-substrate interconnection structure according to the present invention.
  • Fig. 6C shows the step (c).
  • the adhesion strengthening treatment is performed in the regions 17, 17-1 to increase the adhesion strength of these regions, which can be further shown in Fig. 6D.
  • the step (d) shown the state of the fixed connection is maintained, and the possibility of occurrence of the intimate situation is reduced by the separation or deformation between the dielectric layers, thereby improving the process yield; after performing the step (e) shown in FIG. 6E, the jump is performed.
  • FIG. 6F is directly performed through step (e ') without removing the first dielectric layer 19 adjacent to the carrier; and FIG. 6F shows step (f) to make the first multilayer
  • the edge of the dielectric layer on the substrate 300 and the corresponding metal layer are separated from the edges of the other adjacent dielectric layers and their corresponding metal layers (10 and 12, 13 and 15, 16 and 18) to form a preliminary a connecting portion 120 interconnected with the other multilayer substrate, and removing the edge 19-1 of the first dielectric layer 19 to expose the edge of the first metal layer 18 corresponding to the other dielectric layer 19 for preparation
  • step (g) shown in FIG. 6G a separate edge is formed with another multilayer substrate (taking the second multilayer substrate 400 as an example)
  • the second metal layers 22, 25 and 27 are bonded.
  • 6G shows the step ( g ) of bonding the separated end edges of the metal layers 12, 15 and 18 of the first multilayer substrate 300 to the metal layers 22, 25 and 27 having the separated end edges of the second multilayer substrate 400.
  • the second multi-layer substrate 400 has been inverted upside down with respect to the first multi-layer substrate 300.
  • the original and dielectric layers 20, 23 and 26 correspond to the metal layers 22, 25 and 27 located underneath.
  • the bonding between the metal layers 12, 15 and 18 of the first multilayer substrate 300 and the metal layers 22, 25 and 27 of the second multilayer substrate 400 can be immersed and bonded to Eutectic bonding, bonding with an anisotropic conductive adhesive, or gold-gold bonding, gold-copper bonding, etc.; and Figure 6H Representing step (h), the second outer layer and the first outer layer (ie, the upper and lower layers) of the multilayer substrate are fed with the first chip component 100, the second chip component 200, a third substrate, and the multilayer substrate Line link encapsulation.
  • the method of connecting the packages may be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • BGA ball grid array package
  • LGA planar gate grid array
  • PGA pin grid array package
  • Wire Bond wire bond
  • This embodiment can also interchange the order of step (g) and step (h) without changing the interactive structure of the present invention or affecting its function.
  • 7D to 71 are structural diagrams showing steps (d) to (h) which are different from the first embodiment in the seventh embodiment of the method for manufacturing the inter-substrate interconnection structure according to the present invention.
  • the steps shown in Figs. 7A to 7C in the seventh embodiment are the same as those in the first embodiment except for the foregoing steps.
  • FIG. 7D shows the step (d), the step (c) is repeated, the first multilayer substrate 300 is formed, and the third multilayer substrate 500 adjacent to the first multilayer substrate 300 is simultaneously formed as shown in the drawing;
  • FIG. 7E shows Step (e), completely dividing the carrier edge region and its corresponding multilayer substrate along the separation edge (ie, along the vertical dividing lines d1, d3 in FIG. 7D), but dividing the d2 from the chip only to the uppermost portion
  • the first metal layer 12 and the first dielectric layer 10, and the first multilayer substrate 300 and the third multilayer substrate 500 are separated from the carrier 102;
  • FIG. 7F shows the step (e'), removing the first The first dielectric layer 19 adjacent to the carrier substrate 300 and the third multilayer substrate 500 is exposed, and the first metal layer 18 corresponding to the first dielectric layer 19 is exposed;
  • FIG. 7G shows the step (f), making the first The edge of the dielectric layer on the layer substrate 300 and the corresponding metal layer are separated from the edges of the other adjacent dielectric layers and their corresponding metal layers (10 and 12, 13 and 15, 16 and 18) to form a connection portion 120 that is interconnected with other multilayer substrates, but maintains the first metal layer 10 and the first between the third multilayer substrate 500 and the first multilayer substrate 300 The connection of the dielectric layer 12, and the dielectric layers of the third multilayer substrate 500 itself and their corresponding metal layer edges are not separated; FIG.
  • FIG. 7H shows the step (g), like the first embodiment, the first multilayer
  • the separated end edges of the metal layers 12, 15 and 18 of the substrate 300 are bonded to the metal layers 22, 25 and 27 having the separated end edges of the second multilayer substrate 400, and the second multilayer substrate 400 and the third multilayer substrate 500
  • FIG. 71 shows a step (h), the upper and lower layers of the multi-cross-connect structure between the multilayer substrates formed by the multi-layer substrates, the first chip component 100, the second chip component 200, and the third Substrate with these The layer substrate is bonded and packaged.
  • the method of connecting the packages may be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • the second chip component 200 is package-bonded to the third multilayer substrate 500. Therefore, the multiple cross-linking between the multi-layer substrates of the present invention can provide a more flexible concept of an interlocking structure.
  • This embodiment can also interchange the order of step (g) and step (h) without changing the interactive structure of the present invention or affecting its function.
  • FIG. 8 is a cross-sectional view showing the inter-substrate interconnection structure of the first, second, fourth and fifth embodiments according to the present invention.
  • the inter-connecting structure between the multi-layer substrates of the present invention includes at least a first multi-layer substrate 300 and a second multi-layer substrate 400. The first outer layer of the first multilayer substrate 300 is connected and packaged with a first chip component 100.
  • the first outer layer of the second multilayer substrate 400 is bonded to a second chip component 200.
  • the first chip component 100 and the second chip component 200 may be any kind of chip component such as a logic component, a memory component, an analog component, a photovoltaic component, a microelectromechanical component, or a light emitting component.
  • the inter-connecting structure between the multi-layer substrates may further include a third multi-layer substrate (not shown). As shown in FIG. 7 , the third substrate is permeable to the first multi-layer substrate 300 through the solder ball 410; and the solder ball 420 and the second multi-layer substrate 400 are connected and packaged, or the first chip component or The second chip component is bonded and packaged.
  • the package method of the third substrate may also be performed by a ball grid array package (BGA), a planar gate grid array (LGA), a pin grid array package (PGA), or a wire bond (Wire Bond).
  • BGA ball grid array package
  • LGA planar gate grid array
  • PGA pin grid array package
  • Wire Bond wire bond
  • each of the first multilayer substrate 300, the second multilayer substrate 400, and the third substrate may be a flexible multilayer interconnect substrate.
  • the structure in which the multilayer substrates are interconnected by the present invention can provide deformable or flexible properties, and can be used as a package connection of these flexible multilayer substrates.
  • the first multilayer substrate 300 includes a plurality of layers of first dielectric layers 10, 13 and 16, and a plurality of layers of first metal layers 12, 15 and 18.
  • the second multilayer substrate 400 includes a plurality of layers of second dielectric layers 20, 23 and 26, and a plurality of layers of second metal layers 22, 25 and 27. Therefore, substantially the first chip component 100 is encapsulated in the via hole of the first dielectric layer 10 of the first multilayer substrate 300 by the solder ball 110. (VIA), the second chip component 200 is encapsulated in the via hole or the second metal layer 27 of the second dielectric layer 26 of the second multilayer substrate 400 with the solder balls 210.
  • An edge of both the first metal layer 12 of the first multilayer substrate 300 and the butted first dielectric layer 10, the edge of both the first metal layer 15 and the butted first dielectric layer 13, and The end edges of both the first metal layer 18 and the butted first dielectric layer 16 are each relatively separated from the adjacent first metal layer and the corresponding first dielectric layer.
  • the end of the second metal layer 22 of the second multilayer substrate 400 and the butted second dielectric layer 20 the end of the second metal layer 25 and the butted second dielectric layer 23
  • the edge, and the edge of both the second metal layer 27 and its butted second dielectric layer 26 are each relatively separated from the edge of the adjacent second metal layer and the second dielectric layer.
  • the bonding method can be used for bonding adhesives 1, 2, 3, immersion tin, eutectic bonding, bonding with anisotropic conductive adhesive (Anisotropic Conductive Fi lm), or gold-gold (Gold- Gold). ) Bonding, or bonding with gold-copper (Gold-Copper).
  • the second metal layers 22, 25 and 27 are integrally connected to the first metal layers 12, 15 and 18.
  • the direct interconnection between the first chip 100 and the second chip 200 can be achieved by the structure of the interconnection between the multi-layer substrates.
  • the multi-substrate dielectric layer and the corresponding metal layers are not separated and directly packaged, and the separated end of the substrate is used between the first multi-layer substrate 300 and the second multi-layer substrate 400.
  • the edges are interconnected, so that the package density can be further improved and the system can be miniaturized, and any deformable or flexible characteristics can be further provided, thereby serving as a system for flexible packaging. Further, in Fig.
  • an interface adhesion strengthening treatment is performed, and the processing regions 11, 14, 21, and 24 are indicated by thick black lines. It is particularly noteworthy that since other regions than the separation edge of the substrate (between the dielectric layers other than the connection portion 120) are subjected to interface adhesion strengthening treatment to increase the adhesion strength between the dielectric layers, The interface adhesion enhancement treatment is not performed.
  • the end edge inside the connecting portion 120
  • the manner in which the edge of the multilayer substrate is separated may be performed by using a double-sided tape (for example, UV tape) on the first outer layer and the second outer layer of the first multilayer substrate 300 or the second multilayer substrate 400.
  • the tape When the tape is opened, the tape will be brought to the end of the edge where the interface adhesion strengthening treatment is not performed. Repeating the action of affixing and tearing the tape repeatedly can separate the layers of the unattached reinforcing edges, but the metal layers 12, 15, 18, 22, 25 and 27 will be respectively associated with the dielectric layers 10, 13, 16 20, 23 and 26 are connected.
  • the dielectric layer/dielectric interlayer selective interface adhesion strengthening treatment concept the structure of the first multilayer substrate 300 or the second multilayer substrate 400 of the present invention can be completed.
  • the material of the dielectric layer in the present invention is polyimide (Polyimide)
  • the above-mentioned interface adhesion strengthening treatment can be performed by an oxygen or argon electric paddle process.
  • Figure 8 is a cross-sectional view showing an inter-substrate interconnection structure according to a third embodiment and a sixth embodiment of the present invention.
  • the package form is different, before the step (c) is applied to the other dielectric layer, in the region 17 - 1
  • the adhesion strengthening treatment is performed, and thereafter the pad form of the third substrate is changed as an option for different connection operations.
  • the one-to-one relative bonding between the metal layers 12, 15 and 18 of the first multilayer substrate 300 and the second metal layers 22, 25, 27 of the second multilayer substrate 400 is performed.
  • the structure and the manufacturing method of the inter-substrate interaction between the multi-layer substrates enable the inter-connected structure between the plurality of multi-layer substrates encapsulating the respective chips through a plurality of chip elements of any type.
  • the direct interconnection does not need to pass through the third substrate, and the interactive structure can further increase the package density and miniaturize the system.
  • the multi-substrate inter-linkage structure of the present invention further provides deformable or flexible properties for use as a soft system.
  • the present invention has a system integration packaging capability with high integration and high package density.

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Description

多层基板间交互连结结构的制造方法及其交互连结结构
技术领域 本发明涉及一种多层基板间交互连结结构的制造方法及其交互连结结构， 特别是关于一种多层任意种类基板间交互连结结构的制造方法及其交互连结结 构， 可应用于软性封装并适用于各种型式的芯片元件。
背景技术 如今任何类型的电子产品都日趋小型化， 随着半导体晶圆制程尺寸的不断 縮小， 后段封装的相关技术也必须随之朝微型化的方向发展。 因此， 当今 I. C. 整合电路的积集度已不断地大幅提高， 其中使用多层基板来封装不同种类元件， 整合各项功能成为一高效能***已是必然。 举例来说， 一具有基本架构的整合 式***可能包括各种不同的芯片元件' (例如： 逻辑元件、 内存元件、 模拟元件、 光电元件、 微机电元件或发光元件等）， 而这些不同种类芯片元件彼此之间的相 互连通均需透过共享的单一封装基板， 才能进行互连。 如果態将一芯片元件直 接与另一芯片元多重互连， 将可进一步提升封装密度， 使***微型化。 如今虽 已发展一种有关芯片与芯片间封装的堆栈式芯片级封装（Stacked Chip Scale Package; SCSP) , 即所谓的立体式封装 (3D package)。 然而， 基本上该封装技 术仍局限于硬性***的封装概念。 并且， 为配合如今电子产品的多样化及变异性， 封装基板可能是一软性多 层基板 (例如： Notebook主机板与屏幕的控制连线）， 或者封装基板也有可能是 一非平面、 非规则性面的形态。 依据现有技术， 两多层基板间的交互连结必须 透过基板本身以外的连线或基板本身外部的封装等方式才能实现。 因此， 为适 应更具弹性的软性电路板 (软性多层基板)或者多芯片堆栈、 非一般平面封装基 板的软性封装， 改良目前的多层基板封装技术， 以更有效地提高封装密度及整 合式***内各种芯片元件间的连接密度， 甚至应用在所谓***级的封装， 巳成 为如今封装相关技术中一极为重要的课题与挑战。 因此， 如果能发展一种多层基板间交互连结的结构及其制造方法， 用于封 装任意种类芯片的各个多层基板， 使基板与基板间互连密度提高， 同时作为软 性多层基板的连结封装， 即能进一步提高封装密度并使***微型化。
发明内容 本发明的主要目的在于提供一种多层基板间交互连结结构的制造方法 及其交互连结结构， 能使若干个任意种类的芯片元件间， 无需透过共享的单一 封装基板而直接互连， 提高封装密度并使***微型化。 本发明的另一目的在于提供一种多层基板间交互连结结构的制造方法及 其交互连结结构， 其交互连结的结构能提升封装密度并使***微型化， 并提供 可变形或可挠曲的特性从而可作为软性***应用。 为实现上述目的， 本发明多层基板间交互连结结构的制造方法包括下列步 骤：
(1)使每一多层基板上至少一介电层及与其对应的金属层的端缘从其它相 邻介电层局部及其对应金属层的端缘分离； 以及
(2)将其中一多层基板的至少一介电层的分离端缘黏结于另一多层基板的 具分离端缘的金属层， 以完成这些多层基板间的交互连结结构。 依据本发明的制造方法， 在分离步骤（1)之前， 进一步包括一步骤 (a)， 即 提供一载板用以形成其中一多层基板， 其中形成多层基板包括下列步骤：
(b)在载板上的表面， 涂布一介电层；
(c)在介电层上形成一金属层及必要的介层洞 (VIA)后， 再涂布介电层； (d)重复步骤 (c)， 形成多层基板； 以及
(e)沿分离端缘分割出载板沿区域及其对应的多层基板， 并将多层基板从 载板剥离。 在本发明制造方法的步骤 (b)中， 进一步包括一步骤， 即在载板沿区域， 进行一界面附着强化的处理， 以增加介电层对应载板沿区域与载板间的附着强 度， 或者在载板上的表面进行一界面附着强化的处理， 以增加介电层与载板间 的附着强度， 并且在介电层上的表面， 再涂布另一介电层。 如前述在该介电层 上的表面， 再涂布另一介电层， 则在步骤 (e)中从该介电层与该另一介电层间， 将该多层基板从该载板剥离。 本发明的制造方法在黏结的步骤 (2)之前或之后， 进一步包括其中一步骤， 即对这些多层基板的第二外层面与第一外层面进行连结封装。 其中该连结封装 连结若干个芯片元件与一第三基板与这些多层基板。 本发明多层基板间的交互连结结构包括至少一第一多层基板及一第二多 层基板。 第一多层基板具有若干个相互交叠的第一金属层与若干个第一介电层， 其中至少一第一金属层的端缘与其对应的第一介电层的端缘相连接， 而与其它 相邻第一金属层和第一介电层的端缘相对分离。 第二多层基板具有若干个相互 交叠的第二金属层与若干个第二介电层， 其中至少一第二金属层的端缘与其对 应的该第二介电层的端缘连接， 而与其它相邻第二金属层及第二介电层的端缘 相对分离； 之后， 该第一多层基板的至少一第一金属层与该第二多层基板的至 少一第二金属层相互黏结进一步形成一连结部， 从而完成多层基板间的交互连 结结构。 本发明的交互连结结构进一步包括一第一芯片元件， 用以与第一多层基板 的第一外层面进行连结封装； 以及一第二芯片元件， 用以与第二多层基板的第 一外层面进行连结封装。 第一芯片元件及第二芯片元件均是逻辑元件、 内存元 件、 模拟元件、 光电元件、 微机电元件以及发光元件等之中的任意元件。 本发明多层基板间的交互连结结构进一步包括一第三基板， 用以对第一多 层基板与第二多层基板进行间接的连结封装。 该第一多层基板、 该第二多层基 板及该第三基板均可以是一软性多层内连线基板。 与现有技术相比， 本发明提供的多层基板间交互连结结构的制造方法及其 交互连结结构， 能使若干个任意种类的芯片元件间直接互连， 并且其交互连结 结构能进一步提升封装密度并使***微型化。 因此， 本发明的多层基板间交互 连结结构可进一步提供可变形或可挠曲的特性， 从而可作为软性***应用。 以下结合附图与实施例对本发明作进一步的说明。
附图说明 图 1A至 II为依据本发明多层基板间交互连结结构的制造方法的第一实施 例对应步骤 (a)至步骤 (h)的结构示意图； 图 2A至 21为依据本发明多层基板间交互连结结构的制造方法的第二实施 例对应步骤 (a)至步骤 (h)的的结构示意图； ― 图 3A至 3H为依据本发明多层基板间交互连结结构的制造方法的第三实施 例对应步骤 (a)至步骤 (h)的结构示意图； 图 4A至 41为依据本发明多层基板间交互连结结构的制造方法的第四实施 例对应步骤 (a)至步骤 (h)的结构示意图； 图 5A至 51为依据本发明多层基板间交互连结结构的制造方法的第五实施 例对应步骤 (a)至步骤 (h)的结构示意图; · 图 6A至 6H为依据本发明多层基板间交互连结结构的制造方法的第六实施 例对应步骤 (a)至步骤 (h)的结构示意图； 图 7A至 71为依据本发明多层基板间交互连结结构的制造方法的第七实施 例对应步骤 (a)至步骤 (h)的结构示意图； 图 8为依据本发明的第一、 第二、 第四以及第五实施例多层基板间交互连 结结构的剖面图； 以及 图 9为依据本发明的第三实施例、第六实施例多层基板间交互连结结构的 剖面图。
具体实施方式 有关本发明的详细说明及技术内容， 现就结合附图说明如下: 请参考图 1A至 1G， 为依据本发明多层基板间交互连结结构的制造方法的 第一实施例对应步骤 (a)至步骤 (g)的结构示意图。 本发明若干个多层基板间交互连结结构的制造方法第一实施例， 包括下列 步骤： 图 1A表示步骤 (a)， 提供一载板 102用以形成一多层基板（以第一多层基 板 300为例）； 图 1B表示步骤 (b)， 在载板沿区域 119， 进行一界面附着强化的处理， 以 增加第一介电层 19对应载板 102的端缘 119与载板 102间的附着强度； 图 1C表示步骤 (c)， 在第一介电层 19上形成一第一金属层 18及必要的若 千个介层洞 9 (显示于图 1D)后， 再涂布另一第一介电层 16; 图 1D表示步骤 (d)， 重复步骤 (c)， 形成第一多层基板 300， 但是， 在此实 施例中的区域 17、 17-1未进行附着强化处理； 图 1E表示步骤 (e)， 沿分离端缘（即沿着图 ID中的垂直分割线 dl、 d2)分 割载板沿区域 119及其对应的多层基板的端缘 120，并将第一多层基板 300从载 板 102剥离； 图 IF表示步骤 (e ' )， 移除与载板相邻的第一介电层 19， 露出对应第一介 电层 19的第一金属层 18; 图 1G表示步骤 (f)， 使第一多层基板 300上介电层及与其对应的金属层的 端缘各从其它相邻介电层局部及其对应金属层的端缘分离（10与 12、 13与 15、 16与 18)， 以形成一预备与其它多层基板交互连结的连接部 120; 图 1Ή表示步骤 (g)， 将第一多层基板 300的金属层 12、 15以及 18的分离 端缘黏结于第二多层基板 400的具分离端缘的金属层 22、 25以及 27。 并且， 第 二多层基板 400 已相对第一多层基板 300上下倒置， 使这些制造步骤中， 原本 和介电层 20、 23及 26对应， 位于其下方的金属层 22、 25及 27倒置于介电层 20、 23及 26上方， 而第一多层基板 300的金属层 12、 15及 18与第二多层基板 400的金属层 22、 25及 27间的黏结方式可以浸锡黏结、以共晶（Eutectic)黏结、 以异方性导电胶（Anisotropic Conductive Film)黏结， 或者以金-金（Gold- Gold) 黏结、 以金-铜（Gold- Copper)黏结等方式， 以完成本发明多层基板间交互连结 的结构； 以及 图 II表示步骤 (h)， 对这些多层基板的第二外层面与第一外层面（即上下 层面）以第一芯片元件 100、 第二芯片元件 200、 一第三基板与这些多层基板进 行连结封装。 连结封装的方式， 可以球栅阵列封装 (BGA)、 平面闸格阵列 (LGA)、 针脚栅格阵列封装 (PGA)或打线接合 (Wire Bond)等方式进行。 本实施例也可相互调换步骤（g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 请参考图 2D，为依据本发明多层基板间交互连结结构的制造方法的第二实 施例与第一实施例不同的步骤 (c)、步骤 (d)的结构示意图。除步骤 (c)、步骤 (d) 外， 第二实施例中图 2A、 2B, 图 2E至 21所示其它步骤均与第一实施例相同。 图 2C表示步骤 (c)， 涂布第一介电层 16之前， 在此第二实施例中在区域 17进行附着强化处理， 以增加第一介电层 16与步骤 (b)中所涂布第一介电层 19 间的附着强度， 可更进一步在后面图 2D所表示的步骤 (d)中维持固接的状态， 减低介电层间分离、 或变形导致不密接情形的发生可能性， 从而提高制程良率。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 图 3C至 ' 3G为依据本发明多层基板间交互连结结构的制造方法的第三实施 例与第一实施例不同的步骤 (c)至步骤 (g)的结构示意图。 除前述步骤外， 第三 实施例中图 3A、 3B所示步骤均与第二实施例相同。 图 3C表示步骤 (c)， 涂布第一介电层 16之前， 在此第二实施例中在区域 17、 17-1进行附着强化处理， 以增加这些区域的附着强度， 可更进一步在后面 图 3D所表示的步骤 (d)中维持固接状态， 减低介电层间分离、 或变形导致不密 接情形的发生可能性， 从而提高制程良率； 执行图 3E表示的步骤 (e)后， 跳过步骤 (e ' )， 直接执行图 3F表示的步骤 (f)， 而不移除与载板相邻的第一介电层 19; 以及 图 3F表示步骤 (f)， 使第一多层基板 300上介电层及与其对应的金属层的 端缘从其它相邻介电层局部及其对应金属层的端缘分离（10与 12、 13与 15、 16 与 18)， 以形成一预备与其它多层基板交互连结的连接部 120， 并移除第一介电 层 19的端缘 19-1， 露出对应该第一介电层 19的第一金属层 18的端缘， 用以预 备在图 3G所示步骤 (g)中， 与另一多层基板（以第二多层基板 400为例）的具分 离端缘的第二金属层 22、 25及 27黏结。 图 3G表示步骤（g)， 将第一多层基板 300的金属层 12、 15及 18的分离端 缘黏结于第二多层基板 400的具分离端缘的金属层 22、 25及 27。 并且， 第二多 层基板 400已相对第一多层基板 300上下倒置， 使这些制造步骤中， 原本和介 电层 20、 23及 26对应， 位于其下方的金属层 22、 25及 27倒置于介电层 20、 23及 26上方， 而第一多层基板 300的金属层 12、 15及 18与第二多层基板 400 的金属层 22、 25及 27间的黏结方式可以浸锡黏结、 以共晶（Eutectic)黏结、 以异方性导电胶（Anisotropic Conductive Film)黏结， 或者以金-金 (Gold- Gold) 黏结、 以金-铜（Gold- Copper)黏结等方式； 以及 图 3H表示步骤 (h)， 对这些多层基板的第二外层面与第一外层面（即上下 层面）以第一芯片元件 100、 第二芯片元件 200、 一第三基板与这些多层基板进 行连结封装。 连结封装的方式， 可以球栅阵列封装 (BGA)、 平面闸格阵列 (LGA)、 针脚栅格阵列封装 (PGA)或打线接合 (Wire Bond)等方式进行。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 图 4A至 4G为依据本发明多层基板间交互连结结构的制造方法的第四实施 例对应步骤 (a)至步骤 (g)的结构示意图。 本发明若干个多层基板间交互连结结构的制造方法第四实施例， 包括下列 步骤： 图 4A表示步骤 (a)， 提供一载板 102用以形成一多层基板（以第一多层基 板 300为例）； 图 4B表示步骤 (b)， 在该载板 102上的表面进行一界面附着强化的处理， 以增加一介电层 104与该载板 102间的附着强度， 并且在硬化该介电层 104后， 再在该介电层 104上的表面， 涂布另一介电层 19; 图 4C表示步骤 (c)， 在该介电层上形成一第一金属层 18及必要的若干个 介层洞 9 (显示于图 4D)后， 再涂布另一第一介电层 16; 图 4D表示步骤 (d)， 重复步骤 (c)， 形成第一多层基板 300， 但是， 在此实 施例中的区域 17、 17- 1未进行附着强化处理； 图 4E表示步骤 (e)， 沿分离端缘（即沿着图 4D中的垂直分割线 dl、 d2)分 割载板沿区域 119 (显示于图 4C)及其对应的多层基板的端缘 120，并从第一介电 层 19与介电层 104 (显示于图 4B)间，将第一多层基板 300从载板 102 (显示于图 4B)剥离； 图 4F表示步骤 (V )， 移除第一介电层 19， 露出对应第一介电层 19的第 一金属层 18; 图 4G表示步骤 (f)， 使第一多层基板上介电层及与其对应的金属层的端缘 各从其它相邻介电层局部及其对应金属层的端缘分离（10与 12、 13与 15、 16与 18)， 以形成一预备与其它多层基板交互连结的连接部 120; 图 4H表示步骤 (g)， 将第一多层基板 300的金属层.12、 15及 18的分离端 缘黏结于第二多层基板 400的具分离端缘的金属层 22、 25及 27。 并且， 第二多 层基板 400已相对第一多层基板 300上下倒置， 使这些制造步骤中， 原本和介 电层 20、 23及 26对应， 位于其下方的金属层 22、 25及 27倒置于介电层 20、 23及 26上方， 而第一多层基板 300的金属层 12、 15及 18与第二多层基板 400 的金属层' 22、 25及 27间的黏结方式可以浸锡黏结、 以共晶（Eutectic)黏结、 以异方性导电胶（Anisotropic Conductive Film)黏结、 或者以金-金（Gold-Gold) 黏结、 以金-铜（Gold- Copper)黏结等方式， 以完成本发明多层基板间交互连结 的结构； 以及 图 41表示步骤 (h)， 对这些多层基板的第二外层面与第一外层面（即上下 层面）以第一芯片元件 100、 第二芯片元件 200、 一第三基板与这些多层基板进 行连结封装。 连结封装的方式， 可以球栅阵列封装 (BGA)、 平面闸格阵列（LGA)、 针脚栅格阵列封装 (PGA)或打线接合 (Wire Bond)等方式进行。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 图 5D为依据本发明多层基板间交互连结结构的制造方法的第五实施例与 第四实施例不同的步骤 (c>、 步骤 (d)的结构示意图。 除步骤 (c)、 步骤 (d)外， 第五实施例中图 5A、 5B, 图 5E至 51所示其它步骤均与第四实施例相同。 图 5C表示步骤 (c)， 涂布第一介电层 16之前， 在此第二实施例中在区域 17进行附着强化处理， 以增加第一介电层 16与歩骤 (b)中所涂布第一介电层 19 间的附着强度， 可更进一步在后面图 5D所表示的步骤 (d)中维持固接的状态， 减低介电层间分离、 或变形导致不密接情形的发生可能性， 从而提高制程良率。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 图 6C至 6G为依据本发明多层基板间交互连结结构的制造方法的第六实施 例与第四实施例不同的步骤 (c)至步骤 (g)的结构示意图。 图 6C表示步骤 (c)， 涂布介电层 16之前， 在此第六实施例中在区域 17、 17 - 1进行附着强化处理， 以增加这些区域的附着强度， 可更进一步在后面图 6D 所表示的步骤 (d)中维持固接的状态， 减低介电层间分离、 或变形导致不密接情 形的发生可能性， 从而提高制程良率； 执行图 6E表示的步骤 (e)后， 跳过步骤 (e ' )， 直接执行图 6F表示的步骤 (f)， 而不移除与载板相邻的第一介电层 19; 以及 . 图 6F表示步骤 (f)， 使第一多层基板 300上介电层及与其对应的金属层的 端缘从其它相邻介电层局部及其对应金属层的端缘分离（10与 12、 13与 15、 16 与 18)， 以形成一预备与其它多层基板交互连结的连接部 120， 并移除第一介电 层 19的端缘 19-1， 露出对应该另一介电层 19的第一金属层 18的端缘， 用以预 备在图 6G所示步骤 (g)中， 与另一多层基板（以第二多层基板 400为例）的具分 离端缘的第二金属层 22、 25及 27黏结。 图 6G表示步骤 (g)， 将第一多层基板 300的金属层 12、 15及 18的分离端 缘黏结于第二多层基板 400的具分离端缘的金属层 22、 25及 27。 并且， 第二多 层基板 400已相对第一多层基板 300上下倒置， 使这些制造步骤中， 原本和介 电层 20、 23及 26对应， 位于其下方的金属层 22、 25及 27倒置于介电层 20、 23及 26上方， 而第一多层基板 300的金属层 12、 15及 18与第二多层基板 400 的金属层 22、 25及 27间的黏结方式可以浸锡黏结、 以共晶（Eutectic)黏结、 以异方性导电胶 (Ani sotropic Conductive Fi lm)黏结、 或者以金-金 (Gold- Gold) 黏结、 以金-铜 (Gold- Copper)黏结等方式； 以及 图 6H表示步骤 (h)， 对这些多层基板的第二外层面与第一外层面（即上下 层面）以第一芯片元件 100、 第二芯片元件 200、 一第三基板与这些多层基板进 行连结封装。 连结封装的方式， 可以球栅阵列封装 (BGA)、 平面闸格阵列（LGA)、 针脚栅格阵列封装 (PGA)或打线接合 (Wire Bond)等方式进行。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 图 7D至 71为依据本发明多层基板间交互连结结构的制造方法的第七实施 例与第一实施例不同的步骤 (d)至步骤 (h)的结构示意图。 除前述步骤外， 第七 实施例中图 7A至 7C所示步骤均与第一实施例相同。 图 7D表示步骤 (d)， 重复步骤 (c)， 形成第一多层基板 300， 并且如图中所 示也同时形成相邻第一多层基板 300的第三多层基板 500; 图 7E表示步骤 (e)， 沿分离端缘（即沿着图 7D中的垂直分割线 dl、 d3)完 全分割载板沿区域及其对应的多层基板， 但对 d2仅从芯片起， 分割到最上方的 第一金属层 12及第一介电层 10为止， 并将第一多层基板 300、 第三多层基板 500从载板 102剥离； 图 7F表示步骤 (e ' )， 移除第一多层基板 300、 第三多层基板 500与载板 相邻的第一介电层 19， 露出对应第一介电层 19的第一金属层 18; 图 7G表示步骤 (f)， 使第一多层基板 300上介电层及与其对应的金属层的 端缘各从其它相邻介电层局部及其对应金属层的端缘分离（10与 12、 13与 15、 16与 18)， 以形成一预备与其它多层基板交互连结的连接部 120， 但维持第三多 层基板 500与第一多层基板 300间第一金属层 10与第一介电层 12的连结， 而 第三多层基板 500本身的若干介电层及其对应金属层端缘并未分离； 图 7H表示步骤 (g)， 如同第一实施例， 将第一多层基板 300的金属层 12、 15及 18的分离端缘黏结于第二多层基板 400的具分离端缘的金属层 22、 25及 27， 并且第二多层基板 400及第三多层基板 500也可作连结； 以及 图 71表示步骤 (h)， 对这些多层基板所形成的多层基板间多重交叉连结结 构的上下层面， 以第一芯片元件 100、 第二芯片元件 200、 一第三基板与这些多 层基板进行连结封装。 连结封装的方式， 可以球栅阵列封装 (BGA)、 平面闸格阵 列（LGA)、 针脚栅格阵列封装 (PGA)或打线接合 (Wire Bond)等方式进行。 而与第 一实施例不同的是， 第二芯片元件 200对第三多层基板 500做封装连结。 因此， 本发明的多层基板间多重交叉连结， 可提供更具弹性的交互连结结构的概念。 本实施例也可相互调换步骤 (g)与步骤 (h)的顺序， 而不会改变本发明交互 连结结构或影响其功能。 请参考图 8， 为依据本发明的第一、 第二、 第四以及第五实施例多层基板 间交互连结结构的剖面图。 本发明多层基板间的交互连结结构至少包括一第一 多层基板 300、 一第二多层基板 400。 其中该第一多层基板 300的第一外层面与 一第一芯片元件 100进行连结封装， 该第二多层基板 400的第一外层面与一第 二芯片元件 200进行连结封装。 该第一芯片元件 100与该第二芯片元件 200可 以是逻辑元件、 内存元件、 模拟元件、 光电元件、 微机电元件或发光元件等任 意种类的芯片元件。 该多层基板间的交互连结结构可进一步包括一第三多层基板（图中未显 示）。如图 7所示该第三基板可透过锡球 410与第一多层基板 300进行连结封装； 而透过锡球 420与第二多层基板 400进行连结封装， 或对第一芯片元件或第二 芯片元件进行连结封装。 前述第三基板的封装方式也可采用球栅阵列封装 (BGA)、 平面闸格阵列（LGA)、 针脚栅格阵列封装（PGA)或打线接合 (Wire Bond) 等方式进行。 此外， 第一多层基板 300、 第二多层基板 400及第三基板均可以是软性多 层内连线基板。 而通过本发明多层基板间交互连结的结构可提供可变形或可挠 曲的特性， 从而能作为这些软性多层基板的封装连结。 前述第一多层基板 300包括若干层第一介电层 10、 13及 16， 以及若干层 第一金属层 12、 15及 18。 并且前述第二多层基板 400包括若干层第二介电层 20、 23及 26， 以及若干层第二金属层 22、 25及 27。 因此， 实质上该第一芯片 元件 100 以锡球 110 被封装于第一多层基板 300 的第一介电层 10 的介层洞 (VIA)， 第二芯片元件 200则以锡球 210被封装于第二多层基板 400的第二介电 层 26的介层洞或第二金属层 27。 第一多层基板 300的第一金属层 12及其对接的第一介电层 10两者的端缘、 第一金属层 15及其对接的第一介电层 13两者的端缘， 以及第一金属层 18及其 对接的第一介电层 16两者的端缘， 均各从相邻的第一金属层和对应第一介电层 的端缘相对分离。 相对地， 第二多层基板 400的第二金属层 22及其对接的第二 介电层 20两者的端缘、 第二金属层 25及其对接的第二介电层 23两者的端缘， 以及第二金属层 27及其对接的第二介电层 26两者的端缘， 均各从其相邻第二 金属层和第二介电层的端缘相对分离。 当该第一多层基板 300与该第二多层基板 400之间作相互连结时， 将该第 二多层基板 400上下倒置， 该第二多层基板 400的第二金属层 22、 25及 27的 分离端缘会分别与该第一多层基板 300的第一金属层 12、 15及 18的各个分离 端缘相互黏结， 以形成如图 7所示该交互连结结构中的一连结部 120。其黏结方 式可以黏结剂 1、 2、 3 黏结、 以浸锡黏结） 、 以共晶（Eutectic)黏结、 以异方 性导电胶（Anisotropic Conductive Fi lm)黏结， 或者以金-金 (Gold- Gold)黏结、 或以金 -铜 (Gold- Copper)黏结等方式。 透过这些交互黏结方式， 该第二金属层 22、 25及 27便与第一金属层 12、 15及 18相互连结成一体。通过这一多层基板 间交互连绮的结构， 即能达成第一芯片 100与第二芯片 200间的直接互连。 与现有技术未将这些多层基板介电层及对应的各金属层相对分离而直接 进行封装的结构比较， 由于第一多层基板 300与第二多层基板 400间， 利用基 板的分离端缘进行交互连结， 因此能有效地进一步提升封装密度并使***微型 化， 并且能更进一步地提供任意可变形或可挠曲的特性， 从而可作为软性封装 的***应用。 此外， 在图 7中， 这些介电层间， 进行了一种界面附着强化处理， 处理区 域 11、 14、 21 以及 24以粗黑线表示。 特别值得注意的是， 由于除了这些基板 分离端缘以外的其它区域 (连结部 120 以外的这些介电层间）， 均进行了界面附 着强化处理， 以增加这些介电层间的附着强度， 而未进行该界面附着强化处理 的端缘 (连结部 120内）， 便能轻易地使任意介电层端缘及其对应的金属层端缘， 与其它端缘相对分离。 前述多层基板端缘分开的方式可利用双面胶带 (例如： UV tape) , 对贴于 第一多层基板 300或第二多层基板 400的第一外层面与第二外层面， 再撕开胶 带， 则胶带将顺势带开未进行该界面附着强化处理的端缘。 重复多次对贴与撕 开胶带的动作， 便能分开多层未附着强化的端缘， 但金属层 12、 15、 18、 22、 25及 27会分别与介电层 10、 13、 16、 20、 23及 26相连。 通过这一介电层 /介 电层间选择性的界面附着强化处理概念， 即能完成本发明第一多层基板 300 或 第二多层基板 400 间交互连结的结构。 例如： 本发明中的这些介电层的材料为 聚酰亚胺 (Polyimide) , 则便能利用一氧气或氩气电桨制程处理， 进行前述界面 附着强化的处理。 图 8为依据本发明的第三实施例、第六实施例多层基板间交互连结结构的 剖面图。 与第一、 第二、 第四以及第五实施例中多层基板间的交互连结结构不 同的是， 由于封装形式不同， 前述步骤 (c)涂布另一介电层之前， 在区域 17 - 1 进行附着强化处理， 此后改变第三基板的焊垫 (Pad)形式， 作为不同连结运用的 选择。 本发明的这些实施例中， 虽以第一多层基板 300的各金属层 12、 15及 18 与第二多层基板 400各第二金属层 22、 25、 27间进行一对一相对的黏结为例， 但并非以此为限， 也可采用选择性的黏结或一对多基板连结。 与现有技术相比， 本发明所提供的多层基板间交互连结的结构及其制造方 法， 能使若干个任意种类的芯片元件间透过封装各个芯片的各个多层基板间的 交互连结结构直接互连， 无须经由第三基板， 并且该交互连结结构能进一步提 升封装密度并使***微型化。 此外， 本发明的多层基板间交互连结结构更进一 步地提供了可变形或可挠曲的特性， 从而可作为软性***应用。 相较于现有技 术， 无论是有关芯片与芯片间的封装， 或多层基板间的连结封装， 本发明均更 具有高整合性、 高封装密度的***级封装能力。

Claims

权 利 要 求
1.一种多层基板间交互连结结构的制造方法，每一多层基板具有若干个相互 交叠的金属层与若干个介电层， 其特征在于该制造方法包括下列步骤：
使每一多层基板上至少一介电层及与其对应的金属层的端缘各从其它相 邻介电层局部及其对应金属层的端缘分离； 以及
将其中一多层基板的该至少一介电层的分离端缘黏结于另一多层基板的 具分离端缘的金属层， 以完成这些多层基板间交互连结的结构。
2. 如权利要求 1所述的制造方法， 其特征在于： 在分离步骤之前， 进一步 包括提供一载板用以形成其中一多层基板这一步骤 (a)。
3. 如权利要求 2所述的制造方法， 其特征在于： 其中形成该多层基板包括 下列步骤：
(b)在该载板上的表面， 涂布一介电层；
(c)在该介电层上形成一金属层及必要的介层洞后， 再涂布另一介电层；
(d)重复步骤 (c)， 形成该多层基板； 以及
(e)沿该分离端缘分割出该载板沿区域及其对应的多层基板， 并将该多层 基板从该载板剥离。
4. 如权利要求 3所述的制造方法. 其特征在于:在步骤 (b)中， 进一步包括 在该载板的端缘， 进行一界面附着强化的处理这一步骤， 以增加该介电层对应 该载板沿区域与该载板间的附着强度。
5. 如权利要求 3所述的制造方法， 其特征在于:在步骤 (b)中， 进一步包括 在该载板上的表面进行一界面附着强化的处理， 以增加该介电层与该载板间的 附着强度， 并且在该介电层上的表面， 再涂布另一介电层这一步骤。
6. 如权利要求 5所述的制造方法， 其特征在于该界面附着强化处理为一电 浆制程处理。
7. 如权利要求 5所述的制造方法， 其特征在于： 在步骤 (e)中， 从该介电层 与该另一介电层间， 将该多层基板从该载板剥离。
8. 如权利要求 3所述的制造方法， 其特征在于： 进一步包括一步骤 (e ' )， 即移除与该载板相邻的介电层， 露出对应该介电层的该金属层。
9. 如权利要求 3所述的制造方法， 其特征在于： 在步骤 (c)中涂布该介电层 前， 进一步包括在该介电层对应该载板沿区域的表面上进行一界面附着强化处 理这一步骤，以增加该介电层对应该载板沿区域与步骤 (b)中所涂布该介电层间 的附着强度。
10. 如权利要求 9所述的制造方法， 其特征在于： 进一步包括一步骤 (e， ）， 即移除与该载板相邻的介电层， 露出对应该介电层的该金属层。
11. 如权利要求 3所述的制造方法， 其特征在于： 在步骤 (c)中涂布该介电 层前， 进一步包括在该金属层表面及该介电层表面的端缘以外的其它区域进行 一界面附着强化处理这一步骤， 以增加该其它区域的附着强度。
12. 如权利要求 11所述的制造方法， 其特征在于： 在步骤 (e)后， 进一步包 括移除与该载板相邻介电层的分离端缘， 露出对应该介电层的该金属层的端缘 这一步骤。
13. 如权利要求 1所述的制造方法， 其特征在于： 在黏结的步骤之后， 进一 步包括对这些多层基板的第二外层面与第一外层面进行连结封装这一步骤。
14. 如权利要求 13所述的制造方法， 其特征在于该连结封装连结若干个芯 片元件、 一第三基板与这些多层基板。
15. 如权利要求 1所述的制造方法， 其特征在于： 在黏结的步骤之前， 进一 步包括对这些多层基板的第二外层面与第一外层面进行连结封装这一步骤。
16. 如权利要求 15所述的制造方法， 其特征在于该连结封装连结若干个芯 片元件、 一第三基板与这些多层基板。
17. 一种多层基板间的交互连结结构包括一第一多层基板以及一第二多层 基板,该第一多层基板具有若干个相互交叠的第一金属层与若千个第一介电层， 该第二多层基板具有若干个相互交叠的第二金属层与若干个第二介电层， 其特 征在于：
该第一多层基板的至少一第一金属层的端缘与其对应的第一介电层的 端缘相连接， 而与其它相邻第一金属层和第一介电层的端缘相对分离； 该第二 多层基板的至少一第二金属层的端缘与其对应的该第二介电层的端缘相连接， 而与其它相邻第二金属层及第二介电层的端缘相对分离； 该第一多层基板的至 少一第一金属层与该第二多层基板的至少一第二金属层相互黏结以形成一连结 部。
18. 如权利要求 17所述的交互连结结构， 其特征在于该第一多层基板的介 电层的分离端缘以外的其它区域， 进行了一界面附着强化处理， 以增加这些介 电层间的附着强度。
19. 如权利要求 18所述的交互连结结构， 其特征在于该界面附着强化处理 为一电浆制程处理。
20. 如权利要求 19所述的交互连结结构， 其特征在于这些介电层的材料为 聚酰亚胺。
21. 如权利要求 17所述的交互连结结构， 其特征在于这些介电层的材料为 聚酰亚胺。
22. 如权利要求 17所述的交互连结结构， 其特征在于该第二多层基板的介 电层的分离端缘以外的其它区域， 进行了一界面附着强化的处理， 以增加这些 介电层间的附着强度。
23. 如权利要求 22所述的交互连结结构， 其特征在于该界面附着强化处理 为一电浆制程处理。
24. 如权利要求 23所述的交互连结结构， 其特征在于这些介电层的材料为 聚酰亚胺。
25. 如权利要求 22所述的交互连结结构， 其特征在于这些介电层的材料为 聚酰亚胺。
26. 如权利要求 17所述的交互连结结构，其特征在于:进一步包括一第一芯 片元件， 用以对该第一多层基板的第一外层面进行连结封装。
27. 如权利要求 26所述的交互连结结构， 其特征在于该第一芯片元件是逻 辑元件、 内存元件、 模拟元件、 光电元件、 微机电元件以及发光元件之中的任 一元件。
28. 如权利要求 26所述的交互连结结构， 其特征在于： 进一步包括一第三 基板， 用以对该第一芯片元件进行连结封装。
29. 如权利要求 17所述的交互连结结构， 其特征在于： 进一步包括一第二 芯片元件， 用以对该第二多层基板的第一外层面进行连结封装。
30. 如权利要求 29所述的交互连结结构， 其特征在于该第二芯片元件是逻 辑元件、 内存元件、 模拟元件、 光电元件、 微机电元件以及发光元件之中的任 一元件。 .
31. 如权利要求 29所述的交互连结结构， 其特征在于： 进一步包括一第三 基板， 用以对该第二芯片元件进行连结封装。
32. 如权利要求 17所述的交互连结结构， 其特征在于： 进一步包括一第三 基板， 用以对该第一多层基板或该第二多层基板进行连结封装。
33. 如权利要求 32所述的交互连结结构， 其特征在于该第三基板为一软性 基板。
34. 如权利要求 17所述的交互连结结构， 其特征在于该第一多层基板为一 软性基板。
35. 如权利要求 17所述的交互连结结构， 其特征在于该第二多层基板为一 软性基板。
36. 一种多层基板包括若干个金属层，若干个与这些金属层相互交叠的介电层， 其特征在于： 至少一金属层的端缘与其对应的介电层的端缘相连接， 与其它相 邻金属层和介电层的端缘相对分离， 该至少一金属层与其它多层基板的至少一 金属层相互黏结以形成一连结部。
PCT/CN2007/000378 2007-02-05 2007-02-05 Procédé pour la fabrication d'une structure d'assemblage commune entre des panneaux multicouche et structure associée WO2008095337A1 (fr)

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