TW201121008A - Stack package structure and package substrate thereof - Google Patents

Stack package structure and package substrate thereof Download PDF

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Publication number
TW201121008A
TW201121008A TW98140939A TW98140939A TW201121008A TW 201121008 A TW201121008 A TW 201121008A TW 98140939 A TW98140939 A TW 98140939A TW 98140939 A TW98140939 A TW 98140939A TW 201121008 A TW201121008 A TW 201121008A
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Taiwan
Prior art keywords
package
electrical
substrate
electrical connection
substrate body
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TW98140939A
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Chinese (zh)
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TWI394251B (en
Inventor
Che-Min Chu
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Unimicron Technology Corp
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Priority to TW98140939A priority Critical patent/TWI394251B/en
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Publication of TWI394251B publication Critical patent/TWI394251B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A package substrate for package on package; POP/stack packages use is disclosed, comprising a substrate body whereon a chip mounting area is defined and having second electrical connecting pads formed on the periphery of the chip mounting area; an insulating protection layer disposed on the substrate body and formed with a curved groove for corresponding to a respective second electrical connecting pad and having a small hale formed therein; and an electrical contact pad disposed in the curved groove and the small hole for allowing the contact pads to electrically connect to second electrical connecting pads. By forming electrical contact pads on the outer periphery of the second electrical connecting pads covered underneath the protection layer and further forming curved grooves on the electrical contact pads, the problem of detaching solder balls and bridging in the subsequent solder reflow process can be prevented.

Description

201121008 六'發明說明： 【發明所屬之技術領域】 本發明係有關一種封裝結構，尤指一種具有較高之植 焊球良率之堆疊封裝結構及其封裝基板。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure, and more particularly to a package structure having a high solder ball yield and a package substrate thereof. [Prior Art]

Ik著電子產業的蓬勃發展，電子產品也逐漸邁向多功 能、向性能的趨勢。而為了滿足半導體封裝件高整合度 (integration )及微型化（miniaturizati〇n )的封裝需求， 以供更多主、被動元件及線路載接，半導體封裝基板亦逐 漸由雙層電路板演變成？層電路板（multi_layerbGard)， 以在有限的空間下運用層間連接技術（interlayer connectiGn)來擴大半導體封裝基板上可供利用的線路佈局 =積’並配合高線路密度之積體電路（integrated circuit) 需要’而能達到封料輕薄短小及提高電性功能之目的。 ;、、;'而由於外露於封裝基板最外層的電性接觸塾的周 圍通常仍佈設有線路，必須以如綠漆之防焊層同時覆 蓋於該線路與電性的部分表面上，並於該防焊層形 成有外露部分紐接觸㈣防焊層開孔，而該防焊: 以保護線路層及電性接㈣部分表面μ外界環境之㈠ 與水氣影響而氧化。但是，隨著封裝基板中的線路愈= 細1性接觸塾間之間距也越來越小，藉以符合細線= (finelme)、細間距（finepitch)的使用要求，佳 = 現今曝光顯影技術的瓶頸，如欲形成較小之防焊屌 ； 顯露電性接觸塾之部分表面，常有對位不準及曝 】11415 201121008 不佳’甚而造成防焊層開孔 題；為此，該防焊層開孔面2疋顯路開孔不完整等問 接觸面軌以凸塊轉球，=寸過小而無法提供足夠的 層線路層之介電層（絕緣保^業界遂發展出-種於該增 觸塾的技術，以克服上述問蹲"）上直接形成外部電性接 前述技術的習知封裝基板製C第1圖，係為運用 圖。 欠堆®封裝結構的剖視示意 如第1圖所示，習知堆4 I、 半導體晶片3、封裝材4、、裝結構係包括：封裝基板 所述之封震基板W'C置5。 II、 以及電性接觸墊13。所冰土板本體10、絕緣保護層 之第-及第二表面心姆，：：基板本體1〇係具有相對 電性連接墊104及複數位於該2 一表面10a上具有第一 第二電性連接塾1〇2,且於電性連接塾104周圍之 球塾1〇3。又該基板树1〇 ; ⑽上具有複數植 >盲孔ΚΠ，且該等導電盲孔⑼有1數内層線路⑽及導電 與該等第二電性連接塾1〇電性連接該等内層線路100 該基板本體1G之第-及第二^之絕緣保護層11係設於 表面10a上之絕緣保護層：面1:以’且於該第- 孔一令各該開口心二複， 而令各該第1孔„2a㈣各^^二電性連接墊⑽ μ 〜各該弟一電性連接墊104。又 弟一表：】0b上之絕緣保護層π 广以令各該植球墊】〇3對應外露各 俾供接置焊球14。所述 厂弟一開孔112b， 电性褛觸墊13係設於各該開口 111415 201121008 :中又觸塾13電性連接該第二電性連接塾 il接觸墊13之上表面13a係呈平面。 斤返之半導體晶片3設於該絕緣保護層卜0 φ 連接該第1性連接墊104。 11上且電性 曰片封裝材4係形成於該絕緣保護層11與半導體 曰曰乃j之間。 所述之電子裝置5係結合於該基板本體1〇之第 面！〇a之絕緣保護層n上方，該電子袭置$上 電性接觸塾13之焊球5。，以令該焊球5〇結合增：： 觸墊13上’俾使該電子裝置5電性連接該基板本體。 惟，習知技術係於原有的第二電性連接塾1〇2上 緣保護層11表面分卿成封裝基板外部電性接觸塾13、， 由於封裝基板最外表面絲佈設線路層，故其最外表面不 再另外施加防焊層’而可完全顯露電性接輕13表面，藉 以避免原本於防焊層開孔以顯露電性接觸塾部分之表^ 時，會有對位不準及曝先解析度不佳、甚而造成防焊層開 孔偏移或是顯露開孔不完整等問題；但由於習知技術並未 有防焊層開故將該焊球50結合於該電性接觸塾^之 表面時，於回焊過程中’會使該焊球％呈現液態，而導致 焊料因無防焊層開孔之區域航而產生溢流；又由於該電 ^接觸塾13之上表面13&平整1無防焊層開孔侷限-空 =，易使該焊球5G產生脫落掉球的情况，並使得結合該焊 之製料易進行，_造賴焊球脫落或焊料溢流導 致橋接等問題。 111415 6 201121008 因此，如何避免習知技術t外部之 层 =的脫落或谭料溢流導致橋接等問二= 目刖亟右人解決的課題。 【發明内容】 祖一 rrt”知技狀翻缺失，轉明之—目的係提 ^強線路與介電層之結合力且滿足線路細間距需 求之堆疊封裝結構及其封裝基板。 π本發明之另—目的係提供—種能降低製造成本之堆 璧封裝結構及其封裝基板。 為，上述及其他目的，本發明揭露一種封裝基板，係 用於堆璺封裴（Packa§e on package，POP)，包括：基板 本體，係具有相對之第-及第二表面，於該第-表面I且 有置晶區，且該置晶區中具有複數第一電性連接墊，並於 該置晶區周有複數第二電性連接塾，而於該第二表面 j具有複數植球墊；絕緣保護層，係設於該基板本體之第 H表面上’且於該第—表面上之絕緣保護層中設有 複數弧狀凹槽及第―開孔’以令各該弧狀凹槽對應各該第 二電性連祕，而令各該第—開孔對應各該第―電性連接 墊，並於各祕狀凹槽中設有複數微孔，令該第二電性連 =墊之部份表面外露於該等微孔中；以及電性接觸塾，係 6又=各該弧狀凹槽及微孔中，以令該電性接㈣電 該第二電性連接墊。 、曾前述之封裝基板中，該基板本體具有複數内層線路及 ¥電盲孔，且該等導電盲孔電性連_等内層線路與該等 111415 7 201121008 第二電性連接塾。 剛迷之封裝基板中’該電性接觸墊之外表面係呈弧 狀，且形成該電性接觸墊之材料係為銅。 、前述之封裝基板中，該第二表面上之絕緣保護層 中形 成有複數第—開孔，以令各該植球墊對應外露各該第二開 孔。 本發明復揭露—種堆疊封裝（package on package， )^構係包括.基板本體，係具有相對之第一及第 :表面’於該第-表面上具有置晶區，且該置晶區中具有 複數第f性連接堅，並於該置晶區周圍具有複數第二電 ^連接墊’而於該第三表面上具有複數植㈣；絕緣保護 f，係設於該基板本體之第-及第二表面上’且於該第- 之絕、，!：保4層中設有複數弧狀凹槽及第—開孔，以 ^ =弧狀凹槽對應各該第二電性連接塾，而令各該第-開孔對應各該第一雷性車垃 複數和丨，A . 4㈣於各祕狀凹槽中設有 φ γ β ，7該第二電性連接墊之部份表面外露於該等微 該電性!墊、，係設:各該弧狀凹槽及微孔中’以令 π 連接該第二電性連接塾；半導體晶片， :臭區上之絕緣保護層上；以及電子裝置，結合於 δ亥基板本體之第一矣 口％ 有對庫兮+μ '"面之、、，邑、濠保護層上，該電子裝置上具 有子應該％性接觸藝 觸塾該電性接 ’該基板本體具有複數内層& 该寺V-电盲孔電性連接該等内層線路與 111415 8 201121008 該等第二電性連接墊。 !Τ故月〗（之堆⑧封裝結構中’該電性接觸塾之外表面係呈 弧狀，且形成該電性接觸塾之材科係為銅。又該: 上之絕緣保護層中形成有複數第二 ° 、 對應外露各㈣二開孔。 開孔，以令各該植球塾 前述之堆疊封裝結構中，該半 電性連接該第-雨性、車技轨, ^ U I晶方式 電凸塊，俜μ > ^ $ 。別述之封裝結構復包括導 ㈣第:開孔中’以令該導電&塊電性連 電险連接墊及半導體晶片， 形成於該絕緣保護層與半導體晶片之^復包括封裝材，係 另外，於另一實施例中，該曰 性連接該第-電性連接墊，且=;曰^錯由導線電 絕緣保護層與該半導體晶片之間。括縣材，係形成於該 封裂之堆細裝結射，該電子W路板或另- #覆蓋於該封裝基板係於 部之電性接觸部之第二電性連接塾上對應形成外 的導電盲孔以電性連:内層線路係藉由設於該基板本體中 觸塾，又該外部之 ^第一電性連接塾及外部之電性接 後續於該外部之電姑觸塾之表面具有弧形凹部，因而 壞，該焊球與外部 塾上經回痒後結合電子裝置之焊 球與外部之電 =性接觸墊的接觸面積較大，使該禪 脫落之情形。再者，f之間的接著力較強，而不易有焊球 德形凹部也會限制該焊球的移動範 9 r S1 Π1415 201121008 圍5使得各料球不轉球、或因彼此接觸“成橋接等 問題。故相較於習知技術，本發明之堆疊封裝結構具有能 增進植焊狀加I製程的良率，並有利於細間雜之產品設 計等優點。 【實施方式】 、以下糟由知夂的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2G圖，係揭露本發明之一種堆疊封 裝（package on package，POP)結構之製法。 如第2A圖所示’提供一具有相對之第一及第二表面 20a，20b之基板本體2〇，於該第一表面2如上具有置晶區 A ’且該置晶區a中具有複數第—電性連接整綱，並於 該置晶區A周圍具有複數第二電性連接塾加，而於該第 二表面20b上具有複數植球墊2〇3。又該基板本體2〇具有 複數内層祕200及導電盲孔2G1，且料導電盲孔2〇1 電性連接該等内層線路勘與該等第二電性連接塾撕。 如第2B圖所示，於該基板本體2〇之第一及第二表面 20a，20b上形成絕緣保護層21。 如弟2C圖所示’於該第—表面咖上之絕緣保護層 2!中形成複數弧狀凹槽則及第—開孔2仏，以令各該弧 狀凹槽21G對應各該第二電性連接塾202，而令各該第一 開孔212a對應各該第一電性造姐 乐电改連接墊2〇4;於各該弧狀凹槽 2Κ)中形成複數微孔211，令該第二電性連接塾加之部份 111415 201121008 表面外露於該等微孔211中。另外，於該第二表面2叽上 之絕緣保護層21中形成複數第二開孔212b，以令各該植 球墊203對應外露各該第二開孔212b。 如第2D圖所示，於該絕緣保護層21上形成阻層 且於該阻層22中形成複數開口區22〇，以令各該弧狀凹槽 210對應外露於各該開口區220。又選擇性地令該第一開孔 212a外露於該開口區220。 如第2E圖所示，於各該開口區22〇、位於開口區22〇 中之弧狀凹槽210、及位於弧狀凹槽21〇中之該等微孔2ΐι 中形成電性接觸墊23，令該電性接觸墊23電性連接該第 二電性連接塾202。其中，該電性接觸|23之外表面… 係呈弧狀，且形成該電性接觸墊23之㈣係為鋼。 又可於位於開口區220中之第—開孔仙中形成導 電凸塊24，以令該導電凸塊24電性連接該第—電性 墊 204。 如第2F圖所示，_該阻層22，以完成堆 構所用之封裝基板2 ;所述之封裝基板2係包括 ^ 體20、絕緣保護層21、以及電性接觸墊乃。土板尽 所述之基板本體2G係具有相對之第— 20a,20b，於該第-表面2〇a上具有置晶區a，且該、 A中具有複數第-電性連接塾2()4，並於該置晶區a : 具“㈣二電性連接墊2G2，而於該第二表面咖上且 有複數植球墊203。又該基板本體2〇具有複數 /、 及導電盲孔20卜且該等導電盲 e線路200 今等孔201電性連接該等内層 111415 11 201121008 線路200與該等第二電性連接塾2〇2。 所述之絕緣保護層21係設於該基板本體2〇之第一及 第二表面20a，20b上，且於該第一表面2〇a上之絕緣保護 層21中具有複數弧狀凹槽21〇及第一開孔2Ua，以令各 該弧狀凹槽21〇對應各該第二電性連接塾2〇2，而令各該 第-開孔黯對應各該第一電性連接塾204,並於各該弧 狀凹槽210中設有複數微孔211，令該第二電性連接塾加 之部份表面外露於該等微孔211中。又該第二表面勘上 保護層21 +形成有複數第二開孔勝以令各該 球备203對應外露各該第二開孔212b。 孔2H斤二觸塾23係設於各該弧狀凹槽210及微 墊202。又該電:接塾23電性連接該第二電性連接 成該電性接觸塾Μ 3之外表面Ma係呈弧狀，且形 々與墊23之材料係為鋼。 上之絕緣保護層2] „第2F圖之製程，於該置晶區A 體20之第叹置半導體晶片3，再於該基板本 間形成縣與铸體晶片3之 一電子震置5，該半電導子及基板本體20之上方結合 之焊球50，以八 、上具有對應該電性接觸墊23 完成所述之堆‘封：：5〇電性連接該電性接觸墊23，俾 所述之封裝基板導二作。、該，封裝結構係包括 置5。 日日 、封裳材4、以及電子裝 111415 12 201121008 ·· 所述之半導體晶片3設於讀 21上，且該半導體晶片3係以港b日日°1上之絕緣保護層 性連接墊2 G 4，即藉由設於各^ aS_方式電性連接該第-電 塊24經回焊製程形成烊球24，，以“開孔212a中之導電凸 接墊204及半導體晶片3。 ：<電性連接該第一電性連 所述之封裝材4係對應該置s 護層21與該半導體晶片3之間。Β‘Α而形成於該絕緣保 所述之電子裝置5係 係結合於該基板本體20之第〜、'、冑路板或另一封裝結構， 上方，該電子裝置5上具有^2:a之絕緣保護層21 5〇’以令該焊球50結合至該‘：以接觸墊”之烊球 J2. ™ 生接觸塾23上，梭伯兮； 子裝置5電性連接該基板本體扣。 3上俾使該電 如第2G’圖所示，係為本 構；本實施例與上述實施例X $一種堆疊封裳結 係藉由導線30紐連接^相録於該半導體晶片3 材4,係形成於該絕緣連㈣204,且該封裝 及導線3〇 ;故於第2D及上:包覆該半導體晶片3 仙中可不形成導電凸塊。目之1程中，於該第一開孔 於該絕緣保:層疊=構之封裝基板係於覆蓋 電性接觸塾，且該…=二連接塾上對應形成外部之 電盲孔以電性連接至k if由^於該基板本體中的導 塾，又該外部之電性接觸塾之/面接且塾右及/卜部之電性接觸 續於該外部之電性接職有^凹部’因而後 & 口烊後結合電子裝置之焊 111415 13 201121008 球，該焊球與外部之電性接觸墊的接觸面積較大5使該焊 球與外部之電性接觸墊之間的接著力較強，而不易有焊球 脫落之情形。 再者，該弧形凹部也會限制該焊球的移動範圍，使得 各該焊球不易掉球、或因彼此接觸而造成橋接等問題。故 相較於習知技術，本發明之堆疊封裝結構具有能增進植焊 球之加工製程的良率並有利於細間距之產品設計等優點。 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單説明】 第1圖係為習知堆疊封裝結構之剖視示意圖；以及 第2A至2G圖係為本發明堆疊封裝結構之製法之示 意圖；其中，第2G’圖係為第2G圖之另一實施例之示意圖。 【主要元件符號說明】 1、2 封裝基板 10、20 基板本體 10a、20a 第一表面 10b、20b 第二表面 100、200 内層線路 101 ' 201 導電盲孔 102、202 第二電性連接墊 14 111415 201121008 :103 、 203 104 、 204 11、21 110 112a > 212a 112b ' 212b 13 ' 23 13a φ 14、· 24,、50 210 211 22 220 23a 24 3 30 4、4， 5Ik is booming in the electronics industry, and electronic products are gradually moving toward versatility and performance. In order to meet the high integration and miniaturization requirements of semiconductor packages for more active and passive components and line carriers, semiconductor package substrates have gradually evolved from two-layer boards. Layer board (multi_layerbGard), which uses the interlayer connection technology (interlayer connectiGn) in a limited space to expand the available circuit layout on the semiconductor package substrate = product' and meet the high circuit density of the integrated circuit. 'It can achieve the purpose of light and thin sealing material and improve electrical function. ;,;; and because the circuit is usually disposed around the electrical contact 外 exposed on the outermost layer of the package substrate, it must be covered with the solder resist layer such as green lacquer on both the surface and the electrical surface. The solder resist layer is formed with an exposed portion of the contact (4) solder mask opening, and the solder resist: is oxidized by the protection of the circuit layer and the electrical interface (4) of the surface of the external environment (1) and the influence of moisture. However, as the lines in the package substrate become thinner, the distance between the first and second contacts is smaller and smaller, so as to meet the requirements of fine line = (finelme) and fine pitch (finepitch), good = bottleneck of current exposure development technology If you want to form a small solder mask; expose some of the surface of the electrical contact ,, often misalignment and exposure] 11415 201121008 poor 'even good cause of the solder mask opening problem; for this, the solder mask Opening surface 2 疋 路 开 不 不 等 等 等 等 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 = = = = = = = = = = The technique of the touch is to overcome the above-mentioned problem, and the first package of the conventional package substrate C which directly forms the external electrical connection technology is used. Cross-sectional view of the under-stacked package structure As shown in Fig. 1, the conventional stack 4 I, the semiconductor wafer 3, the package 4, and the package structure include a package substrate W'C. II, and an electrical contact pad 13. The slab body 10, the first and second surface of the insulating protective layer, the substrate body 1 has a relatively electrical connection pad 104 and the plurality of first and second electrodes 10a have a first second electrical property. The port 塾1〇2 is connected to the ball 塾1〇3 around the 塾104. Further, the substrate tree 1〇; (10) has a plurality of implanted blind holes, and the conductive blind holes (9) have a plurality of inner layers (10) and electrically connected to the second electrical connections 塾1〇 electrically connected to the inner layers The first and second insulating protective layers 11 of the substrate body 1G are provided on the surface 10a of the insulating protective layer: the surface 1: is in the first hole, and the opening is doubled, and Let each of the first holes „2a(4) each of the two electrical connection pads (10) μ~ each of the electrical connection pads 104. Also, a table: 】 0b on the insulating protective layer π wide to make each of the ball pads 〇3 corresponds to the exposed 俾 for the soldering ball 14. The factory brother has an opening 112b, and the electrical stroking pad 13 is disposed in each opening 111415 201121008: the contact 塾 13 is electrically connected to the second electric The upper surface 13a of the contact pad 13 is flat. The semiconductor wafer 3 is placed on the insulating protective layer, and the first connection pad 104 is connected to the insulating pad. 11 and the electrical package 4 is attached. Formed between the insulating protective layer 11 and the semiconductor device j. The electronic device 5 is bonded to the first surface of the substrate body 1 Above the layer n, the electrons are placed on the solder ball 5 of the power contact 塾13 to bond the solder balls 5:: The touch pad 13 is electrically connected to the substrate body. However, the conventional technology is based on the surface of the second electrical connection 塾1〇2 upper edge protection layer 11 to form an external electrical contact 塾13 of the package substrate. Since the outermost surface of the package substrate is provided with a circuit layer, The outermost surface of the outer surface is no longer additionally applied with a solder resist layer', and the surface of the electrical contact light 13 can be completely exposed, so as to avoid the surface of the solder resist layer to expose the electrical contact portion, the alignment may be inaccurate. And the problem of poor initial resolution, even causing the opening of the solder resist layer or revealing the incomplete opening; however, the solder ball 50 is bonded to the electrical property because the solder mask is not opened by the prior art. When contacting the surface of the 塾^, during the reflow process, the % of the solder ball will be liquid, which causes the solder to overflow due to the area where the solder mask is not opened; and because the electric contact is above the 塾13 Surface 13 & flat 1 without solder mask opening limitation - empty =, easy to make the solder ball 5G to fall off the ball And making the welding material combined with the welding easy, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Etc. 2 = The subject solved by the right person. [Inventive content] The ancestral rrt" knows the lack of knowledge, and the purpose is to improve the combination of the strong line and the dielectric layer and meet the fine pitch requirements of the line. Stacking the package structure and its package substrate. π Another object of the present invention is to provide a stacked package structure and a package substrate thereof which can reduce manufacturing costs. For the above and other purposes, the present invention discloses a package substrate for use in a stacking package (POP), comprising: a substrate body having opposite first and second surfaces, a surface I having a crystallographic region, wherein the crystallographic region has a plurality of first electrical connection pads, and a plurality of second electrical connections are formed around the crystallographic region, and the plurality of implants are present on the second surface j a ball pad; an insulating protective layer is disposed on the H-th surface of the substrate body; and a plurality of arc-shaped grooves and first opening holes are formed in the insulating protective layer on the first surface to make each of the arcs The groove corresponds to each of the second electrical connection secrets, and each of the first opening holes corresponds to each of the first electrical connection pads, and a plurality of micro holes are disposed in each of the secret grooves, so that the second electrical property is a portion of the surface of the pad = exposed in the micropores; and an electrical contact 塾, the system 6 is in each of the arcuate grooves and the micro holes, so that the electrical connection (four) is electrically connected to the second electrical connection pad. In the above-mentioned package substrate, the substrate body has a plurality of inner layer lines and a plurality of inner blind lines, and the inner conductive lines of the conductive blind holes are connected to the second electrical connection of the 111415 7 201121008. The outer surface of the electrical contact pad is in an arc shape, and the material forming the electrical contact pad is copper. In the above package substrate, a plurality of first openings are formed in the insulating protective layer on the second surface, so that each of the ball pads corresponding to the second openings is exposed. The present invention discloses a package on package structure comprising: a substrate body having opposite first and first surfaces: a crystallized region on the first surface, and the crystallographic region Having a plurality of f-th connection and having a plurality of second electrical connection pads around the crystallized region and having a plurality of implants on the third surface; the insulation protection f is disposed on the substrate body - and The second surface is provided with a plurality of arcuate grooves and a first opening in the layer 4, and the arcuate groove corresponds to each of the second electrical ports. And each of the first opening is corresponding to each of the first lightning vehicle and the plurality of 丨, A. 4 (4) is provided with φ γ β in each secret groove, 7 part of the surface of the second electrical connection pad is exposed In the arc-shaped recesses and the micro-holes, the second electrical connection is connected by π; the semiconductor wafer: the insulating protective layer on the odorous region; And the electronic device, combined with the first port of the δHui substrate body, has a pair of 兮+μ '" face, 邑, 濠 protective layer, the electron The device has a sub-contact, and the electrical contact is provided. The substrate body has a plurality of inner layers & the temple V-electric blind holes are electrically connected to the inner layer lines and 111415 8 201121008 the second electrical connection pads . !Τ故月〗 (In the stack of 8 package structure, the surface of the electrical contact is curved, and the material that forms the electrical contact is copper. Also: formed in the insulating protective layer There are a plurality of second angles, corresponding to the exposed (four) two openings. The holes are opened to make the ball-planting frame in the aforementioned stacked package structure, the semi-electrical connection of the first rain, the car track, ^UI crystal mode The electric bump, 俜μ > ^ $. The package structure includes a guide (4): in the opening, to make the conductive & block electrically connected to the power pad and the semiconductor wafer, formed in the insulating protective layer And the semiconductor wafer comprises a package material, and in another embodiment, the first electrical connection pad is electrically connected, and the fault is electrically insulated between the conductive layer and the semiconductor wafer. The prefabricated material is formed in the sealed stack of fine-junction, and the electronic W-way plate or the other is formed on the second electrical connection port of the electrical contact portion of the package substrate. The outer conductive blind hole is electrically connected: the inner layer is connected to the substrate body, and the outer portion is An electrical connection and an external electrical connection are followed by an arcuate recess on the surface of the external electric contact, and thus the solder ball and the external crucible are combined with the solder ball and the external portion of the electronic device. The contact area of the electric contact pad is large, which makes the zen fall off. Moreover, the adhesion between f is strong, and it is not easy to have a solder ball. The concave shape also limits the movement of the solder ball. 9 r S1 Π1415 201121008 Circumference 5 makes the ball of each material not turn the ball, or contact with each other to "bridge" and the like. Therefore, compared with the prior art, the stacked package structure of the present invention has the advantage of improving the welding-like addition process, and Advantages of the product design and the like are exemplified. [Embodiment] The following describes the embodiments of the present invention by way of specific examples, and those skilled in the art can easily understand other aspects of the present invention from the contents disclosed in the present specification. Advantages and Effects. Referring to Figures 2A to 2G, a method of fabricating a package on package (POP) structure of the present invention is disclosed. As shown in Figure 2A, a first and second surface are provided. The substrate body 2a of 20a, 20b has a crystallizing area A' on the first surface 2, and the plurality of first-electrode connection lines in the crystal-forming area a, and has a plurality of numbers around the crystal-forming area A The second surface 20b has a plurality of ball pads 2〇3. The substrate body 2 has a plurality of inner layers 200 and conductive blind holes 2G1, and the conductive blind holes 2〇1 The inner layer is connected to the second electrical connection and the second electrical connection is torn. As shown in FIG. 2B, an insulating protective layer 21 is formed on the first and second surfaces 20a, 20b of the substrate body 2. 2C shows a plurality of arcuate grooves and a first opening 2仏 in the insulating protective layer 2! on the first surface coffee, so that each of the arcuate grooves 21G corresponds to each of the second electrical properties. Connecting the cymbals 202, so that each of the first openings 212a corresponds to each of the first electrical sorcerer electrical connection pads 2 〇 4; forming a plurality of micro holes 211 in each of the arcuate grooves 2 ,) The second electrical connection plus the portion 111415 201121008 surface is exposed in the micropores 211. In addition, a plurality of second openings 212b are formed in the insulating protective layer 21 on the second surface 2'', so that each of the ball pads 203 correspondingly exposes the second openings 212b. As shown in FIG. 2D, a resist layer is formed on the insulating protective layer 21, and a plurality of open regions 22A are formed in the resist layer 22, so that the arcuate recesses 210 are correspondingly exposed to the respective open regions 220. Optionally, the first opening 212a is exposed to the opening region 220. As shown in FIG. 2E, the electrical contact pads 23 are formed in each of the open regions 22A, the arcuate recesses 210 in the open regions 22A, and the micropores 2ΐ in the arcuate recesses 21〇. The electrical contact pad 23 is electrically connected to the second electrical connection port 202. Wherein, the outer surface of the electrical contact |23 is curved, and the (four) forming the electrical contact pad 23 is steel. The conductive bumps 24 are formed in the first opening in the opening region 220 to electrically connect the conductive bumps 24 to the first electrical pads 204. As shown in Fig. 2F, the resist layer 22 is used to complete the package substrate 2 used in the stack; the package substrate 2 includes a body 20, an insulating protective layer 21, and an electrical contact pad. The substrate body 2G as described in the earth plate has opposite sides 20a, 20b, and has a crystallizing area a on the first surface 2A, and the A has a plurality of first electrical connections 塾 2 () 4, and in the crystal zone a: has "(4) two electrical connection pads 2G2, and on the second surface coffee and has a plurality of ball pads 203. The substrate body 2 has a complex /, and conductive blind holes 20 and the conductive blind e-line 200 is connected to the inner layer 111415 11 201121008 line 200 and the second electrical connection 塾 2 〇 2. The insulating protective layer 21 is disposed on the substrate. The first and second surfaces 20a, 20b of the body 2b and the insulating protective layer 21 on the first surface 2A have a plurality of arcuate recesses 21 and a first opening 2Ua for each The arcuate recess 21 〇 corresponds to each of the second electrical connections 塾 2 〇 2, and each of the first opening 黯 corresponds to each of the first electrical connections 塾 204, and is disposed in each of the arcuate grooves 210 There are a plurality of micropores 211, such that a portion of the surface of the second electrical connection is exposed in the micropores 211. The second surface is coated with a protective layer 21 + formed with a plurality of second openings Each of the ball preparations 203 is adapted to expose the second opening 212b. The hole 2H 2 is disposed in each of the arcuate grooves 210 and the micro pad 202. The electric: the connection 23 is electrically connected to the first The second surface is electrically connected to the outer surface Ma of the electrical contact 塾Μ 3 is arc-shaped, and the material of the shape and the pad 23 is steel. The insulating protective layer on the upper surface 2] „the process of the 2F drawing, The semiconductor wafer 3 of the crystal region A body 20 is slanted, and then one of the county and the casting die 3 is electrically placed on the substrate, and the solder ball 50 is bonded to the semi-conductor and the substrate body 20 to The electrical contact pad 23 is electrically connected to the electrical contact pad 23, and the electrical contact pad 23 is electrically connected to the package substrate. The package structure includes 5. The semiconductor wafer 3 is disposed on the read 21, and the semiconductor wafer 3 is an insulating protective layer connection pad 2 on the port b. G 4, that is, the ball 24 is formed by the reflow process by electrically connecting the first block 24 to each of the first block 24, to "the conductive bump 204 and the semiconductor wafer 3 in the opening 212a. <Electrically connecting the first electrically connected package 4 to the between the protective layer 21 and the semiconductor wafer 3. The electronic device 5 is formed in the insulation The electronic device 5 has an insulating protective layer 21 〇 ' on the electronic device 5 to bond the solder ball 50 to the upper portion, the 'the circuit board or the other package structure. ': contact pad' 烊 ball J2. TM contact 塾 23, shuttle 兮; sub-device 5 is electrically connected to the substrate body buckle. 3 is a top view such that the electric power is as shown in FIG. 2G'; the present embodiment and the above embodiment X $ a stacked seal knot are connected to the semiconductor wafer 3 by a wire 30 The insulating layer (four) 204 is formed on the insulating package (four) 204, and the package and the conductor are 3 〇; therefore, the second bump and the upper surface of the semiconductor wafer 3 do not form conductive bumps. In the first step, the first opening is in the insulation: the laminated substrate is laminated on the electrical contact 塾, and the ...= two connection 对应 corresponds to form an external electrical blind hole to be electrically connected To k if by the guide in the body of the substrate, the external electrical contact / face and the electrical contact of the right and / / part of the electrical contact continued to the external electrical contact has a recess] and thus & After the mouth is combined with the electronic device welding 111415 13 201121008 ball, the contact area of the solder ball with the external electrical contact pad is larger 5, the bonding force between the solder ball and the external electrical contact pad is stronger, It is not easy to have a solder ball falling off. Moreover, the arcuate recesses also limit the range of movement of the solder balls, so that the solder balls are less likely to drop balls or cause bridging due to contact with each other. Therefore, compared with the prior art, the stacked package structure of the present invention has the advantages of improving the yield of the processing process of the solder ball and facilitating the product design of the fine pitch. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments can be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional stacked package structure; and FIGS. 2A to 2G are schematic views showing a method of manufacturing a stacked package structure of the present invention; wherein the 2Gth image is a 2Gth image A schematic diagram of another embodiment. [Main component symbol description] 1, 2 package substrate 10, 20 substrate body 10a, 20a first surface 10b, 20b second surface 100, 200 inner layer 101 '201 conductive blind hole 102, 202 second electrical connection pad 14 111415 201121008 : 103 , 203 104 , 204 11 , 21 110 112a > 212a 112b ' 212b 13 ' 23 13a φ 14, 24, 50 210 211 22 220 23a 24 3 30 4, 4, 5

A 植球墊 第一電性連接墊 絕緣保護層 開口 第一開孔 第二開孔 電性接觸墊 上表面 焊球 弧狀凹槽 微孔 阻層 開口區 外表面 導電凸塊 半導體晶片 導線 封裝材 電子裝置 置晶區 15 111415A ball pad first electrical connection pad insulation protective layer opening first opening second opening electrical contact pad upper surface solder ball arc groove micro hole resistance layer open area outer surface conductive bump semiconductor wafer wire package material electronic Device crystal zone 15 111415

Claims (1)

201121008 七、申請專利範圍： 1. 一種封裝基板，係用於堆疊封裝（package⑽package， POP)，包括： 基板本體，係具有相對之第一及第二表面，於該第 一表面上具有置晶區，且該置晶區中具有複數第一電性 連接墊，並於該置晶區周圍具有複數第二電性連接墊， 而於該第二表面上具有複數植球墊； 靶緣保護層，係設於該基板本體之第一及第二表曳 於該第—表面上之絕緣保護層中設有複數弧狀凹 曰及第-開孔’以令各該弧狀凹槽對應各該第二電性達 2塾’而令各該第—開孔對應各該第—電性連接塾，並 t=:r設有複數微孔，令該第二電性連接塾 邛伤表面外露於該等微孔中；以及 電胜接觸墊，係設於各該弧狀凹槽及汽孔中 該電性接觸墊電性僧及u孔中，以令 2. 如申請專利範C弟二電性連接塾。 具有複數内層線路導+ -中3基板本體 接該等内層線路與等導電盲孔電性連 3. 如申請專利範圍第了 =性連接塾。 墊之外表面係呈弧狀。、基板，其中’該電性接觸 其中，形成該電 4. :申請專利範圍第" 接觸塾之材料係為鋼。基板 上之絕緣保士…π、珂裘基扳，其中’該第二表 *層中形成有複數第二開孔，以令蝴 =切細_第2項之封裳基板 上之絕缓保雄θ , Π1415 16 201121008 墊對應外露各t亥第二開孔。 6·種堆宜封震（Paekage on package，POP)結構，係包 括： 一基板本體，係具有相對之第—及第二表面，於該第 it上具有4晶區’且該置晶區中具有複數第一電性 而於Μ亚Ϊ _置晶區腳具有複數第二電性連接塾， 而於料二一上具有複數植球塾； 势 、’邑緣保覆層，係設於該基板本體之第—及 i及且第於 表面上之絕緣保制中設有魏⑽凹 接塾而應各該第二電性連 於各該弧狀凹错中設有複數微孔，”第並 之部份表面外霉於該等微孔中；7料-電性連接塾 %性接觸势，传今於i 該電性接:墊電性連接該第:電微孔中’以令 及+導體晶片’設於該置晶區上之絕緣保護層上；以 _>電子裝置，結合於該基板本體之第一本二 濩層上’該電子裝置上具有對應該電性接觸之絕緣保 这坏球結合至該電性接觸墊 ^ 性連接該基板本體。 皁使該㊆子裳置電 入如申請專利範圍第6項之堆 本體具有複數内層線路及導電、、、° ’，、，該基板 性連接該等内層線路與該等第二電性電盲孔電 111415 17 201121008 δ·如申請專利範圍第6項之堆疊封裝結構，其中 接觸墊之外表面係呈弧狀。 、忒电性 9.如申請專·圍第6項之堆疊封裝 電性接觸墊之材料係為鋼。 〃中，形成該 10·=請專利範圍第6項之堆叠封裝結構，其中 表面上之絕緣保護層中形成有複數第 植球塾對應外露各該第二開孔。 开’以令各該 如申請專利範圍第6項之堆叠封裝結構，其中， 體晶0以覆晶方式電性連接該第—電性連接塾二 請專利範圍第η項之堆疊封裝結構 凸塊’係設於各該第-開孔中，以令該 接該第一電性連接墊及半導體晶片。 “連 13.=申請專㈣η項之料縣結構，復包 材’係形成㈣崎賴層財 、 14·如申請專鄕圍第6項之堆疊封間。 髀曰y及#，. 且訂展、、，口構’其中’該半導 由導線電性連接該第—電料 申叫專利乾圍第14項之堆疊封裝結構 材’係形狀朗_護;！ ± ^括封褒 導線。 Is上以包覆該半導體晶片及 16.Π:;= 第6項之堆4封裝結構，其中，該電子 罝知電路板或另一封裝結構。 Π14Ι5 18201121008 VII. Patent application scope: 1. A package substrate, which is used for a package (10) package, POP, comprising: a substrate body having opposite first and second surfaces, and having a crystallizing region on the first surface And having a plurality of first electrical connection pads in the crystallographic region, and having a plurality of second electrical connection pads around the crystallographic region, and having a plurality of ball pads on the second surface; a target edge protection layer, And a plurality of arcuate recesses and first opening holes are disposed in the insulating protective layer of the first and second surfaces of the substrate body, wherein the arcuate grooves correspond to the first The second electrical property is up to 2塾' such that each of the first opening corresponds to each of the first electrical connection ports, and t=:r is provided with a plurality of micropores, so that the second electrical connection is exposed to the surface And the micro-hole; and the electrical contact pad is disposed in each of the arcuate groove and the vapor hole in the electrical contact pad and the u-hole, so as to make the patent Connection 塾. There are a plurality of inner layer wiring guides + - medium 3 substrate body connected to the inner layer lines and the electrically conductive blind holes electrically connected. 3. As claimed in the patent scope = sexual connection 塾. The surface outside the pad is curved. And a substrate in which the electrical contact is formed to form the electricity. 4. The scope of the patent application is "steel". Insulation protector on the substrate...π, 珂裘基板, in which 'the second table* layer is formed with a plurality of second openings, so that the butterfly = shredded _ the second item on the shelf substrate θ , Π 1415 16 201121008 The pad corresponds to the exposed second opening of each t. 6. A Paekage on package (POP) structure, comprising: a substrate body having opposite first and second surfaces, having a fourth crystal region on the first and having the crystal region Having a plurality of first electrical properties and having a plurality of second electrical connections at the foot of the Μ Ϊ 置 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶a (10) recessed joint is provided in the insulation protection of the first and the second surfaces of the substrate body, and each of the second electrical connections is provided with a plurality of micropores in each of the arcuate concaves, And part of the surface is out of the micropores; 7 material-electrical connection 塾% contact potential, passed on i, the electrical connection: the electrical connection of the first: electric micro-hole The +-conductor wafer is disposed on the insulating protective layer on the crystallizing region; and the electronic device is coupled to the first dielectric layer of the substrate body to have an insulation corresponding to the electrical contact The bad ball is bonded to the electrical contact pad to electrically connect the substrate body. The soap is used to place the seven child skirts into the sixth scope of the patent application. The stack body has a plurality of inner layer lines and a conductive line, and the substrate is connected to the inner layer lines and the second electrical electric blind holes. 111415 17 201121008 δ · as claimed in claim 6 Stacked package structure, wherein the surface of the contact pad is arc-shaped. 忒Electrical property 9. If the material of the packaged electrical contact pad of the application of the sixth item is steel, the formation of the 10·= The stacked package structure of the sixth aspect of the patent, wherein a plurality of the first ball-forming balls are formed in the insulating protective layer on the surface corresponding to the second opening. The opening is to be stacked as in the sixth item of the patent application scope. a package structure, wherein the bulk crystal 0 is electrically connected to the first electrical connection in a flip chip manner, and the stacked package structure bumps of the nth aspect of the patent range are disposed in each of the first opening holes to enable the Connected to the first electrical connection pad and the semiconductor wafer. "Continuous 13.=Application for the special (four) n item of the county structure, the package material 'formed (four) the sturdy layer of wealth, 14 · if you apply for the special group of the sixth item of the stack Enclosed.髀曰y and #,. and the exhibition, the mouth structure 'where the semi-conductor is electrically connected to the wire by the wire--the material is called the patent package, the 14th package of the package structure' ;! ± ^ 封 褒 wire. Is mounted on the semiconductor wafer and the stack 4 package structure of the sixth item, wherein the electronic circuit board or another package structure. Π14Ι5 18
TW98140939A 2009-12-01 2009-12-01 Stack package structure and package substrate thereof TWI394251B (en)

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