WO2006134664A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2006134664A1 WO2006134664A1 PCT/JP2005/011143 JP2005011143W WO2006134664A1 WO 2006134664 A1 WO2006134664 A1 WO 2006134664A1 JP 2005011143 W JP2005011143 W JP 2005011143W WO 2006134664 A1 WO2006134664 A1 WO 2006134664A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film
- semiconductor device
- insulating film
- interlayer insulating
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims description 65
- 238000004519 manufacturing process Methods 0.000 title claims description 41
- 239000003990 capacitor Substances 0.000 claims abstract description 89
- 239000011229 interlayer Substances 0.000 claims abstract description 79
- 230000004888 barrier function Effects 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims description 48
- 239000001257 hydrogen Substances 0.000 claims description 39
- 229910052739 hydrogen Inorganic materials 0.000 claims description 39
- 239000010410 layer Substances 0.000 claims description 39
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 37
- 238000009792 diffusion process Methods 0.000 claims description 25
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 19
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 2
- 229910001928 zirconium oxide Inorganic materials 0.000 claims 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims 1
- 229910001936 tantalum oxide Inorganic materials 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 83
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 78
- 239000007789 gas Substances 0.000 description 61
- 230000015654 memory Effects 0.000 description 49
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 40
- 239000010936 titanium Substances 0.000 description 39
- 238000004544 sputter deposition Methods 0.000 description 32
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 238000005229 chemical vapour deposition Methods 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 21
- 239000004020 conductor Substances 0.000 description 20
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 18
- 239000001301 oxygen Substances 0.000 description 18
- 229910052760 oxygen Inorganic materials 0.000 description 18
- 229910052721 tungsten Inorganic materials 0.000 description 17
- 229910052697 platinum Inorganic materials 0.000 description 16
- 238000000206 photolithography Methods 0.000 description 14
- 229910052719 titanium Inorganic materials 0.000 description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 14
- 239000010937 tungsten Substances 0.000 description 14
- 229910052741 iridium Inorganic materials 0.000 description 13
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 12
- 229910000457 iridium oxide Inorganic materials 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 229910052745 lead Inorganic materials 0.000 description 10
- 229910052726 zirconium Inorganic materials 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000002253 acid Substances 0.000 description 8
- 239000011575 calcium Substances 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 8
- 229910052712 strontium Inorganic materials 0.000 description 8
- 229910052791 calcium Inorganic materials 0.000 description 7
- 229910044991 metal oxide Inorganic materials 0.000 description 7
- 150000004706 metal oxides Chemical class 0.000 description 7
- 229910016570 AlCu Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical compound [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 description 6
- 229910003446 platinum oxide Inorganic materials 0.000 description 6
- 230000010287 polarization Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000010948 rhodium Substances 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 230000002269 spontaneous effect Effects 0.000 description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 3
- 229910001882 dioxygen Inorganic materials 0.000 description 3
- 239000001307 helium Substances 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910052702 rhenium Inorganic materials 0.000 description 3
- 229910052703 rhodium Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 238000000224 chemical solution deposition Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052762 osmium Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910015802 BaSr Inorganic materials 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 241000700560 Molluscum contagiosum virus Species 0.000 description 1
- 241000270907 Noreia Species 0.000 description 1
- 229910020684 PbZr Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004121 SrRuO Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- -1 silicon oxide nitride Chemical class 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XROWMBWRMNHXMF-UHFFFAOYSA-J titanium tetrafluoride Chemical compound [F-].[F-].[F-].[F-].[Ti+4] XROWMBWRMNHXMF-UHFFFAOYSA-J 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Definitions
- the present invention relates to a semiconductor device suitable for a nonvolatile memory having a ferroelectric capacitor and a method for manufacturing the same.
- a ferroelectric material is used instead of a silicon oxide or a silicon nitride as a capacitor insulating film of a capacitor element constituting a DRAM.
- a ferroelectric material is used instead of a silicon oxide or a silicon nitride as a capacitor insulating film of a capacitor element constituting a DRAM.
- research and development has been extensively conducted on technologies using high dielectric constant materials.
- a ferroelectric memory using a ferroelectric film having a spontaneous polarization characteristic as a capacitor insulating film in order to realize a nonvolatile RAM capable of a write operation and a read operation at a low voltage and a high speed is also actively researched and developed.
- a ferroelectric memory stores information by utilizing a hysteresis characteristic of a ferroelectric.
- a ferroelectric capacitor having a ferroelectric film as a capacitor dielectric film between a pair of electrodes is provided for each memory cell.
- polarization occurs according to the applied voltage between the electrodes, and spontaneous polarization remains even when the applied voltage is removed.
- the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Therefore, information can be read if spontaneous polarization is detected.
- Ferroelectric memories are characterized by high-speed operation, low power consumption, and excellent write Z-read durability.
- ferroelectric capacitors having a dielectric film and an upper electrode made of a Pt film, when the substrate is heated to about 200 ° C in an atmosphere with a hydrogen partial pressure of about 40 Pa (0.3 Torr), Pb The ferroelectric properties of the Zr Ti O film are almost lost.
- ferroelectric capacitors having a dielectric film and an upper electrode made of a Pt film, when the substrate is heated to about 200 ° C in an atmosphere with a hydrogen partial pressure of about 40 Pa (0.3 Torr), Pb The ferroelectric properties of the Zr Ti O film are almost lost.
- ferroelectric capacitors ferroelectric capacitors
- Patent Document 1 Japanese Patent Application Laid-Open No. 9 293869
- Patent Document 3 Japanese Patent Laid-Open No. 2001-210798
- An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress deterioration of characteristics due to the penetration of hydrogen or the like of external force.
- the semiconductor device includes a plurality of ferroelectric capacitors formed above a semiconductor substrate, and a first that directly covers the ferroelectric capacitors and prevents diffusion of hydrogen or water.
- a barrier film, an interlayer insulating film formed on the first barrier film, and a wiring formed on the interlayer insulating film and connected to the ferroelectric capacitor are provided.
- the interlayer insulating film is a small number of the plurality of ferroelectric capacitors. Both contain one or more second membranes that cover one and the top and side forces and prevent the diffusion of hydrogen or water.
- the one or more second NOR films cover the plurality of ferroelectric capacitors in common.
- a ferroelectric capacitor is formed above the semiconductor substrate, and then the ferroelectric capacitor is directly covered to prevent diffusion of hydrogen or water.
- a barrier film is formed.
- an interlayer insulating film is formed on the first barrier film.
- a wiring connected to the ferroelectric capacitor is formed on the interlayer insulating film.
- at least one of the plurality of ferroelectric capacitors is covered with an upper side force and a side force to prevent diffusion of hydrogen or water.
- the plurality of ferroelectric capacitors are commonly covered with the one or two or more second noria films by forming the noria film.
- FIG. 1 is a circuit diagram showing a configuration of a memory cell array of a ferroelectric memory (semiconductor device) manufactured by a method according to an embodiment of the present invention.
- FIG. 2A is a cross-sectional view showing a method of manufacturing a ferroelectric memory according to the first embodiment of the present invention in the order of steps.
- FIG. 2D is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 2C.
- FIG. 2F is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 2E.
- FIG. 21 is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 2H.
- FIG. 2J is a cross-sectional view showing the method of manufacturing the ferroelectric memory in the order of steps, following FIG.
- FIG. 2K is a cross-sectional view showing the method of manufacturing the ferroelectric memory in the order of steps, following FIG. 2J.
- FIG. 4 is a cross-sectional view showing a ferroelectric memory according to a third embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing a ferroelectric memory according to a fourth embodiment of the present invention.
- FIG. 6A is a cross-sectional view showing the method of manufacturing the ferroelectric memory according to the first embodiment of the present invention in the order of steps.
- FIG. 6B is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 6A.
- FIG. 6C is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 6B.
- FIG. 6D is a cross-sectional view showing the manufacturing method of the ferroelectric memory in order of processes following FIG. 6C.
- FIG. 6E is a cross-sectional view showing the manufacturing method of the ferroelectric memory in order of processes, following FIG. 6D.
- FIG. 6F is a cross-sectional view showing the manufacturing method of the ferroelectric memory in order of processes, following FIG. 6E.
- FIG. 6G is a cross-sectional view showing the manufacturing method of the ferroelectric memory in the order of steps, following FIG. 6F.
- the memory cell array is provided with a plurality of bit lines 3 extending in one direction, and a plurality of word lines 4 and plate lines 5 extending in a direction perpendicular to the direction in which the bit lines 3 extend. Yes.
- a plurality of memory cells of the ferroelectric memory are arranged in an array so as to be matched with the lattice formed by these bit line 3, word line 4 and plate line 5.
- Each memory cell is provided with a ferroelectric capacitor (memory portion) 1 and a MOS transistor (switching portion) 2.
- the gate of the MOS transistor 2 is connected to the word line 4.
- One source / drain of the MOS transistor 2 is connected to the bit line 3, and the other source / drain is connected to one electrode of the ferroelectric capacitor 1.
- the other electrode of the ferroelectric capacitor 1 is connected to the plate line 5.
- Each word line 4 and plate line 5 are shared by a plurality of MOS transistors 2 arranged in the same direction as the direction in which they extend.
- each bit line 3 is shared by a plurality of MOS transistors 2 arranged in the same direction as the extending direction thereof.
- the direction in which the word line 4 and the plate line 5 extend and the direction in which the bit line 3 extends may be referred to as a row direction and a column direction, respectively.
- the arrangement of the bit line 3, the word line 4 and the plate line 5 is not limited to the above.
- FIGS. 2A to 2L are cross-sectional views illustrating a method of manufacturing a ferroelectric memory (semiconductor device) according to the first embodiment of the present invention in the order of steps.
- a 200 nm-thickness SiON film (silicon oxide nitride film) is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition). Further, a silicon oxide film having a film thickness of, for example, 600 nm is formed on the entire surface by plasma TEOSCVD. An interlayer insulating film 26 is composed of these SiON film and silicon oxide film. Next, the surface of the interlayer insulating film 26 is planarized by, eg, CMP.
- a 500 nm-thickness tungsten film (not shown) is formed on the entire surface by, eg, CVD.
- the tungsten film and the barrier metal film are polished by CMP until the surface of the interlayer insulating film 26 is exposed.
- a conductor plug 34 embedded in the contact hole 32 or the like and containing tungsten is formed.
- an antioxidant film 28 having a thickness of 100 ⁇ m is formed on the entire surface by, eg, plasma CVD.
- the oxidation prevention film 28 for example, a SiON film or a silicon nitride film is formed.
- a silicon oxide film 30 having a thickness of 130 nm is formed on the entire surface by, eg, plasma TEOSCVD.
- heat treatment is performed in a nitrogen (N) atmosphere.
- the heat treatment temperature is 650 ° C.
- the heat treatment time is 30 minutes to 60 minutes.
- an aluminum oxide film 36a having a thickness of 20 nm to 100 nm is formed on the entire surface by, eg, sputtering or CVD. Further, a Pt film 36b having a thickness of 100 nm to 300 nm (for example, 175 nm) is formed as a lower electrode film on the entire surface by, eg, sputtering.
- a laminated film 36 is composed of the aluminum oxide film 36a and the Pt film 36b.
- the ferroelectric film 3 is formed on the entire surface by, eg, sputtering.
- Form 8 As the ferroelectric film 38, for example, the film thickness is 100 nm to 250 nm (for example, 15
- PZT film is formed.
- the formation method of the ferroelectric film 38 is not limited to the sputtering method.
- the ferroelectric film 38 may be formed by an OCVD method or the like.
- heat treatment is performed in an oxygen atmosphere by, for example, RTA (Rapid Thermal Annealing).
- Heat treatment temperature is 650 ° C ⁇ 800 ° C (for example, 750 ° C) and heat treatment time is 30 seconds
- an IrO film 40a having a film thickness of, for example, 25 nm to 75 nm is formed by, eg, sputtering or MOCVD. Then argon and oxygen atmosphere
- an IrO film 40b having a film thickness of 150 nm to 250 nm is formed. At this time, the process
- the oxygen composition ratio of the IrO film 40b Y force
- a partial electrode film 40 is formed.
- the upper electrode film may have a three-layer structure.
- a first IrO film having a thickness of 10 nm to 100 nm (for example, 50 nm) by, for example, sputtering or MOCVD the film thickness is, for example, by sputtering or MOCVD Is 100
- An Ir film having a thickness of 20 nm to 100 nm (for example, 75 nm) is formed by the MOCVD method or the MOCVD method.
- the film formation temperature of the Ir film is, for example, 450 ° C.
- the Ir film is the surface of the first and second IrO films
- a photoresist film (not shown) is formed on the entire surface by, eg, spin coating, and the photoresist film is patterned into the planar shape of the upper electrode of the ferroelectric capacitor by photolithography. Subsequently, the upper electrode film 40 is etched. Etching gas For example, Ar gas and CI gas are used. Thereafter, the photoresist film is removed.
- heat treatment is performed in an oxygen atmosphere, for example, at 400 ° C. to 700 ° C. (eg, 650 ° C.) for 30 minutes to 120 minutes (eg, 60 minutes).
- This heat treatment is for preventing the occurrence of an abnormality on the surface of the upper electrode (the patterned upper electrode film 40).
- a photoresist film (not shown) is formed on the entire surface by, eg, spin coating, and the photoresist film is patterned into a planar shape of the capacitive insulating film by photolithography. Subsequently, the ferroelectric film is etched. Thereafter, the photoresist film is removed. Next, heat treatment is performed in an oxygen atmosphere at 300 ° C. to 400 ° C. (eg, 350 ° C.) for 30 minutes to 120 minutes (eg, 60 minutes).
- the barrier film 44 is formed by, eg, sputtering or CVD.
- the noria film 44 for example, an aluminum oxide film having a thickness of 20 nm to 150 nm is formed.
- the method for forming the aluminum oxide film is not limited to the sputtering method or the CVD method, but it is preferable to adopt a method other than the MOCVD method.
- heat treatment is performed in an oxygen atmosphere, for example, at 400 ° C to 600 ° C for 30 minutes to 120 minutes.
- a photoresist film (not shown) is formed on the entire surface by, eg, spin coating, and the photoresist film is patterned into the planar shape of the lower electrode of the ferroelectric capacitor by photolithography. Subsequently, the noria film 44 and the lower electrode film 36 are etched. As a result, a lower electrode is formed.
- a ferroelectric capacitor 42 is composed of the notched upper electrode film 46, the ferroelectric film 38 and the stock electrode film 36, and this ferroelectric capacitor 42 corresponds to the ferroelectric capacitor 1 in FIG.
- the barrier film 44 remains so as to cover the upper electrode film 40 and the ferroelectric film 38. Thereafter, the photoresist film is removed. Next, heat treatment is performed in an oxygen atmosphere, for example, at 350 ° C. to 600 ° C. for 30 minutes to 60 minutes.
- a barrier film 46 is formed on the entire surface by, eg, sputtering or CVD.
- the noria film 46 for example, an aluminum oxide film having a thickness of 20 nm to 50 nm is formed. The whole of the ferroelectric capacitor 42 is covered by the noria film 46.
- an interlayer insulating film 48 made of a silicon oxide film having a thickness of, for example, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD.
- a silicon oxide film for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas.
- the interlayer insulating film 50 for example, an insulating inorganic film or the like may be formed. After the formation of the interlayer insulating film 50, the surface of the interlayer insulating film 48 is planarized by, eg, CMP.
- a trench 49 reaching the barrier film 46 is formed in the interlayer insulating film 48 by using a photolithography technique.
- the position of the groove 49 may surround all the ferroelectric capacitors 42 arranged in an array, for example, or one or more of the ferroelectric capacitors 42 arranged in an array
- a groove 49 surrounding the substrate may be formed at a plurality of locations.
- an aluminum oxide film is formed as the noria film 46, and therefore, the noria film 46 can be used as an etching stopper film in forming the trench 49. If such an acid aluminum film is not formed, the acid prevention film 28 may be used as an etching stopper film.
- the sidewall of the groove 49 is inclined following the formation of the groove 49.
- etching using Ar gas is performed.
- the inclination angle of the side wall is preferably 60 ° or less.
- the substrate temperature in this heat treatment is, for example, 350 ° C.
- the flow rate of N 2 O gas is, for example, lOOOsccm.
- the gas flow rate is 285 sccm, for example.
- the gap between the counter electrodes is, for example, 7.62 mm (0.3 inch).
- the high frequency power to be applied is 525 W, for example.
- the atmospheric pressure in the chamber is, for example, about 400 Pa (3 Torr). Use N 2 O gas after heat treatment.
- the interlayer insulating film 48 may be exposed to the plasma atmosphere generated in this manner. By the heat treatment, moisture present in the interlayer insulating film 48 is removed. And it is generated using NO gas etc. When the interlayer insulating film 48 is exposed to the plasma atmosphere, the film quality of the interlayer insulating film 48 changes, and moisture enters the interlayer insulating film 48.
- a barrier film 50 is formed on the entire surface by, eg, sputtering or CVD.
- the noria film 50 for example, an aluminum oxide film having a film thickness of 50 nm to 100 nm is formed.
- the noria film 50 becomes flat.
- the noria film 50 is also formed in the groove 49. At this time, since the side wall of the groove 49 is inclined (for example, 60 ° or more), the noria film 50 is formed almost uniformly with good coverage.
- an interlayer insulating film 52 is formed on the entire surface by, eg, plasma TEOSCVD.
- the interlayer insulating film 52 for example, a silicon oxide film having a thickness of 800 nm to 1000 nm is formed.
- a SiON film, a silicon nitride film, or the like may be formed.
- the surface of the interlayer insulating film 52 is planarized by, eg, CMP.
- a contact hole 53 reaching the upper electrode 40 of the ferroelectric capacitor 42 is formed on the interlayer insulating film 52, the noria film 50, and the interlayer insulating film 48 by using a photolithography technique.
- a contact hole (not shown) reaching the lower electrode 36 of the dielectric capacitor 42 is formed.
- heat treatment is performed in an oxygen atmosphere at 400 ° C to 600 ° C for 30 minutes to 120 minutes (60 minutes).
- the substrate temperature is, for example, 500 ° C to 600 ° C.
- the ferroelectric film 38 is supplied with oxygen, and the electrical characteristics of the ferroelectric capacitor 42 are restored.
- this heat treatment may be performed in an ozone atmosphere rather than an oxygen atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen is supplied to the ferroelectric film 38 and the electrical characteristics of the ferroelectric capacitor 42 are restored.
- the interlayer insulating film 52, the noria film 50, the interlayer insulating film 48, the barrier film 46, the silicon oxide film 30 and the oxide film preventing film 28 are formed by using a photolithography technique.
- a contact hole 54 reaching the conductor plug 34 is formed.
- plasma cleaning using Ar gas is performed.
- a natural oxide film or the like existing on the surface of the conductor plug 34 is removed.
- the plasma cleaning conditions are such that, for example, the hot oxide film is removed by lOnm.
- a TiN film (not shown) having a film thickness of 20 nm to 100 nm is formed as a barrier metal film on the entire surface by, eg, sputtering.
- a tungsten film (not shown) having a film thickness of 300 nm to 600 nm is formed on the entire surface by, eg, CVD. Thereafter, the tungsten film and the barrier metal film are polished by, for example, CMP until the surface of the interlayer insulating film 52 is exposed. As a result, as shown in FIG. 2K, a conductor plug 56 containing tungsten is formed by being embedded in the contact holes 53, 54 and the like.
- the high frequency power to be applied is 525 W, for example.
- the pressure in the chamber is, for example, about 400 Pa (3 Torr).
- plasma cleaning using Ar gas is performed.
- the plasma cleaning conditions are set such that, for example, the hot oxide film is removed by lOnm.
- a Ti film with a thickness of 60 nm, a TiN film with a thickness of 30 nm, an AlCu alloy film with a thickness of 360 nm, a Ti film with a thickness of 5 nm, and a thickness of 70 nm TiN films are sequentially formed.
- a multilayer film composed of a Ti film, a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed.
- the laminated film is patterned using photolithography technology. As a result, as shown in FIG. 2L, a wiring (first metal wiring layer) 58 made of a laminated film is formed.
- high density plasma enhanced CVD High Density Plasma enhanced
- a silicon oxide film 60 having a film thickness of 750 nm is formed by a chemical vapor deposition (CVD) method.
- a silicon oxide film 62 having a thickness of, for example, lOOm is formed by plasma TEOSCVD.
- the source gas for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used. Note that the method for forming the silicon oxide films 60 and 62 is not limited to the one described above. It is not specified. For example, both silicon oxide films 60 and 62 may be formed by the plasma TEOS CVD method! /.
- the surface of the silicon oxide film 62 is planarized by, eg, CMP.
- the substrate temperature in this heat treatment is, for example, 350 ° C.
- a contact hole 63 reaching the wiring 58 is formed in the silicon oxide films 62 and 60 by using a photolithography technique. Thereafter, plasma cleaning using Ar gas is performed. As a result, a natural oxide film or the like existing on the surface of the wiring 58 is removed.
- the plasma cleaning conditions are, for example, such that the thermal oxide film is removed by 25 nm.
- a Ti film (not shown) having a thickness of lOnm is formed by, eg, sputtering.
- a TiN film (not shown) having a film thickness of 3.5 ⁇ m to 7 ⁇ m is formed by, for example, MOCVD.
- a rare metal film is composed of the Ti film and TiN film.
- a tungsten film (not shown) having a film thickness of 300 nm to 600 nm is formed by, eg, CVD.
- the tanta- sten film and the barrier metal film are polished by, for example, the CMP method until the surface of the silicon oxide film 62 is exposed. As a result, a conductor plug 64 containing tungsten and being embedded in the contact hole 63 is formed.
- heat treatment is performed in a plasma atmosphere generated using N 2 O gas or N gas.
- the amount of 2 2 is, for example, 285 sccm.
- the gap between the counter electrodes is, for example, 7.62 mm (0.3 inch).
- the high frequency power to be applied is 525 W, for example.
- the atmospheric pressure in the chamber is, for example, about 400 Pa (3 Torr).
- a Ti film with a thickness of 60 nm, a TiN film with a thickness of 30 nm, an AlCu alloy film with a thickness of 360 nm, a Ti film with a thickness of 5 nm, and a thickness of 70 nm TiN film The shift is not shown in the figure).
- a multilayer film composed of a Ti film, a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed.
- the laminated film is patterned using photolithography technology.
- a wiring (second metal wiring layer) 66 made of a laminated film is formed.
- a silicon oxide film 68 having a thickness of 750 nm is formed by, for example, a high density plasma CVD method.
- a silicon oxide film 70 having a thickness of, for example, lOO nm is formed by plasma TEOSCVD. Note that the method of forming the silicon oxide films 68 and 70 is not limited to the above. For example, both silicon oxide films 68 and 70 may be formed by the plasma TE OSCVD method!
- the surface of the silicon oxide film 70 is planarized by, eg, CMP.
- the substrate temperature in this heat treatment is set to 350 ° C., for example.
- the flow rate of N 2 O gas is 1
- the flow rate of N gas is, for example, 285 sccm.
- the counter electrode gap is
- the applied high frequency power is, for example, 525W.
- the atmospheric pressure in the chamber is, for example, about 400 Pa (3 Torr).
- a contact hole 72 reaching the wiring 66 is formed in the silicon oxide films 68 and 70 by using a photolithography technique. Thereafter, plasma cleaning using Ar gas is performed. As a result, a natural oxide film or the like existing on the surface of the wiring 66 is removed.
- the plasma cleaning conditions are, for example, such that the thermal oxide film is removed by 25 nm.
- a Ti film (not shown) having a thickness of lOnm is formed by, eg, sputtering. More
- a TiN film (not shown) having a film thickness of 3.5 ⁇ m to 7 ⁇ m is formed by MOCVD, for example.
- a rare metal film is composed of the Ti film and TiN film.
- a tungsten film (not shown) having a film thickness of 300 nm to 600 nm is formed by, eg, CVD.
- the tanta- sten film and the barrier metal film are polished by, eg, CMP method until the surface of the silicon oxide film 70 is exposed. As a result, the contact hole 72 is buried.
- a conductor plug 74 containing tungsten is formed. [0062] Next, heat treatment is performed in a plasma atmosphere generated using NO gas, N gas, or the like.
- the substrate temperature in this heat treatment is, for example, 350 ° C.
- the flow rate of N 2 O gas is, for example, lOOOsccm. N gas flow
- the amount of 2 2 is, for example, 285 sccm.
- a Ti film with a thickness of 60 nm, a TiN film with a thickness of 30 nm, an AlCu alloy film with a thickness of 360 nm, a Ti film with a thickness of 5 nm, and a thickness of 70 nm TiN films are sequentially formed.
- a multilayer film composed of a Ti film, a TiN film, an AlCu alloy film, a Ti film, and a TiN film is formed.
- the laminated film is patterned using photolithography technology.
- a wiring (third metal wiring layer) 76 made of a laminated film is formed.
- a 700 nm thick silicon oxide film 78 is formed by, for example, a high density plasma CVD method.
- the method of forming the silicon oxide film 78 is not limited to the above.
- the silicon oxide film 78 may be formed by a plasma TEOSCVD method.
- the substrate temperature in this heat treatment is, for example, 350 ° C.
- the flow rate of N 2 O gas is, for example, lOOOsccm
- the flow rate of N gas is, for example, 285 sccm.
- a silicon nitride film 80 having a thickness of 500 nm is formed on the silicon oxide film 78 by, eg, CVD.
- the silicon nitride film 80 prevents moisture from entering and prevents the wiring 76, 66, 58 and the like from being corroded by moisture.
- an opening (not shown) reaching the electrode pad is formed in the silicon nitride film 80 and the silicon oxide film 78 by using a photolithography technique.
- a polyimide film 82 having a film thickness of, for example, 2 m to 10 m is formed by, eg, spin coating.
- an opening (not shown) reaching the electrode pad is formed in the polyimide film 82 using a photolithographic technique. In this way, the semiconductor device according to this embodiment is completed.
- the barrier film 50 exists between the ferroelectric capacitor 42 and the wiring (first metal wiring layer) 58.
- the barrier film 50 is formed on the planarized interlayer insulating film 48, the NOR film 50 is flat above the ferroelectric capacitor 42.
- the noria film 50 is formed below the wiring (first metal wiring layer) 58 in this embodiment. Therefore, the barrier film 50 can also prevent the adverse effect that hydrogen reaches the ferroelectric capacitor 42 when forming the silicon oxide films 60 and 62 and the like. Therefore, according to the present embodiment, the phenomenon that hydrogen reaches the ferroelectric film 38 can be surely prevented, and the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen. Problems can be prevented. Therefore, according to the present embodiment, it is possible to reliably prevent the deterioration of the electrical characteristics of the ferroelectric capacitor 42.
- the ferroelectric capacitor 42 is indirectly surrounded by the barrier film 52 in the lateral direction. Therefore, it is possible to prevent hydrogen from reaching the ferroelectric film 38 from the side. In addition, it is possible to reliably prevent the deterioration of the characteristics of the outermost ferroelectric capacitors 42 arranged in an array.
- an interlayer insulating film 52 is formed on the barrier film 50, and a wiring 58 is formed on the interlayer insulating film 52. Therefore, the degradation of the noria film 50 is suppressed by the interlayer insulating film 52, and the function of the barrier film 50 can be sufficiently exerted. Further, since the interlayer insulating film 52 is formed on the barrier film 50, it is possible to prevent a situation where even the barrier film 50 is etched when patterning to form the wiring 58. . Furthermore, even with the wiring 58, high reliability can be obtained.
- the conductor plug 56 is directly connected to the source Z drain diffusion layer 14. It is connected to the source Z drain diffusion layer 14 through the conductor plug 34.
- the conductor plug 56 is to be directly connected to the source Z drain diffusion layer 14, not only the interlayer insulating films 52 and 48 but also the noor film 50 is etched to form the source Z drain. It is necessary to form a contact hole that reaches the diffusion layer 14. However, since the etching characteristics of the NORA film 50 such as an aluminum oxide film are significantly different from those of the interlayer insulating films 52 and 48, etc., contact holes that do not damage the source / drain diffusion layer 14 are formed. It is extremely difficult to form.
- the wiring 58 and the source / drain diffusion layer 14 are electrically connected without damaging the source Z drain diffusion layer 14 because the conductor plug 34 is interposed therebetween. Can be connected. Therefore, according to the present embodiment, a highly reliable semiconductor device can be manufactured with a high yield.
- the oxidation prevention film 28 is formed on the interlayer insulating film 26. For this reason, when the silicon oxide film 30 or the like is formed, the surface of the conductor plug 34 can be prevented from being oxidized, and the contact resistance between the conductor plug 56 and the conductor plug 34 can be kept low. wear.
- FIG. 3 is a cross-sectional view showing a ferroelectric memory (semiconductor device) according to the second embodiment of the present invention.
- the NOR film 50 is composed of an acid aluminum film 50a and an acid titanium film 50b.
- the thickness of the aluminum oxide film 50a is, for example, 20 nm to 50 nm
- the thickness of the titanium oxide film 50b is, for example, 20 nm to 100 nm. Titanium oxide film
- the aluminum oxide film 50a and the acid film is formed sequentially.
- oxide film 50 it is also possible to form the oxide aluminum film 50 a on the oxide titanium film 50 b after forming the oxide titanium film 50 b on the interlayer insulating film 48. Good.
- FIG. 4 is a cross-sectional view showing a ferroelectric memory (semiconductor device) according to a third embodiment of the present invention.
- a barrier film 84 is formed between the wiring (first metal wiring layer) 58 and the wiring (second metal wiring layer) 66, and the wiring (second metal wiring layer) 66
- a barrier film 86 is formed between the wiring (third metal wiring layer) 76. That is, the barrier film 84 and the silicon oxide film 65 are sequentially formed on the flattened silicon oxide film 62, and the wiring 66 is formed thereon. Further, a barrier film 86 and a silicon oxide film 71 are sequentially formed on the planarized silicon oxide film 70, and a wiring 76 is formed thereon.
- the noria films 84 and 86 are, for example, an aluminum oxide film having a thickness of 50 nm.
- the film thickness of the silicon oxide films 65 and 71 is, for example, lOOnm.
- the barrier film 84 and a silicon oxide film 65 are sequentially formed. Thereafter, in the same manner as in the first embodiment, a series of processes up to the flatness of the silicon oxide film 70 is performed for the formation capability of the wiring 66. Next, a barrier film 86 and a silicon oxide film 71 are sequentially formed.
- the NOR films 84 and 86 can also be formed so as to surround the ferroelectric capacitor 42, as with the NOR film 50. However, considering the increase in the number of processes, the necessity of deeper grooves, and sufficient hydrogen-noreness due to the noria film 50, the noria films 84 and 86 are flat. A film is preferred.
- FIG. 5 is a cross-sectional view showing a ferroelectric memory (semiconductor device) according to a fourth embodiment of the present invention.
- a noria film 90 is formed above the wiring (third metal wiring layer) 76. That is, a flattened silicon oxide film 88 is formed on the silicon oxide film 78, and a barrier film 90 is formed on the silicon oxide film 88. Then, an insulating film 92 such as a silicon oxide film is formed on the noor film 90, and a silicon nitride film 80 and a polyimide film 82 are formed on the insulating film 92 as in the first embodiment. ing.
- the barrier film 90 is an aluminum oxide film having a film thickness of, for example, about 50 nm, and the film thickness of the insulating film 92 is, for example, lOOnm.
- the silicon oxide layer is formed.
- a silicon oxide film 88 having a thickness that fills the depression of the film 78 is formed.
- the surface of the silicon oxide film 88 is planarized.
- a barrier film 90 and an insulating film 92 are sequentially formed on the silicon oxide film 88. Since the barrier film 90 is formed on the flattened silicon oxide film 88, the NOR film 90 becomes flat.
- the processes from the formation of the silicon nitride film 92 to the formation of the pad opening are performed to complete the semiconductor device.
- the flat noria film 90 is also formed above the uppermost wiring 76, higher hydrogen noria properties can be obtained. Therefore, the yield can be further improved.
- FIG. 6A to FIG. 6G show ferroelectric memories (semiconductors) according to the fifth embodiment of the present invention. It is sectional drawing which shows the manufacturing method of an apparatus in order of a process.
- a well 312 is formed on the surface of a semiconductor substrate 311 such as a silicon substrate.
- a semiconductor substrate 311 such as a silicon substrate.
- STI shallow insulator
- An isolation region 313 is formed by isolation. Subsequently, by forming a gate insulating film 314, a gate electrode 315, a cap film 316, a sidewall 317, a source Z drain diffusion layer 318 and a silicide layer 319 on the surface of the well 312, the MOS transistor 320 is formed as a switching element. Form.
- the MOS transistor 320 corresponds to the MOS transistor 2 in FIG. Note that each MOS transistor 320 has a force for forming two source Z drain diffusion layers 318 for the source and drain, one of which is shared between the two MOS transistors 320.
- a silicon oxynitride film 321 (thickness: 200 nm) is formed on the entire surface so as to cover the MOS transistor 320, and a silicon oxide film 322 (thickness: lOOOnm) is formed on the entire surface as an interlayer insulating film. ) And flatten the silicon oxide film 322 by CMP (chemical mechanical polishing) or the like.
- the silicon oxynitride film 321 is formed to prevent hydrogen deterioration of the gate insulating film 314 and the like when the silicon oxide film 322 is formed.
- contact holes reaching the silicide layers 319 are formed in the silicon oxide film 322 and the silicon oxynitride film 321 to open plug contact portions.
- a conductive film 324 is formed by embedding a W film by, for example, the CVD method and performing flattening by CMP.
- an iridium film 325 is formed on the silicon oxide film 322 by, eg, sputtering.
- the substrate temperature is set to 500 ° C.
- the film forming power is set to IkW
- the flow rate of Ar gas is set to lOOsccm
- the pressure in the chamber is set to 0.35 Pa
- the film forming time is set to 176 seconds.
- an iridium oxide film 326 is formed on the iridium film 325 by, for example, a sputtering method.
- the conditions at this time are, for example, that the substrate temperature is 50 ° C., the deposition rate is IkW, the flow rate of Ar gas is 60 sccm, the flow rate of O gas is 60 sccm, and the pressure in the chamber is 0.37 P. a and the deposition time is 10 seconds.
- the substrate temperature is 50 ° C.
- the deposition rate is IkW
- the flow rate of Ar gas is 60 sccm
- the flow rate of O gas is 60 sccm
- the pressure in the chamber is 0.37 P. a
- the deposition time is 10 seconds.
- a platinum film 327 is formed on the iridium oxide film 326 by, eg, sputtering.
- the conditions at this time are, for example, that the substrate temperature is 350 ° C., the deposition pressure is lkW, the Ar gas flow rate is lOOsccm, the pressure in the chamber is 0.38 Pa, and the deposition time is 8 seconds. To do. As a result, a platinum film 327 having a thickness of about 15 nm is obtained.
- a platinum oxide film 328 is formed on the platinum film 327, for example, by sputtering.
- the conditions at this time are, for example, that the substrate temperature is 350 ° C., the deposition rate is lkW, the Ar gas flow rate is 36 sccm, the O gas flow rate is 144 sccm, and the pressure in the chamber is 6.2 Pa.
- the film formation time is 22 seconds.
- a platinum oxide film 328 having a thickness of about 25 nm is formed.
- a platinum film 329 is formed on the platinum oxide film 328 by, for example, sputtering.
- the conditions at this time are, for example, that the substrate temperature is 100 ° C., the film forming power is lkW, the flow rate of Ar gas is lOOsccm, the pressure in the chamber is 0.4 Pa, and the film forming time is 32 seconds.
- a platinum film 329 having a thickness of about 50 nm is formed.
- iridium film 325, iridium oxide film 326, platinum film 327, platinum oxide film 328 and platinum film 329 constitute a barrier metal film and a lower electrode film.
- the following laminate may be used as the barrier metal film and the lower electrode film.
- a laminate in which a Ti film is formed on an Ir film (b) a laminate in which a Ti film and a TiAIN film are sequentially formed on an Ir film, and (c) a Ti film is formed on a Pt film. (D) a laminate in which an IrO film is formed on a Pt film, (e
- a laminate in which a 2 1 -X X 3 film is formed, or (g) a laminate in which a Ti film and a T1A1N film are sequentially formed on a Pt film may be used. That is, Pt, Ir, Ru, Rh, Re, Os, Pd, SrRuO and TiAIN
- a single film or a laminated conductive film of a metal or metal oxide containing at least one selected from the group consisting of these can be used.
- the platinum film 329 is crystallized by performing rapid heat treatment (RTA) in an Ar atmosphere for 60 seconds at, for example, 750 ° C.
- RTA rapid heat treatment
- a ferroelectric film such as a PLZT ((Pb, La) (Zr, Ti) 0) film 330 is formed on the platinum film 329.
- the PLZT film 330 is, for example, M Force that can be formed by the OCVD method When using the MOCVD method, it is desirable to change the structure of the lower electrode film to another.
- an upper electrode film 331 is formed on the PLZT film 330 by sputtering.
- the upper electrode film 331 is composed of two layers of iridium oxide films having different compositions, for example.
- the substrate temperature is set to room temperature
- the film forming capacity is set to 2 kW
- the Ar gas flow rate is set to lOOsccm
- the O gas flow rate is set to 59 sccm. So
- the first iridium oxide film is about 50 nm. After forming the first iridium oxide film, annealing is performed, and then the second iridium oxide film is formed.
- the second-layer iridium oxide film is, for example, about 75 to 125 nm. Subsequently, the back surface (back surface) of the semiconductor substrate (wafer) 311 is cleaned.
- an iridium adhesion film (mask adhesion film) 332 is formed on the upper electrode film 331 by, for example, a sputtering method.
- the substrate temperature is set to 400 ° C. or higher
- the Ar gas flow rate is set to lOOsccm
- the film forming power is set to lkW
- the film forming time is set to 7 seconds.
- an iridium adhesion film 332 having a thickness of about lOnm is formed.
- the iridium adhesion film 332 After forming the iridium adhesion film 332, when patterning the upper electrode film 331, the PLZT film 330, the platinum film 329, the platinum oxide film 328, the platinum film 327, the iridium oxide film 326, and the iridium film 325, as a hard mask A titanium nitride film (not shown) to be used and a silicon oxide film (not shown) using TEOS are sequentially formed.
- the titanium nitride film is formed at 200 ° C., for example, and its thickness is about 200 nm.
- the silicon oxide film is formed at, for example, 390 ° C., and the thickness thereof is about 390 ⁇ m.
- a hard mask is formed only in a region where a stack type ferroelectric capacitor is to be formed.
- a hard mask is formed only in a region where a stack type ferroelectric capacitor is to be formed.
- the physical film 328, the platinum film 327, the iridium oxide film 326, and the iridium film 325 are collectively processed to form a ferroelectric capacitor having a stack structure as shown in FIG. 6D.
- This ferroelectric capacitor corresponds to the ferroelectric capacitor 1 in FIG.
- the hard mask silicon oxide film and titanium nitride film
- heat treatment is performed in an oxygen atmosphere, for example, at 300 to 500 ° C. for 30 to 120 minutes.
- the barrier film 335 is formed on the entire surface by, eg, sputtering or CVD.
- an acid aluminum film having a thickness of 20 nm is formed by, for example, sputtering or CVD.
- a recovery annealing is performed. For example, heat treatment is performed at 500 ° C. to 700 ° C. for 30 minutes to 120 minutes in an oxygen atmosphere.
- an interlayer insulating film 336 made of a silicon oxide film having a thickness of, for example, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD.
- a silicon oxide film for example, a mixed gas of TEOS gas, oxygen gas, and helium gas is used as the source gas.
- the interlayer insulating film 336 for example, an insulating inorganic film or the like may be formed.
- the surface of the interlayer insulating film 336 is planarized by, eg, CMP.
- a trench 337 reaching the barrier film 335 is formed in the interlayer insulating film 336 by using a photolithography technique.
- the position of the groove 337 may surround, for example, all the ferroelectric capacitors arranged in an array, or surround one or more of the ferroelectric capacitors arranged in the array.
- the groove 337 may be formed at a plurality of locations.
- the noria film 335 can be used as an etching stopper film in forming the groove 337.
- the side wall of the groove 337 is inclined following the formation of the groove 337.
- etching using Ar gas is performed.
- the inclination angle of the side wall is preferably 60 ° or less.
- a noria film 338 is formed on the entire surface by, eg, sputtering or CVD.
- the noria film 338 for example, an oxide film having a film thickness of 50 nm to 100 nm is used. A lumi-mu film is formed.
- the NOR film 338 is formed on the flattened interlayer insulating film 336, so that the NOR film 338 becomes flat. Further, the noria film 338 is also formed in the groove 337. At this time, since the side wall of the groove 337 is inclined (for example, 60 ° or more), the noria film 338 is formed almost uniformly with good coverage.
- an interlayer insulating film 339 is formed on the entire surface by, eg, plasma TEOSCVD.
- the interlayer insulating film 339 for example, a silicon oxide film having a film thickness of 800 nm to 1000 nm is formed.
- a SiON film, a silicon nitride film, or the like may be formed.
- the surface of the interlayer insulating film 339 is planarized by, eg, CMP.
- contact holes reaching the conductor plug 324 are formed in the interlayer insulating film 339, the noria film 338, the interlayer insulating film 336, and the barrier film 335 using patterning and etching techniques.
- the conductor plug 56 and the wiring 58 are formed in the same manner as the formation of the conductor plug 56 in the first embodiment. Subsequently, similarly to the second embodiment, the processes from the formation of the silicon oxide film 60 to the formation of the nod opening are performed to complete the semiconductor device.
- the wiring 56 connected to the ferroelectric capacitor is connected to the plate line, and the wiring connected to the MOS transistor 320 via the conductor plug 56 is connected to the bit line.
- the barrier film is not limited to the acid-aluminum film and the acid-aluminum titanium film, and can prevent at least diffusion of hydrogen or water, such as a metal oxide film or a metal nitride film.
- Any film can be used.
- an A1 nitride film, an A1 oxynitride film, a Ta oxide film, a Ta nitride film, a Zr oxide film, a Si oxynitride film, or the like can be used.
- the metal oxide film is dense, it is possible to reliably prevent hydrogen diffusion even when the metal oxide film is relatively thin. Therefore, it is preferable to use a metal oxide as the noria film from the viewpoint of miniaturization.
- the crystal structure of the substance constituting the ferroelectric film is limited to the velovskite structure.
- it may be a Bi layer structure.
- the composition of the material constituting the ferroelectric film is not particularly limited.
- the acceptor element may contain Pb (lead), Sr (strontium), Ca (calcium), Bi (bismuth), Ba (barium), Li (lithium) and Z or Y (yttrium).
- Ti titanium
- Zr zirconium
- Hf hafnium
- V vanadium
- Ta tantalum
- W tungsten
- M n manganese
- A1 aluminum
- Bi bismuth
- Z or Sr sinrontium
- the chemical formula of the material constituting the ferroelectric film is, for example, Pb (Zr, Ti) 2 O, (Pb, Ca)
- Power is not limited to these.
- Si may be added to these.
- the present invention is not limited to application to a ferroelectric memory, but may be applied to, for example, DRAM or the like.
- a ferroelectric film for example, a high dielectric film such as (BaSr) TiO film (BST film), SrTiO film (STO film), TaO film, etc.
- the high dielectric film is a dielectric film having a relative dielectric constant higher than that of silicon dioxide.
- the composition of the upper electrode and the lower electrode is not particularly limited.
- the bottom electrode may also be configured with, for example, Pt (platinum), Ir (iridium), Ru (ruthenium), Rh (rhodium), Re (rhenium), Os (osmium) and Z or Pd (palladium) forces. It may be composed of these acids.
- the upper electrode may be composed of, for example, Pt, Ir, Ru, Rh, Re, Os, and Z or Pd acid oxide. Further, the upper electrode may be configured by laminating a plurality of films.
- the structure of the ferroelectric memory cell is not limited to the 1T1C type, but may be the 2T2C type.
- the ferroelectric capacitor itself may be configured to serve both as a force storage unit and a switching unit.
- the structure is such that a ferroelectric capacitor is formed instead of the gate electrode of the MOS transistor. That is, A ferroelectric capacitor is formed on the semiconductor substrate via a gate insulating film.
- the method for forming the ferroelectric film is not particularly limited.
- sol-gel method organometallic decomposition (MOD) method, CSD (Chemical Solution Deposition) method, chemical vapor deposition (CV D) method, epitaxial growth method, sputtering method, MOCVD (Metal Organic Chemical Vapor Deposition) Laws can be adopted.
- MOD organometallic decomposition
- CSD Chemical Solution Deposition
- CV D chemical vapor deposition
- epitaxial growth method sputtering method
- MOCVD Metal Organic Chemical Vapor Deposition
- Patent Document 2 Japanese Patent Laid-Open No. 2003-115545 describes that a capacitor is covered with an acid-tantalum film and then further covered with an acid-aluminum film. However, even if such a structure is adopted, it is difficult to secure a sufficient barrier performance against hydrogen entering from the side.
- Patent Document 3 Japanese Patent Application Laid-Open No. 2001-2107978 discloses that a capacitor is directly covered with a laminate composed of a silicon nitride film and an aluminum oxide film. However, even if such a structure is adopted, it is difficult to ensure sufficient barrier performance against hydrogen entering from the side.
- Patent Document 4 Japanese Patent Laid-Open No. 2003-174145
- an upper electrode is shared between a plurality of ferroelectric capacitors arranged in a direction parallel to the direction in which the word lines extend, and the strength of these capacitors is increased.
- Provide a hydrogen barrier film directly covering the dielectric capacitor provide a hydrogen barrier film between these ferroelectric capacitors, and provide a gap between the plurality of ferroelectric capacitors arranged in a direction parallel to the direction in which the bit lines extend. Is described.
- the process becomes complicated, and sufficient strength and characteristics may be deteriorated. Furthermore, the crystallinity of the ferroelectric film is lowered or the ferroelectric film is easily peeled off due to the influence of the hydrogen barrier film existing between the lower electrodes.
- the present invention it is possible to prevent the entry of lateral force such as hydrogen into the ferroelectric capacitor. For this reason, the yield can be improved. It is also possible to extend the life. In addition, the operating temperature range can be expanded.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007521050A JP4930371B2 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置及びその製造方法 |
KR1020077027352A KR100973703B1 (ko) | 2005-06-17 | 2005-06-17 | 반도체 장치 및 그 제조 방법 |
CN2005800501714A CN101203953B (zh) | 2005-06-17 | 2005-06-17 | 半导体器件及其制造方法 |
PCT/JP2005/011143 WO2006134664A1 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置及びその製造方法 |
US11/957,711 US7910968B2 (en) | 2005-06-17 | 2007-12-17 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/011143 WO2006134664A1 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/957,711 Continuation US7910968B2 (en) | 2005-06-17 | 2007-12-17 | Semiconductor device and method for manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006134664A1 true WO2006134664A1 (ja) | 2006-12-21 |
Family
ID=37532036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/011143 WO2006134664A1 (ja) | 2005-06-17 | 2005-06-17 | 半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7910968B2 (ja) |
JP (1) | JP4930371B2 (ja) |
KR (1) | KR100973703B1 (ja) |
CN (1) | CN101203953B (ja) |
WO (1) | WO2006134664A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008198641A (ja) * | 2007-02-08 | 2008-08-28 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2008294194A (ja) * | 2007-05-24 | 2008-12-04 | Seiko Epson Corp | 強誘電体キャパシタの製造方法及び強誘電体キャパシタ |
JP2011203169A (ja) * | 2010-03-26 | 2011-10-13 | Seiko Epson Corp | 熱型光検出器、熱型光検出装置及び電子機器 |
JP5399232B2 (ja) * | 2007-02-21 | 2014-01-29 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006129366A1 (ja) * | 2005-06-02 | 2006-12-07 | Fujitsu Limited | 半導体装置及びその製造方法 |
KR100989086B1 (ko) * | 2005-11-29 | 2010-10-25 | 후지쯔 세미컨덕터 가부시키가이샤 | 반도체 장치와 그 제조 방법 |
CN101617399B (zh) * | 2007-02-27 | 2011-05-18 | 富士通半导体股份有限公司 | 半导体存储器件及其制造、测试方法、封装树脂形成方法 |
US20110079878A1 (en) * | 2009-10-07 | 2011-04-07 | Texas Instruments Incorporated | Ferroelectric capacitor encapsulated with a hydrogen barrier |
KR102434434B1 (ko) * | 2016-03-03 | 2022-08-19 | 삼성전자주식회사 | 반도체 소자 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004095861A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2004282041A (ja) * | 2003-02-26 | 2004-10-07 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004303996A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | 強誘電体メモリ素子およびその製造方法 |
JP2004349474A (ja) * | 2003-05-22 | 2004-12-09 | Toshiba Corp | 半導体装置とその製造方法 |
JP2005116756A (ja) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2005129875A (ja) * | 2002-11-13 | 2005-05-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005166920A (ja) * | 2003-12-02 | 2005-06-23 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09293869A (ja) | 1996-04-25 | 1997-11-11 | Nec Corp | 半導体装置およびその製造方法 |
JP2001210798A (ja) | 1999-12-22 | 2001-08-03 | Texas Instr Inc <Ti> | コンデンサ構造の保護のための絶縁性と導電性の障壁の使用 |
JP4428500B2 (ja) * | 2001-07-13 | 2010-03-10 | 富士通マイクロエレクトロニクス株式会社 | 容量素子及びその製造方法 |
EP1298730A3 (en) | 2001-09-27 | 2007-12-26 | Matsushita Electric Industrial Co., Ltd. | Ferroelectric memory and method for fabricating the same |
JP3962296B2 (ja) | 2001-09-27 | 2007-08-22 | 松下電器産業株式会社 | 強誘電体メモリ装置及びその製造方法 |
JP2003115545A (ja) | 2001-10-04 | 2003-04-18 | Sony Corp | 誘電体キャパシタおよびその製造方法 |
TWI229935B (en) * | 2002-11-13 | 2005-03-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
KR100574534B1 (ko) * | 2002-11-13 | 2006-04-27 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체장치 및 그 제조방법 |
US7238609B2 (en) | 2003-02-26 | 2007-07-03 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
JP4025316B2 (ja) * | 2004-06-09 | 2007-12-19 | 株式会社東芝 | 半導体装置の製造方法 |
JP4803995B2 (ja) * | 2004-06-28 | 2011-10-26 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
JP4042730B2 (ja) * | 2004-09-02 | 2008-02-06 | セイコーエプソン株式会社 | 強誘電体メモリおよびその製造方法 |
KR200442869Y1 (ko) | 2007-01-30 | 2008-12-17 | 한대승 | 다기능 리튬 이온 충전기 |
-
2005
- 2005-06-17 JP JP2007521050A patent/JP4930371B2/ja not_active Expired - Fee Related
- 2005-06-17 WO PCT/JP2005/011143 patent/WO2006134664A1/ja active Application Filing
- 2005-06-17 KR KR1020077027352A patent/KR100973703B1/ko active IP Right Grant
- 2005-06-17 CN CN2005800501714A patent/CN101203953B/zh not_active Expired - Fee Related
-
2007
- 2007-12-17 US US11/957,711 patent/US7910968B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004095861A (ja) * | 2002-08-30 | 2004-03-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2005129875A (ja) * | 2002-11-13 | 2005-05-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2004282041A (ja) * | 2003-02-26 | 2004-10-07 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004303996A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | 強誘電体メモリ素子およびその製造方法 |
JP2004349474A (ja) * | 2003-05-22 | 2004-12-09 | Toshiba Corp | 半導体装置とその製造方法 |
JP2005116756A (ja) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2005166920A (ja) * | 2003-12-02 | 2005-06-23 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008198641A (ja) * | 2007-02-08 | 2008-08-28 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP5399232B2 (ja) * | 2007-02-21 | 2014-01-29 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8796043B2 (en) | 2007-02-21 | 2014-08-05 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
US9305996B2 (en) | 2007-02-21 | 2016-04-05 | Fujitsu Semiconductor Limited | Semiconductor device |
JP2008294194A (ja) * | 2007-05-24 | 2008-12-04 | Seiko Epson Corp | 強誘電体キャパシタの製造方法及び強誘電体キャパシタ |
US7754501B2 (en) | 2007-05-24 | 2010-07-13 | Seiko Epson Corporation | Method for manufacturing ferroelectric capacitor |
JP2011203169A (ja) * | 2010-03-26 | 2011-10-13 | Seiko Epson Corp | 熱型光検出器、熱型光検出装置及び電子機器 |
US9182288B2 (en) | 2010-03-26 | 2015-11-10 | Seiko Epson Corporation | Thermal detector, thermal detection device, and electronic instrument |
Also Published As
Publication number | Publication date |
---|---|
CN101203953B (zh) | 2012-04-04 |
JPWO2006134664A1 (ja) | 2009-01-08 |
US20080105911A1 (en) | 2008-05-08 |
US7910968B2 (en) | 2011-03-22 |
CN101203953A (zh) | 2008-06-18 |
JP4930371B2 (ja) | 2012-05-16 |
KR20080007381A (ko) | 2008-01-18 |
KR100973703B1 (ko) | 2010-08-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8236643B2 (en) | Method of manufacturing semiconductor device including ferroelectric capacitor | |
KR100989086B1 (ko) | 반도체 장치와 그 제조 방법 | |
JP5251864B2 (ja) | 半導体装置及びその製造方法 | |
KR100949109B1 (ko) | 반도체 장치 및 그 제조 방법 | |
WO2006129366A1 (ja) | 半導体装置及びその製造方法 | |
US20140030824A1 (en) | Semiconductor device having capacitor with capacitor film held between lower electrode and upper electrode | |
JP5251129B2 (ja) | 半導体装置及びその製造方法 | |
KR100973703B1 (ko) | 반도체 장치 및 그 제조 방법 | |
US8614104B2 (en) | Method for manufacturing semiconductor device | |
JP2007165350A (ja) | 半導体装置の製造方法 | |
KR100909029B1 (ko) | 반도체 장치 및 그 제조 방법 | |
KR101262432B1 (ko) | 반도체 장치의 제조 방법 | |
JP4579236B2 (ja) | 半導体装置の製造方法 | |
KR100943011B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP5007723B2 (ja) | キャパシタを含む半導体装置及びその製造方法 | |
JP4649899B2 (ja) | 半導体記憶装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 1020077027352 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007521050 Country of ref document: JP Ref document number: 11957711 Country of ref document: US Ref document number: 200580050171.4 Country of ref document: CN |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: DE |
|
WWP | Wipo information: published in national office |
Ref document number: 11957711 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 05751107 Country of ref document: EP Kind code of ref document: A1 |