WO1998043101A1 - Bloc fonctionnel pour circuit integre, circuit integre a semiconducteur, procede d'inspection de circuits integres a semiconducteur, et procede de conception associe - Google Patents
Bloc fonctionnel pour circuit integre, circuit integre a semiconducteur, procede d'inspection de circuits integres a semiconducteur, et procede de conception associe Download PDFInfo
- Publication number
- WO1998043101A1 WO1998043101A1 PCT/JP1998/001249 JP9801249W WO9843101A1 WO 1998043101 A1 WO1998043101 A1 WO 1998043101A1 JP 9801249 W JP9801249 W JP 9801249W WO 9843101 A1 WO9843101 A1 WO 9843101A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- integrated circuit
- output
- circuit
- inspection
- data
- Prior art date
Links
- 238000007689 inspection Methods 0.000 title claims abstract description 257
- 239000004065 semiconductor Substances 0.000 title claims abstract description 146
- 238000000034 method Methods 0.000 title claims description 35
- 238000012360 testing method Methods 0.000 claims description 277
- 230000006870 function Effects 0.000 claims description 251
- 238000001514 detection method Methods 0.000 claims description 56
- 230000005540 biological transmission Effects 0.000 claims description 23
- 230000008859 change Effects 0.000 claims description 11
- 238000013461 design Methods 0.000 claims description 11
- 238000012938 design process Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 3
- 238000012986 modification Methods 0.000 description 37
- 230000004048 modification Effects 0.000 description 37
- 238000010586 diagram Methods 0.000 description 20
- 230000000295 complement effect Effects 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 7
- 238000010998 test method Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- 230000005856 abnormality Effects 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000001902 propagating effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000644 propagated effect Effects 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PVCRZXZVBSCCHH-UHFFFAOYSA-N ethyl n-[4-[benzyl(2-phenylethyl)amino]-2-(4-phenoxyphenyl)-1h-imidazo[4,5-c]pyridin-6-yl]carbamate Chemical compound N=1C(NC(=O)OCC)=CC=2NC(C=3C=CC(OC=4C=CC=CC=4)=CC=3)=NC=2C=1N(CC=1C=CC=CC=1)CCC1=CC=CC=C1 PVCRZXZVBSCCHH-UHFFFAOYSA-N 0.000 description 1
- 238000004092 self-diagnosis Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
Definitions
- the present invention relates to a function block for an integrated circuit such as a macro cell provided with a self-diagnosis circuit for checking a failure between function blocks, a semiconductor integrated circuit designed using the function block for the integrated circuit, and a method for testing and designing the same.
- a function block for an integrated circuit such as a macro cell provided with a self-diagnosis circuit for checking a failure between function blocks
- a semiconductor integrated circuit designed using the function block for the integrated circuit and a method for testing and designing the same.
- the output of the first function block 5 1 1 is provided with a shift register 5 16 that can output parallel output to the outside, and the input of the second function block 5 12 can receive parallel input from the outside.
- a simple shift register 5 17 is provided. Here, from scan-in pin 5 14 to shift register 5 16 Evening 517 and scan partner pin 515 are connected in series.
- the first integrated circuit functional block further includes a determination result output circuit that receives test data based on a control signal indicating a test data reception state, determines whether the input test data is correct, and outputs a determination result.
- a determination result output circuit that receives test data based on a control signal indicating a test data reception state, determines whether the input test data is correct, and outputs a determination result.
- it is provided.
- a method for designing a semiconductor integrated circuit according to the present invention is a method for designing a semiconductor integrated circuit using a plurality of integrated circuit function blocks each having a predetermined function such as a logic circuit or a memory circuit.
- a test data output circuit for outputting test data based on a control signal indicating a detection data transmission state; and a control signal indicating a test data reception state, for each of the plurality of integrated circuit functional blocks. Inspection data is input, the correctness of the input inspection data is judged, and a judgment result is output.
- a judgment result output circuit, and an inspection standby circuit that blocks output of an output signal based on a control signal indicating an inspection standby state is provided.
- the number of steps required to create a verification data can be reduced, so that a functional processor for an integrated circuit constituting the semiconductor integrated circuit can be reduced. Since the inspection between blocks can be performed easily and reliably, a semiconductor integrated circuit with a low defect rate can be obtained.
- FIG. 5 shows a semiconductor integrated circuit according to the first, fifth, sixth, eighth and ninth embodiments of the present invention.
- 4 is a list showing a test data sequence used for testing a circuit.
- FIG. 14 is a circuit diagram showing a detection data output circuit of a function block for an integrated circuit according to a third modification of the third embodiment of the present invention.
- FIG. 19 is a circuit diagram showing an integrated circuit function block test result output circuit according to the seventh embodiment of the present invention.
- FIG. 20 is a circuit diagram showing an integrated circuit function block determination result output circuit according to the eighth embodiment of the present invention.
- FIG. 26 is a schematic block configuration diagram of a semiconductor integrated circuit for illustrating a method of inspecting a function block using a shift register in a conventional semiconductor integrated circuit.
- FIG. 1 shows a functional block for an integrated circuit according to a first embodiment of the present invention and a circuit configuration of a semiconductor integrated circuit configured using the functional blocks for the integrated circuit.
- the semiconductor integrated circuit 1 includes, for example, a first integrated circuit function block (hereinafter simply referred to as a function block) 10, a second function block 20, and a third function block 30.
- the function blocks 10, 20, and 30 are connected to each other using a 4-bit interblock signal line 2.
- the inter-block signal line 2 is connected to bidirectional pins (not shown) of the first function block 10 and the second function block 20, and is connected to an input pin (not shown) of the third function block 30. ) Is connected.
- the first function block 10 performs a predetermined function of the first function block 10 and outputs a result thereof.
- a logic circuit 11 that operates at the time of the test and outputs a predetermined detection data sequence is provided.
- Selector 13 for selecting and outputting one of the output signal of the logic circuit 11 and the output signal of the test data output circuit 12 and between the selector 13 and the bidirectional pin.
- the test standby circuit 14 that is connected to the test block and puts the functional block into a standby state at the time of test, the tri-state buffer 15 that is brought into the high impedance state by the test standby circuit 14, and the test data string are received from the second functional block.
- a judgment result output circuit 16 for comparing the expected value held in the test data sequence with the received test data sequence and outputting the judgment result signal to the judgment result signal line 5.
- the judgment result output circuit 36 receives the inspection control signal from the control signal input terminal 36 2 and the inspection data sequence from the inspection data input terminal 36 1, and internally holds and standardizes it in advance.
- the expected value and the input inspection data sequence are compared for each pit.For example, when parallel data is output, mismatched pits are output as high data.
- a latch section 365 for immediately outputting to the inspection result output circuit 6 as a determination result signal.
- FIG. 4 shows a flowchart of a method for testing a semiconductor integrated circuit according to the first embodiment of the present invention.
- a control signal is transmitted to the test mode decoder 4 of the semiconductor integrated circuit 1 shown in FIG. Sends a predetermined inspection control signal to the component.
- the first function block 10 is notified of a first inspection control signal to enter a detection data transmission state
- the second function block 20 is notified of a third inspection control signal to be in an inspection standby state.
- the third function block 30 is notified of the second inspection control signal, and the detection function is set to the overnight reception state.
- the first functional block 10 shown in FIG. 1 is prepared and standardized in advance because the detection data output circuit 12 is activated and the inspection standby circuit 14 is deactivated.
- the detection data string is passed through the inter-block signal line 2 to the third function Output to 30. Since the test standby circuit 24 is activated, the second functional block 20 sets the tristate buffer 25 to a high impedance state so that no signal is output to the inter-block signal line 2.
- the third function block 30 activates the judgment result output circuit 36 to enter a state in which the test data string from the first function block 10 can be received.
- a decision signal from the test result output circuit 6 of the test data string corresponding to the time t 1 and the time t 2 is sent to the outside of the semiconductor integrated circuit. Observation is performed using a monitor device or the like electrically connected to the circuit. If any of the judgment signals at time t 2 and time t 2 is not a normal value, the semiconductor integrated circuit 1 to be inspected is monitored. If the judgment signal corresponding to the time tl and the time t2 is a normal value as a defective product, and the judgment signals corresponding to the time t2 are both normal values, the test item relating to the test data string shown in FIG. 5 in the semiconductor integrated circuit 1 is passed.
- the function blocks designed in the function block design process are sequentially registered in the library.
- each inter-block signal line 2 since the bits of each inter-block signal line 2 are output while being inverted in time, the signals that alternately transition from 0 to 1 and from 1 to 0 are adjacent to each other, and the crosstalk inspection is performed. I can do it reliably.
- FIG. 12 shows a circuit configuration of a function block detection output overnight output circuit according to a first modification of the third embodiment. 12, the same components as those shown in FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted.
- the selection circuits are two bits of the first selection circuit 122A and the second selection circuit 122B.
- the first flip-flop 1 25 a is connected between the selection signal input terminal 123 and the first selection circuit 122 A so that the shift register 125 is configured.
- the second flip-flop 125b is inserted between the selection signal input terminal 123 and the second selection circuit 122B.
- the division for performing the grouping is equally divided, but it is not always necessary to divide the division.
- FIG. 16 shows a test data string used in the test method for a semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in FIG. 16, all the same values in the inspection data are output after being inverted every inspection time. That is, at time t 1 All bits are output as 0, all bits are output as 1 at U t 2, and all bits are output as 0 at time t 3.
- test data sequence shown in FIG. 16 is output so that the output interval becomes the maximum signal propagation time allowed for the inter-block signal line 2.
- the inspection data output at the previous time in the judgment result output circuit 36 is taken in as reception data, and an abnormal inspection is performed.
- the data will be received. For example, when receiving the test data sequence output at time t 2, if the delay of the test data sequence output at time tl increases, the test data received by the determination result output circuit 36 At least one of the bits in the column is 0. Similarly, when receiving the test data sequence output at time t 3 and the delay of the test data sequence output at time t 2 increases, the judgment result output circuit 36 receives the test data sequence. At least one of the pits in the inspection data string is 1.
- FIG. 17 (a) shows a circuit configuration of a test data output circuit of a functional block according to the fifth embodiment of the present invention
- FIG. 17 (b) shows a functional plot according to the fifth embodiment of the present invention
- 3 shows a circuit configuration of a judgment result output circuit of the circuit.
- the inspection data output circuit 12 according to the present embodiment includes a first inspection data generation section 127A and a second inspection data generation section 1 2
- the first inspection data generator 1 27 A generates the output pattern shown in FIG. 5
- the inspection data output circuit 12 in the inspection data transmission state receives the selection control signal input to the selection control signal input terminal 128, and generates the first and second inspection data based on the selection control signal. Outputs a selection signal to select one of 127A and 127B.
- a selection circuit for outputting the selected side detection data sequence to the detection data output terminal 130 on the output side of the first and second detection data generation sections 127 A and 127 B. 1 3 1 is provided.
- the judgment result output circuit 36 in the test data receiving state receives the test data sequence at the test data input terminal 361, and receives the first control signal based on the selection control signal input to the selection control signal input terminal 366. Then, one of the second expected value comparison units 3654A and 3654B is activated. Thereafter, as described above, the determination result from the expected value comparison unit on the activated side is output to the latch unit 365, and is used as a determination result signal of the functional block. Output to the outside.
- the judgment signal of the received test data sequence is held by the test result output circuit 6, so that the judgment signals can be checked at the end of the test and batch processing can be performed.
- the first flip-flop circuit C0 receives the output signal of the first selection circuit B0, and the output signal forms a feedback loop with the first OR circuit AO and is input to the second selection circuit B1.
- the Shift Regis constitutes the evening.
- the second (bit 1) inspection data from the expected value comparison unit is processed by a circuit including a second OR circuit A1, a second selection circuit B1, and a second flip-flop circuit C1.
- the third (bit 2) and fourth (bit 3) inspection data are processed in the same manner as the inspection data of bit 0.
- the determination result output circuit 36 receives, for example, a predetermined number of test data strings shown in FIG. 5 in a detection data overnight reception state, and then receives a test control signal (not shown).
- the selection circuits B0 to B3 are switched, and the flip-flops C0 to C3 are used as shift registers.
- Connected scan partner terminal 3 6 7 B outputs to the inspection result output circuit 6 of the semiconductor integrated circuit 1 shown in FIG.
- the inspection result output circuit 6 according to the present embodiment may be configured to output the determination result signal as it is.
- the judgment result signal is held by the judgment result output circuit 36 for each bit of the test data string, so that detailed information of the test data string can be provided without providing many wirings and many external pins. Can be checked, and the judgment result signal can be checked at the end of the inspection, so that inspection batch processing can be performed.
- the semiconductor integrated circuit has a plurality of determination result output circuits 36 according to the present embodiment, and when checking the determination result signal at the end of the test, the output side and the input side of each shift register are mutually connected. It may be connected to form a new shift register. In this way, the judgment result signal can be read continuously from the plurality of judgment result output circuits 36, so that the inspection can be made more efficient.
- the expected value comparison unit 365 When MISR is used, the judgment result signal is compressed and held, so that the detailed information for each bit is lost, but the expected value comparison unit 365 always expects the inspection data sequence at each inspection time. Since there is no need to compare with the value, the configuration of the expected value comparing unit 365 can be simplified. Furthermore, the inspection data received without passing through the expected value comparison unit 365 can be used as it is.
- FIG. 21 shows a circuit configuration of a test data output circuit of a functional block according to the ninth embodiment of the present invention.
- the circuit 12 receives a test control signal from the control signal input terminal 13 5, generates a predetermined test data sequence and outputs it, and a test data generator 1 27, and generates test data.
- a test data generator 1 Connected between the section 127 and the test data output terminal 124, generates an inverted state as an inverted data generating section that inverts and outputs the value of the test data string generated based on the test control signal.
- Circuit 13 6 6.
- test data output circuit 12 configured as described above and a test method of a semiconductor integrated circuit including functional blocks including the test data output circuit 12 will be described.
- the inspection data output circuit 1 2 When the inversion state generation circuit 1336 is activated, the inspection data sequence output by the inspection data generation section 127 is inverted and output.
- test data output circuit 12 included in the first functional block 10 and the test data output circuit 22 included in the second functional block 20 shown in FIG. 1 both have an inverted state generating circuit 1 36
- the first function block 10 is in a test data transmission state
- the second function block 20 is in a test standby state
- the third function block 30 is in a test data reception state.
- the test data output circuit 22 outputs a test data sequence obtained by inverting all bits of the test data sequence at time t1.
- the tri-state buffer 25 of the second functional block 20 is set to the high impedance state and the output is blocked as described above, so that if there is no failure, the inverted test data sequence is not output.
- the tristate buffer 25 does not enter the high impedance state due to some failure, the signals of the first functional block 10 and the second functional block 20 having different logical values are blocked. Since a collision occurs on the inter-signal line 2, the possibility of an abnormal signal reaching the third function block 30 increases, and the accuracy of the inspection can be improved.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69836625T DE69836625D1 (de) | 1997-03-21 | 1998-03-20 | Prüfen der funktionellen blöcke in einer integrierten halbleiterschaltung |
US09/381,377 US6708301B1 (en) | 1997-03-21 | 1998-03-20 | Functional block for integrated circuit, semiconductor integrated circuit, inspection method for semiconductor integrated circuit, and designing method therefor |
EP98909824A EP0969289B1 (en) | 1997-03-21 | 1998-03-20 | Testing the functional blocks in a semiconductor integrated circuit |
KR10-1999-7008378A KR100522217B1 (ko) | 1997-03-21 | 1998-03-20 | 집적회로용 기능블록, 반도체 집적회로, 반도체 집적회로의 검사방법 및 그 설계방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9/67667 | 1997-03-21 | ||
JP6766797 | 1997-03-21 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/381,377 A-371-Of-International US6708301B1 (en) | 1997-03-21 | 1998-03-20 | Functional block for integrated circuit, semiconductor integrated circuit, inspection method for semiconductor integrated circuit, and designing method therefor |
US10/751,525 Continuation US20040139376A1 (en) | 1997-03-21 | 2004-01-06 | Functional block for integrated circuit, semiconductor integrated circuit, method for testing semiconductor integrated circuit, and method for designing semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998043101A1 true WO1998043101A1 (fr) | 1998-10-01 |
Family
ID=13351592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/001249 WO1998043101A1 (fr) | 1997-03-21 | 1998-03-20 | Bloc fonctionnel pour circuit integre, circuit integre a semiconducteur, procede d'inspection de circuits integres a semiconducteur, et procede de conception associe |
Country Status (6)
Country | Link |
---|---|
US (2) | US6708301B1 (ja) |
EP (1) | EP0969289B1 (ja) |
KR (1) | KR100522217B1 (ja) |
DE (1) | DE69836625D1 (ja) |
TW (1) | TW366450B (ja) |
WO (1) | WO1998043101A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008541059A (ja) * | 2005-05-05 | 2008-11-20 | サイプレス セミコンダクター コーポレーション | パラレルデータ伝送テスト回路及びテスト方法 |
CN103383022A (zh) * | 2012-05-02 | 2013-11-06 | 诺马德国有限责任公司 | 异形夹 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3654104B2 (ja) * | 2000-01-12 | 2005-06-02 | 富士通株式会社 | 試験方法、動作条件設定方法及び動作条件設定可能な装置 |
KR100657255B1 (ko) * | 2000-06-16 | 2006-12-14 | 삼성전자주식회사 | 비디오 신호 처리 시스템 |
JP4846128B2 (ja) * | 2001-07-12 | 2011-12-28 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそのテスト方法 |
US7027947B2 (en) * | 2003-04-03 | 2006-04-11 | Fujitsu Limited | Integrated circuit testing method, program, storing medium, and apparatus |
JP4063207B2 (ja) * | 2003-12-04 | 2008-03-19 | 株式会社リコー | 画像処理装置検査システムと方法およびプログラム |
KR100657830B1 (ko) * | 2005-01-24 | 2006-12-14 | 삼성전자주식회사 | 반도체 메모리 장치의 테스트 장치 및 방법 |
US7587645B2 (en) * | 2005-01-24 | 2009-09-08 | Samsung Electronics Co., Ltd. | Input circuit of semiconductor memory device and test system having the same |
US7739571B2 (en) * | 2005-01-27 | 2010-06-15 | Panasonic Corporation | Semiconductor integrated circuit and system LSI having a test expected value programming circuit |
JP5601860B2 (ja) * | 2010-03-26 | 2014-10-08 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
TWI435208B (zh) * | 2010-12-02 | 2014-04-21 | Realtek Semiconductor Corp | 積體電路與其控制方法 |
JP6295113B2 (ja) * | 2014-03-17 | 2018-03-14 | ルネサスエレクトロニクス株式会社 | 自己診断装置及び自己診断方法 |
US9835680B2 (en) | 2015-03-16 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method, device and computer program product for circuit testing |
CN112768444B (zh) * | 2020-12-31 | 2023-06-13 | 成都海光集成电路设计有限公司 | 集成电路芯片、数据分析***及电子设备 |
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-
1998
- 1998-03-20 EP EP98909824A patent/EP0969289B1/en not_active Expired - Lifetime
- 1998-03-20 TW TW087104273A patent/TW366450B/zh not_active IP Right Cessation
- 1998-03-20 KR KR10-1999-7008378A patent/KR100522217B1/ko not_active IP Right Cessation
- 1998-03-20 US US09/381,377 patent/US6708301B1/en not_active Expired - Fee Related
- 1998-03-20 WO PCT/JP1998/001249 patent/WO1998043101A1/ja active IP Right Grant
- 1998-03-20 DE DE69836625T patent/DE69836625D1/de not_active Expired - Lifetime
-
2004
- 2004-01-06 US US10/751,525 patent/US20040139376A1/en not_active Abandoned
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2008541059A (ja) * | 2005-05-05 | 2008-11-20 | サイプレス セミコンダクター コーポレーション | パラレルデータ伝送テスト回路及びテスト方法 |
CN103383022A (zh) * | 2012-05-02 | 2013-11-06 | 诺马德国有限责任公司 | 异形夹 |
Also Published As
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US20040139376A1 (en) | 2004-07-15 |
TW366450B (en) | 1999-08-11 |
DE69836625D1 (de) | 2007-01-25 |
EP0969289A4 (en) | 2004-09-08 |
KR20000076281A (ko) | 2000-12-26 |
KR100522217B1 (ko) | 2005-10-14 |
US6708301B1 (en) | 2004-03-16 |
EP0969289A1 (en) | 2000-01-05 |
EP0969289B1 (en) | 2006-12-13 |
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