US6440574B2 - Substrate for high-voltage modules - Google Patents

Substrate for high-voltage modules Download PDF

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Publication number
US6440574B2
US6440574B2 US09/776,948 US77694801A US6440574B2 US 6440574 B2 US6440574 B2 US 6440574B2 US 77694801 A US77694801 A US 77694801A US 6440574 B2 US6440574 B2 US 6440574B2
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United States
Prior art keywords
layer
metal layer
main side
substrate
dielectric
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Expired - Lifetime
Application number
US09/776,948
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English (en)
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US20010014413A1 (en
Inventor
Guy LeFranc
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31—Surface property or characteristic of web, sheet or block

Definitions

  • the invention relates to a substrate for high voltage modules with a reduced electric field strength.
  • circuits and circuit devices are often built up on boards or insulating material metallized on two sides.
  • ceramic boards coated with copper on both sides are used.
  • the ceramic board thereby constitutes an insulator with a given dielectric constant.
  • the components are mounted on the structured metal layer.
  • very high electric field strengths occur, in particular at the lateral edges of the upper metal layer, because of the high electrical voltage present between the contact surfaces.
  • the field strength is up to 50 kV/mm at a voltage of 5000 V.
  • the insulation requirements which are placed on power modules can no longer be met or at least can no longer be complied with reliably.
  • the object of the present invention is to provide a substrate for a high voltage module which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and in which, with the same geometry of insulator and metallization, the breakdown voltage is shifted to higher values.
  • a substrate for high voltage modules comprising:
  • a ceramic layer having a first main side, a second main side opposite the first main side, and a first dielectric constant ⁇ 1 ;
  • a dielectric layer with a second dielectric constant ⁇ 2 disposed on the first main side adjacent the upper metal layer on the ceramic layer.
  • the solution is based on reducing the field strength at the edges of the metallization.
  • a dielectric layer with a second dielectric constant is provided on the ceramic layer, adjoining the upper metallization.
  • the advantage of the invention resides in the fact that no significant change has to be made to the basic structure of the components currently used but, with the invention, simple protection can be achieved against peak discharges which would destroy the electronic circuit.
  • the upper metal layer is at least partly embedded in the ceramic layer.
  • the upper metal layer is connected to the lower metal layer via the dielectric layer. This permits the suppression of the surface discharge at the edge of the metallizations which, at excessively high operating voltages, can lead to destruction of the soft encapsulation.
  • the dielectric layer has a thickness approximately equal to a thickness of one of the upper metal layer and the lower metal layer.
  • the thickness of the dielectric layer Since the dissipation of the field peak depends on the thickness of the dielectric layer, it is advantageous to have the thickness of the dielectric layer approximately assume the thickness of the upper or the lower metal layer. A high dielectric constant also leads to the dissipation of the field peak.
  • FIGS. 1A and 1B each show the field profile in a configuration according to the present invention
  • FIG. 2 is a sectional view taken through a conventional prior art encapsulated circuit element
  • FIG. 3 is a diagram showing the field profile in a configuration according to the prior art.
  • FIG. 4 is a detail of a preferred configuration of the substrate according to the invention.
  • FIG. 2 there is seen a typical construction of an encapsulated circuit element according to the prior art.
  • the AlN-DCB substrate, on which the circuit is built up, is designated by 1 .
  • the insulator 1 is fixed to a copper baseplate 2 , which is used both for the mechanical stabilization of the circuit and to thermally connect the circuit to the outside.
  • the copper baseplate 2 holds the components of the circuit and ensures that heat is dissipated from the components to a heat sink cooling element.
  • the AlN substrate is connected to the copper baseplate 2 via soldered connections 3 .
  • the electronic circuit includes an IGBT 4 and a diode 5 , which are designed for voltages of, say, 1600 V.
  • the components 4 and 5 are connected to each other, for example by aluminum thick-wire bonding wires 6 and/or via metallizations on the insulator 1 .
  • the aluminum wires 6 in the case of thick wire bonding preferably have a thickness of about 200-500 ⁇ m.
  • the entire circuit construction is encapsulated in a soft encapsulation 8 , for example silicon gel, and is then incorporated in a plastic housing 9 , which is preferably fixed directly to the copper baseplate 2 and is filled with a hard encapsulating compound 7 . Only the feed lines, with load-current contacts 10 , are led out of the plastic housing 9 . In addition, the load-current contacts 10 are also connected to the circuit in the housing 9 via soldered connections 3 .
  • a soft encapsulation 8 for example silicon gel
  • FIG. 3 The field profile in such a construction according to the prior art is shown in FIG. 3 in an enlarged detail from the illustration in FIG. 2 .
  • the lower metal layer 16 of the construction shown in FIG. 3 may be in thermal contact with the copper baseplate 2 , and therefore with a cooling element, via a soldered connection. From the density of the equipotential lines 13 in FIG. 3 it can be seen that at the edges 14 a high field strength prevails in this construction according to the prior art, so that if a material-dependent breakdown field strength is exceeded, uncontrolled discharges occur, as a result of which sensitive components of the circuit can be destroyed.
  • the field profile of the electric field strength is influenced in such a way that the field does not emerge abruptly from the metallic elements of the structure; instead the field lines experience only a relatively small deflection. As a result, the density of the field lines is kept below a given level, and a flashover becomes less probable.
  • FIG. 1A shows the profile of the equipotential lines 13 at the edges 14 , in a similar illustration to FIG. 3 .
  • the edges 14 are embedded in the dielectric layer 11 .
  • the equipotential lines are therefore pulled apart, so to speak, as compared with the illustration in FIG. 3 .
  • FIG. 1B shows the situation in which the configuration is only partly connected to the dielectric layer 11 . It can be seen that the equipotential lines 13 lie closer to one another as compared with the situation in FIG. 1 A. However, the partial covering of the edges and structures of the subassembly with a small radius of curvature may be adequate if the voltages in the subassembly also remain limited.
  • FIG. 4 illustrates a preferred embodiment of the invention.
  • the ceramic layer 1 is connected to the baseplate 2 via the lower metal layer 16 and the soldered connection 3 .
  • the edge of the upper metal layer 15 is spaced further apart from the edge of the ceramic layer 1 than the edge of the lower metal layer 16 . This is a measure, known from the prior art, for reducing field peaks.
  • the upper metal layer 15 is connected to the lower metal layer 16 via the dielectric layer 11 .
  • the dielectric layer 11 runs along the surface of the ceramic layer 1 . The latter is approximately as thick as the metallic layers 15 , 16 .
  • the substrate according to the invention is surrounded by a soft encapsulation 8 .
  • the dissipation of the field peak is advantageously carried out both during steady-state and in transient operation.
  • the substrate according to the invention for high voltage modules can assume the following characteristic values: the ceramic layer 1 is typically composed of AlN.
  • the thickness d is, for example, 0.63 mm.
  • the thickness of the upper and the lower metal layers 15 , 16 is selected to be 300 ⁇ m.
  • the layer thickness of the dielectric layer 11 is selected to be 200 ⁇ m.
  • the dielectric constant ⁇ of the dielectric layer advantageously has a value ⁇ 100.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Insulating Bodies (AREA)
US09/776,948 1998-08-05 2001-02-05 Substrate for high-voltage modules Expired - Lifetime US6440574B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE19835396 1998-08-05
DE19835396 1998-08-05
DE19835396.0 1998-08-05
PCT/DE1999/002384 WO2000008686A2 (de) 1998-08-05 1999-08-03 Substrat für hochspannungsmodule

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/002384 Continuation WO2000008686A2 (de) 1998-08-05 1999-08-03 Substrat für hochspannungsmodule

Publications (2)

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US20010014413A1 US20010014413A1 (en) 2001-08-16
US6440574B2 true US6440574B2 (en) 2002-08-27

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Country Link
US (1) US6440574B2 (ja)
EP (1) EP1101248A2 (ja)
JP (1) JP2002522904A (ja)
WO (1) WO2000008686A2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025820A1 (en) * 2008-07-29 2010-02-04 Mitsubishi Electric Corporation Semiconductor device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE0003360D0 (sv) * 2000-09-21 2000-09-21 Abb Ab A semiconductor device
DE10158185B4 (de) * 2000-12-20 2005-08-11 Semikron Elektronik Gmbh Leistungshalbleitermodul mit hoher Isolationsfestigkeit
DE10130517C2 (de) 2001-06-25 2003-07-24 Eupec Gmbh & Co Kg Hochspannungsmodul und Verfahren zu dessen Herstellung
EP2337070A1 (en) 2009-12-17 2011-06-22 ABB Technology AG Electronic device with non-linear resistive field grading and method for its manufacturing
JP5766347B2 (ja) * 2012-03-19 2015-08-19 三菱電機株式会社 半導体モジュール及びその製造方法
FR2992468B1 (fr) * 2012-06-25 2015-07-03 Alstom Transport Sa Circuit electrique susceptible d'etre connecte directement a de la haute tension
JP6540324B2 (ja) * 2015-07-23 2019-07-10 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法
FR3052295B1 (fr) * 2016-06-06 2018-11-09 Universite Toulouse Iii - Paul Sabatier Procede de traitement d'un materiau electriquement isolant lui conferant des proprietes de gradation de champ electrique auto-adaptatives pour composants electriques
EP3279935B1 (en) 2016-08-02 2019-01-02 ABB Schweiz AG Power semiconductor module
WO2024095813A1 (ja) * 2022-10-31 2024-05-10 日本発條株式会社 部品実装基板、部品実装基板の製造方法、電子モジュール、及び電子モジュールの製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3039440A1 (de) 1980-10-18 1982-04-22 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Anordnung zur aufnahme von elektrischen und/oder elektronischen bauelementen
JPH03283586A (ja) 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp 樹脂基板
JPH06152146A (ja) 1992-10-30 1994-05-31 Toshiba Corp 電源装置の配線基板
JPH06318776A (ja) 1993-12-01 1994-11-15 Mitsuba Electric Mfg Co Ltd 基板の形成パターン保護構造
EP0714127A2 (en) 1991-11-28 1996-05-29 Kabushiki Kaisha Toshiba Semiconductor package
EP0717586A1 (en) 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board
JPH08172248A (ja) 1994-12-20 1996-07-02 Nikon Corp プリント基板
JPH09129989A (ja) 1995-10-30 1997-05-16 Sanyo Electric Works Ltd プリント配線板
JPH09135057A (ja) 1995-11-08 1997-05-20 Mitsubishi Electric Corp 回路基板及びその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3039440A1 (de) 1980-10-18 1982-04-22 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Anordnung zur aufnahme von elektrischen und/oder elektronischen bauelementen
JPH03283586A (ja) 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp 樹脂基板
EP0714127A2 (en) 1991-11-28 1996-05-29 Kabushiki Kaisha Toshiba Semiconductor package
JPH06152146A (ja) 1992-10-30 1994-05-31 Toshiba Corp 電源装置の配線基板
JPH06318776A (ja) 1993-12-01 1994-11-15 Mitsuba Electric Mfg Co Ltd 基板の形成パターン保護構造
EP0717586A1 (en) 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board
JPH08172248A (ja) 1994-12-20 1996-07-02 Nikon Corp プリント基板
JPH09129989A (ja) 1995-10-30 1997-05-16 Sanyo Electric Works Ltd プリント配線板
JPH09135057A (ja) 1995-11-08 1997-05-20 Mitsubishi Electric Corp 回路基板及びその製造方法
US5986218A (en) 1995-11-08 1999-11-16 Mitsubishi Denki Kabushiki Kaisha Circuit board with conductor layer for increased breakdown voltage

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025820A1 (en) * 2008-07-29 2010-02-04 Mitsubishi Electric Corporation Semiconductor device
US8450828B2 (en) * 2008-07-29 2013-05-28 Mitsubishi Electric Corporation Semiconductor device

Also Published As

Publication number Publication date
WO2000008686A2 (de) 2000-02-17
EP1101248A2 (de) 2001-05-23
WO2000008686A3 (de) 2000-05-11
JP2002522904A (ja) 2002-07-23
US20010014413A1 (en) 2001-08-16

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