WO2000008686A3 - Substrat für hochspannungsmodule - Google Patents

Substrat für hochspannungsmodule Download PDF

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Publication number
WO2000008686A3
WO2000008686A3 PCT/DE1999/002384 DE9902384W WO0008686A3 WO 2000008686 A3 WO2000008686 A3 WO 2000008686A3 DE 9902384 W DE9902384 W DE 9902384W WO 0008686 A3 WO0008686 A3 WO 0008686A3
Authority
WO
WIPO (PCT)
Prior art keywords
main side
layer
dielectric
disposed
substrate
Prior art date
Application number
PCT/DE1999/002384
Other languages
English (en)
French (fr)
Other versions
WO2000008686A2 (de
Inventor
Guy Lefranc
Original Assignee
Siemens Ag
Guy Lefranc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Guy Lefranc filed Critical Siemens Ag
Priority to JP2000564234A priority Critical patent/JP2002522904A/ja
Priority to EP99952251A priority patent/EP1101248A2/de
Publication of WO2000008686A2 publication Critical patent/WO2000008686A2/de
Publication of WO2000008686A3 publication Critical patent/WO2000008686A3/de
Priority to US09/776,948 priority patent/US6440574B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31—Surface property or characteristic of web, sheet or block

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Insulating Bodies (AREA)

Abstract

Die Erfindung schlägt ein Substrat für Hochpannungsmodule mit einer Keramikschicht mit einer ersten Hauptseite und einer der ersten Hauptseite gegenüberliegenden zweiten Hauptseite vor, die eine erste Dielektrizitätskonstante aufweist. Auf der ersten Hauptseite ist eine obere Metallschicht angeordnet, während auf der zweiten Hauptseite eine untere Metallschicht angeordnet ist. Zur Verringerung von Feldspitzen wird vorgeschlagen, eine an die obere Metallschicht angrenzende und auf der ersten Hauptseite der Keramikschicht angeordnete dielektrische Schicht mit einer zweiten Dielektrizitätskonstante vorzusehen. Die Dichte der Felslinien an Kanten von spannungsführenden Elementen werden dadurch abgemildert, daß die Dielektrizitätskonstanten der Keramikschicht und der dielektrischen Schicht aufeinander abgestimmt werden.
PCT/DE1999/002384 1998-08-05 1999-08-03 Substrat für hochspannungsmodule WO2000008686A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000564234A JP2002522904A (ja) 1998-08-05 1999-08-03 高電圧モジュール用の基板
EP99952251A EP1101248A2 (de) 1998-08-05 1999-08-03 Substrat für hochspannungsmodule
US09/776,948 US6440574B2 (en) 1998-08-05 2001-02-05 Substrate for high-voltage modules

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19835396 1998-08-05
DE19835396.0 1998-08-05

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/776,948 Continuation US6440574B2 (en) 1998-08-05 2001-02-05 Substrate for high-voltage modules

Publications (2)

Publication Number Publication Date
WO2000008686A2 WO2000008686A2 (de) 2000-02-17
WO2000008686A3 true WO2000008686A3 (de) 2000-05-11

Family

ID=7876568

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/002384 WO2000008686A2 (de) 1998-08-05 1999-08-03 Substrat für hochspannungsmodule

Country Status (4)

Country Link
US (1) US6440574B2 (de)
EP (1) EP1101248A2 (de)
JP (1) JP2002522904A (de)
WO (1) WO2000008686A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE0003360D0 (sv) * 2000-09-21 2000-09-21 Abb Ab A semiconductor device
DE10158185B4 (de) * 2000-12-20 2005-08-11 Semikron Elektronik Gmbh Leistungshalbleitermodul mit hoher Isolationsfestigkeit
DE10130517C2 (de) 2001-06-25 2003-07-24 Eupec Gmbh & Co Kg Hochspannungsmodul und Verfahren zu dessen Herstellung
JP5477681B2 (ja) * 2008-07-29 2014-04-23 三菱電機株式会社 半導体装置
EP2337070A1 (de) 2009-12-17 2011-06-22 ABB Technology AG Elektronische Vorrichtung mit nichtlinearer resistiver Feldabstufung und Verfahren zu ihrer Herstellung
JP5766347B2 (ja) * 2012-03-19 2015-08-19 三菱電機株式会社 半導体モジュール及びその製造方法
FR2992468B1 (fr) * 2012-06-25 2015-07-03 Alstom Transport Sa Circuit electrique susceptible d'etre connecte directement a de la haute tension
JP6540324B2 (ja) * 2015-07-23 2019-07-10 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法
FR3052295B1 (fr) * 2016-06-06 2018-11-09 Universite Toulouse Iii - Paul Sabatier Procede de traitement d'un materiau electriquement isolant lui conferant des proprietes de gradation de champ electrique auto-adaptatives pour composants electriques
EP3279935B1 (de) 2016-08-02 2019-01-02 ABB Schweiz AG Leistungshalbleitermodul
WO2024095813A1 (ja) * 2022-10-31 2024-05-10 日本発條株式会社 部品実装基板、部品実装基板の製造方法、電子モジュール、及び電子モジュールの製造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283586A (ja) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp 樹脂基板
JPH06318776A (ja) * 1993-12-01 1994-11-15 Mitsuba Electric Mfg Co Ltd 基板の形成パターン保護構造
EP0714127A2 (de) * 1991-11-28 1996-05-29 Kabushiki Kaisha Toshiba Halbleitergehäuse
EP0717586A1 (de) * 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Von einer Hochspannungsleiterbahn auf einer Leiterplatte erzeugtes verfahren zur Verminderung der Stärke des elektrischen Feldes
JPH08172248A (ja) * 1994-12-20 1996-07-02 Nikon Corp プリント基板
JPH09129989A (ja) * 1995-10-30 1997-05-16 Sanyo Electric Works Ltd プリント配線板
JPH09135057A (ja) * 1995-11-08 1997-05-20 Mitsubishi Electric Corp 回路基板及びその製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3039440C2 (de) 1980-10-18 1984-02-16 ANT Nachrichtentechnik GmbH, 7150 Backnang Anordnung zur Aufnahme von elektrischen und/oder elektronischen Bauelementen
JPH06152146A (ja) 1992-10-30 1994-05-31 Toshiba Corp 電源装置の配線基板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03283586A (ja) * 1990-03-30 1991-12-13 Toshiba Lighting & Technol Corp 樹脂基板
EP0714127A2 (de) * 1991-11-28 1996-05-29 Kabushiki Kaisha Toshiba Halbleitergehäuse
JPH06318776A (ja) * 1993-12-01 1994-11-15 Mitsuba Electric Mfg Co Ltd 基板の形成パターン保護構造
EP0717586A1 (de) * 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Von einer Hochspannungsleiterbahn auf einer Leiterplatte erzeugtes verfahren zur Verminderung der Stärke des elektrischen Feldes
JPH08172248A (ja) * 1994-12-20 1996-07-02 Nikon Corp プリント基板
JPH09129989A (ja) * 1995-10-30 1997-05-16 Sanyo Electric Works Ltd プリント配線板
JPH09135057A (ja) * 1995-11-08 1997-05-20 Mitsubishi Electric Corp 回路基板及びその製造方法
US5986218A (en) * 1995-11-08 1999-11-16 Mitsubishi Denki Kabushiki Kaisha Circuit board with conductor layer for increased breakdown voltage

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 016, no. 108 (E - 1179) 17 March 1992 (1992-03-17) *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 02 31 March 1995 (1995-03-31) *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 11 29 November 1996 (1996-11-29) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 09 30 September 1997 (1997-09-30) *

Also Published As

Publication number Publication date
WO2000008686A2 (de) 2000-02-17
EP1101248A2 (de) 2001-05-23
JP2002522904A (ja) 2002-07-23
US6440574B2 (en) 2002-08-27
US20010014413A1 (en) 2001-08-16

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