Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
  • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
  • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
  • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
  • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L23/15—Ceramic or glass substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
  • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
  • H01L2224/45001—Core members of the connector
  • H01L2224/45099—Material
  • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
  • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
  • H01L2224/45124—Aluminium (Al) as principal constituent
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/4805—Shape
  • H01L2224/4809—Loop shape
  • H01L2224/48091—Arched
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/481—Disposition
  • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
  • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/13—Discrete devices, e.g. 3 terminal devices
  • H01L2924/1304—Transistor
  • H01L2924/1305—Bipolar Junction Transistor [BJT]
  • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/181—Encapsulation
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/31—Surface property or characteristic of web, sheet or block

Definitions

• the invention relates to a substrate for high-voltage modules with a reduced electrical field strength.
• the circuits are often built up on plates or double-sided metallized insulating material.
• So z. B. used in power electronics on both sides Cu-coated ceramic plates, wherein the ceramic plate is an insulator with a given dielectric constant.
• the components are mounted on the structured metal layer.
• Very high electric field strengths occur in particular at the lateral edges of the upper metal layer due to the high electrical voltage present between the contact surfaces.
• the field strength is up to 50 kV / mm at a voltage of 5000 V.
• the insulation requirements placed on power modules can no longer be met due to the breakdown voltage at the transition to the ceramic, that is to say the insulator, being exceeded at least can no longer be reliably observed.
• the solution is based on reducing the field strength at the edges of the metallization.
• a dielectric layer is provided on the ceramic layer with a second dielectric constant, which is connected to the upper metal lization bordered.
• the advantage of the invention lies in the fact that no essential change has to be made to the basic structure of components used today, but simple protection against peak discharges which would destroy the electronic circuit can be achieved with the invention.
• the upper metal layer is at least partially embedded in the ceramic layer. It is also advantageous to connect the upper metal layer to the lower metal layer via the dielectric layer. As a result, the surface discharge at the edge of the metallizations can be suppressed, which, if the operating voltages are too high, can lead to destruction in the soft casting.
• the second dielectric constant is advantageously at a value greater than or equal to 10. Since the breakdown of the field peak is dependent on the thickness of the dielectric layer, it is advantageous to increase the thickness of the dielectric layer approximately to the thickness of the upper or lower metal layer to let. A high dielectric constant also leads to the degradation of the field tip.
• FIGS. 1 a and 1b each show the field profile in a structure according to the present invention
• 2 shows a typical structure of a potted switching element according to the prior art
• Fig. 3 shows the field course in a structure according to the prior art
• FIG. 4 shows a detail of a preferred arrangement of the substrate according to the invention.
• FIG. 2 A typical structure of a potted switching element according to the prior art is shown in cross section in FIG. 2.
• the AIN-DCB substrate on which the circuit is built is designated by 1.
• the insulator 1 is attached to a Cu base plate 2, which serves both for mechanical stabilization of the circuit and for the thermal connection of the circuit to the outside.
• the Cu base plate 2 holds the components of the circuit and ensures that heat is dissipated from the components to a heat sink (not shown).
• the A1N substrate is connected to the Cu base plate 2 via solder connections 3.
• the electronic circuit in the form shown comprises an IGBT 4 and a diode 5, the z. B. are designed for voltages of 1600 V. These components 4 and 5 are connected to one another, for example, with Al thick wire bonding wires 6 and / or via metallizations 12 on the insulator 1.
• the AI wires 6 preferably have a thickness of approximately 200-500 ⁇ m in the thick wire bonding.
• the entire circuit structure is in a soft potting 8 z.
• B poured from silicone gel and then installed in a housing made of plastic 9, which is preferably attached directly to the Cu base plate 2 and with a hard potting compound 7th is replenished. Only the feed lines with load current contacts 10 are led out of the plastic housing 9. The load current contacts 10 are also connected to the circuit in the housing 9 via solder connections 3.
• FIG. 3 The field course in such a construction according to the prior art is shown in FIG. 3 in an enlarged detail from the illustration in FIG. 2.
• the lower metal layer 16 of the structure shown in FIG. 3 can be in thermal contact via a soldered connection with the copper base plate 2 and thus with a heat sink. From the density of the aquipotential lines 13 in FIG. 3 it can be seen that there is a high field strength at the edges 14 in this prior art structure, so that uncontrolled discharges occur when a material-dependent breakdown field strength is exceeded comes, through which sensitive components of the circuit can be destroyed.
• the field course of the electric field strength is influenced by the dielectric layer 11 adjoining the upper metal layer 15 on the upper surface 20 of the ceramic plate 1 such that the field does not emerge abruptly from the metallic elements of the structure, but rather only the field lines relatively experience a small deflection. This keeps the density of the field lines below a given level and makes a rollover less likely.
• FIG. 1 a shows the course of the equipotential lines 13 at the edges 14 in a representation similar to FIG. 3.
• the edges 14 are embedded in the electrical layer 11 as shown in FIG. 3.
• the equipotential lines are quasi pulled apart from the illustration in FIG. 3. This reduces the field strength at the edges 14 and other structures, which reduces the risk of breakdown or rollover. It is only important that the edges 14 themselves from the insulating compound 11, i.e. the dielectric are covered.
• FIG. 1b the situation is shown in which the structure from FIG. 1 or FIG. 2 is only partially connected to the dielectric layer 11. It can be seen that the equipotential lines 13 are closer together compared to the situation in FIG. However, the partial coverage of the edges and structures of the assembly with a small radius of curvature can be sufficient, even if the stresses in the assembly remain limited.
• FIG. 2 shows a preferred embodiment of the invention.
• the ceramic layer 1 is connected to the base plate 2 via the lower metal layer 16 and the solder connection 3.
• the edge of the upper metal layer 15 is further from the edge than the edge of the lower metal layer 16 the ceramic layer 1 spaced. This is a measure known from the prior art for reducing field peaks.
• the upper metal layer 15 is connected to the lower metal layer 16 via the dielectric layer 11.
• the dielectric layer 11 runs along the surface of the ceramic layer 1. This has approximately the thickness of the metal layers 15, 16.
• the substrate according to the invention is surrounded by a soft potting 8.
• the substrate according to the invention for high-voltage modules can assume the following characteristic values:
• the ceramic layer 1 typically consists of A1N.
• the thickness d is, for example, 0.63 mm.
• the thickness of the upper and lower metal layers 15, 16 is chosen to be 300 ⁇ .
• the layer thickness of the dielectric layer 11 is chosen to be 200 ⁇ m.
• the electricity constant ⁇ of the dielectric layer is advantageously at a value> 100.

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• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Ceramic Engineering (AREA)
• Materials Engineering (AREA)
• Insulated Metal Substrates For Printed Circuits (AREA)
• Structure Of Printed Boards (AREA)
• Insulating Bodies (AREA)

Applications Claiming Priority (3)

Publications (1)

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• 1999
  • 1999-08-03 JP JP2000564234A patent/JP2002522904A/ja active Pending
  • 1999-08-03 WO PCT/DE1999/002384 patent/WO2000008686A2/de not_active Application Discontinuation
  • 1999-08-03 EP EP99952251A patent/EP1101248A2/de not_active Ceased
• 2001
  • 2001-02-05 US US09/776,948 patent/US6440574B2/en not_active Expired - Lifetime

Non-Patent Citations (1)

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