US20060060920A1 - Poly-silicon-germanium gate stack and method for forming the same - Google Patents
Poly-silicon-germanium gate stack and method for forming the same Download PDFInfo
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 238000000151 deposition Methods 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 19
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 11
- 229910007264 Si2H6 Inorganic materials 0.000 claims description 10
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 47
- 230000008021 deposition Effects 0.000 description 38
- 230000008569 process Effects 0.000 description 30
- 239000007789 gas Substances 0.000 description 24
- 230000003746 surface roughness Effects 0.000 description 18
- 238000011065 in-situ storage Methods 0.000 description 13
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 11
- 229910052986 germanium hydride Inorganic materials 0.000 description 11
- 239000012071 phase Substances 0.000 description 9
- 230000007704 transition Effects 0.000 description 8
- 239000003085 diluting agent Substances 0.000 description 7
- 230000006911 nucleation Effects 0.000 description 7
- 238000010899 nucleation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
- 239000000376 reactant Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZSBXGIUJOOQZMP-JLNYLFASSA-N Matrine Chemical compound C1CC[C@H]2CN3C(=O)CCC[C@@H]3[C@@H]3[C@H]2N1CCC3 ZSBXGIUJOOQZMP-JLNYLFASSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000008450 motivation Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H01L21/8232—Field-effect technology
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
Definitions
- the embodiments of the present invention relate to a poly-silicon-germanium (poly-SiGe) gate stack for semiconductor device and a method for forming the same.
- Transistor drive currents and hence switching speeds for CMOS (complementary metal oxide semiconductor) devices increase with increasing inversion capacitance.
- One of the factors that limit inversion capacitance is charge carrier depletion in conventional poly-Si gate electrodes during inversion.
- Alternative gate electrode materials for CMOS devices used in high performance logic circuits are needed to circumvent polysilicon (or poly-Si) depletion.
- metal gates whose charge carrier concentrations exceed the carrier concentration of poly-Si by at least two orders of magnitude, virtually eliminates the poly-Si depletion effect.
- metal gates whose charge carrier concentrations exceed the carrier concentration of poly-Si by at least two orders of magnitude, virtually eliminates the poly-Si depletion effect.
- the integration of metal gates into a conventional CMOS flow is complicated due to process integration difficulties.
- metal gates lack the thermal and chemical stability that is necessary to survive subsequent high temperature anneals. Deposition and patterning of metal gates are also presently immature.
- poly-SiGe poly-silicon-germanium gates instead of conventional poly-Si gates.
- Germanium (Ge) incorporation into poly-Si enhances doping to increase the amount of implanted dopants that can be activated. This is particularly true of dopants such as boron. The higher dopant activation results in a higher charge carrier concentration and a concomitant reduction in gate electrode depletion during inversion.
- SiGe is a mid-gap semiconductor material so that threshold voltages for NMOS and PMOS devices are almost equal in magnitude with opposite polarity. Complementary threshold voltages are necessary for proper CMOS circuit operation.
- a further advantage of poly-SiGe is that the material is chemically similar to poly-Si. This calls for minimal adjustment to the process integration scheme to accommodate poly-SiGe. Poly-SiGe is thermally stable and can survive the thermal cycling that devices are subjected to during the fabrication sequence.
- the embodiments of the present invention provide a poly-SiGe gate for a CMOS device that reduces charge carrier depletion.
- a gate stack for semiconductor MOS device comprises a dielectric film formed on a semiconductor substrate of said semiconductor MOS device, a first ⁇ -Si layer formed on the dielectric film, a poly-SiGe layer formed on the first ⁇ -Si layer, a second ⁇ -Si layer formed on the poly-SiGe layer, and a poly-Si layer formed on the second ⁇ -Si layer.
- a method of depositing an ⁇ -Si layer on a substrate comprises placing the substrate in a chamber, introducing a first Si-containing source gas into the chamber, and introducing a second Si-containing source gas into the chamber until an ⁇ -Si layer of less than about 50 ⁇ thickness has been deposited on said substrate.
- a method of forming a gate stack on a substrate comprises depositing a thin dielectric layer on top of the substrate, depositing a first ⁇ -Si layer on the dielectric film, depositing a poly-SiGe layer on the first ⁇ -Si layer, depositing a second ⁇ -Si layer on the poly-SiGe layer, and depositing a poly-Si layer on the second ⁇ -Si layer.
- FIG. 1 show a gate stack structure of an embodiment of the current invention.
- FIG. 2A shows the process flow of deposition a thin ⁇ -Si layer.
- FIG. 2B shows another process flow of depositing a thin ⁇ -Si layer.
- FIG. 3 shows the effect of GeH 4 :SiH 4 flow ratio on the poly-SiGe deposition rate and the Ge content in the film.
- FIG. 4 shows Auger analsis result of Ge incorporation in the poly-SiGe film.
- FIG. 5 shows conformal deposition of poly-SiGe, where the Ge content is 23 atomic %.
- FIG. 6A shows surface roughness of 800 ⁇ poly-SiGe deposited directly on thermal SiO 2 .
- the Ge content is 30 atomic %.
- FIG. 6B shows surface roughness of 800 ⁇ poly-SiGe deposited with an intervening 50 ⁇ ⁇ -Si seed layer deposited and with the process according to the invention.
- the Ge content is 30 atomic %.
- FIG. 7 shows the ⁇ -2 ⁇ XRD scan of poly-SiGe film showing the film crystallinity.
- the Ge content is 38 atomic %.
- FIG. 8A shows the surface roughness of 1000 ⁇ poly-SiGe/500 ⁇ poly-Si stack for direct deposition of poly-Si on poly-SiGe.
- FIG. 8B shows the surface roughness of 1000 ⁇ poly-SiGe/500 ⁇ poly-Si stack for for a stack containing 100 ⁇ ⁇ -Si at the interface between poly-SiGe and poly-Si.
- FIG. 9 shows the surface roughness of poly-SiGe as a function of Ge content and deposition temperature.
- Poly-SiGe gates where the concentration of Ge is between about 5 atomic % to about 40 atomic %, reduce gate electrode depletion during inversion, but they cannot be deposited directly on a SiO 2 -based gate dielectric because Ge etches the gate oxide resulting in volatile GeO formation. GeO formation inhibits the growth of a high quality poly-SiGe film. This chemical incompatibility makes it desirable to incorporate a thin ⁇ -Si (amorphous silicon) layer in between the gate dielectric and the poly-SiGe.
- the work function of the gate electrode depends on the work function of the material adjacent to the gate electrode. If the ⁇ -Si is too thick it will exhibit the work function of poly-Si after anneal. If the ⁇ -Si is sufficiently thin, Ge from the adjoining poly-SiGe will diffuse into the ⁇ -Si during subsequent thermal annealing and alter the work function to that of poly-SiGe.
- a fine-grained poly-Si or poly-SiGe is also desirable.
- implanted dopants are more uniformly distributed across the grain.
- dopants may segregate at the grain boundaries diminishing the electrically active dopant concentration.
- fine-grained films generally result in etched lines with smooth edges. Line edge roughness for gate electrodes can increase sub-threshold slope and threshold voltage spread, both of which are undesirable in high performance devices.
- silicide formation and transformation of the silicide from the initial as-formed high-resistivity phase to the lower resistivity phase following thermal anneal is favored by a finer grain size.
- One way to improve the morphology of poly-Si deposited on poly-SiGe is to insert a thin ⁇ -Si layer in between the poly-SiGe and poly-Si layers.
- the ⁇ -Si layer can retain its amorphous microstructure during poly-Si deposition.
- the growth of poly-Si on poly-SiGe with an intervening layer of ⁇ -Si will not be hetero-epitaxial. Therefore, the poly-Si grain structure will be more akin to that obtained when the film is deposited directly on an amorphous surface, such as an SiO 2 layer.
- FIG. 1 shows a gate stack that includes a poly-SiGe layer.
- a thin gate dielectric layer 202 is formed by depositing silicon dioxide 202 a , to a thickness between about 20 ⁇ to about 150 ⁇ , and an oxynitride to a thickness between about 20 ⁇ to about 100 ⁇ .
- the thin gate dielectric layer 202 may include just the silicon dioxide layer 202 a .
- a thin ⁇ -Si layer 207 is formed on top of the thin dielectric layer 202 . The thickness of the thin ⁇ -Si layer 207 is between about 30 ⁇ to about 50 ⁇ .
- a poly-SiGe layer 208 is deposited to a thickness between about 300 ⁇ to about 1000 ⁇ .
- a thin ⁇ -Si layer 209 is deposited to a thickness between about 50 ⁇ to about 300 ⁇ .
- a poly-silicon gate 204 is formed on top of the thin ⁇ -Si layer 209 to a thickness between about 300 ⁇ to about 1500 ⁇ .
- Source region 205 and drain region 206 are formed respectively on either side of and partially under the thin dielectric layer 202 .
- Deposition of the thin ⁇ -Si layer 207 , poly-SiGe layer 208 and thin ⁇ -Si layer 209 can be achieved by employing novel sequencing of process gases and use of alternative process gases in reactors that are amenable to rapid gas flow and temperature cycling.
- the invention is illustratively described below with reference to a mini-batch low pressure chemical vapor deposition (LPCVD) system, FlexStar, such as those commercially available from Applied Materials, Inc. of Santa Clara, Calif. However, it should be understood that the invention has utility in other system configurations such as single-wafer LPCVD systems or other applicable LPCVD systems. All of the experiments reported here were performed on FlexStar system.
- This FlexStar system utilizes cross wafer gas flow, i.e., the process gases flow across the wafer surface.
- Cross wafer gas flow has several advantages for this application. First, reactant and dopant concentrations are uniform across the surface of the wafer. Secondly, each wafer receives the same dose of reactants resulting in good wafer-to-wafer uniformity. Thirdly, the residence time of the gases in the vicinity of the wafer can be controlled through the gas flow. Control of gas residence times is crucial for ultra-thin depositions in which film deposition must begin simultaneously across the wafer. Residence times also define the extent of gas phase reactions.
- the wafer temperature can also be cycled for different process steps in a sequential process.
- the process temperature has to be increased by about 100° C. while transitioning from deposition of poly-SiGe to deposition of poly-Si.
- Temperature cycling is difficult to implement in a conventional vertical diffusion furnace, but the unique architecture of the FlexStar system makes this possible.
- the method 300 includes the following steps shown in FIG. 2A .
- the nucleation period should be less than 5 minutes to enable deposition of the thin ⁇ -Si film 207 shown in FIG. 1 .
- Si 2 H 6 After nucleation has been established, the flow of Si 2 H 6 is stopped and a flow of SiH 4 (a Si-containing source gas) or SiH 4 diluted with other gases, such as N 2 , Ar, H 2 or He, is introduced into the chamber until the desired thickness (30-50 ⁇ ) of ⁇ -Si is deposited at step 303 .
- SiH 4 a Si-containing source gas
- SiH 4 diluted with other gases such as N 2 , Ar, H 2 or He
- the method 310 includes the following steps. First, one or more substrates are placed in the process chamber at step 311 . Afterwards, a flow SiH 4 /Si 2 H 6 gas mixture, or SiH 4 /Si 2 H 6 diluted with other non-reactive gases, such as N 2 , Ar, H 2 or He, is introduced into the chamber for a short duration to initiate the nucleation of ⁇ -Si on the substrate surface at step 312 . The nucleation period should be less than 5 minutes to enable depositing the thin ⁇ -Si film 207 shown in FIG. 1 .
- Si 2 H 6 is stopped and the flow of SiH 4 (or SiH 4 diluted with other gases, such as N 2 , Ar, H 2 or He) is continued until the desired thickness (30-50 ⁇ ) of ⁇ -Si is deposited on top of the substrate at step 313 .
- SiH 4 or SiH 4 diluted with other gases, such as N 2 , Ar, H 2 or He
- nucleation delays can be reduced to nearly zero and an adequately low deposition rate can be achieved for controllable deposition of 30-50 ⁇ ⁇ -Si films.
- a specific example of processing conditions for the modified process to deposit a 50 ⁇ ⁇ -Si seed layer are described below.
- Step 1 0.2 sIm Si 2 H 6 , 2.0 sIm SiH 4 , 0.0 slm diluent N 2 , 0.4 Torr, 520° C., for 30 seconds.
- Step 2 0.0 slm Si 2 H 6 , 2.0 slm SiHJ 4 , 0.0 slm diluent N 2 , 0.4 Torr, 520° C., 150 seconds.
- Step 1 0.15 slm Si 2 H 6 , 2.3 slm diluent N 2 , 0.4 Torr, 520° C., 30 seconds.
- Step 2 2.0 slm SiH 4 , 0.0 slm diluent N 2 , 0.4 Torr, 520° C., 60 seconds.
- a complete process sequence also includes steps to stabilize the gas flows and wafer temperature prior to deposition, and chamber pump/purge steps that are performed following the deposition but prior to removing the substrates from the reactor.
- the gas sequencing concept can be applied over a wide range of process conditions and the specific choice of process conditions for ⁇ -Si are dependent primarily on the reactor configuration. Further, although the method has been described for SiH 4 and Si 2 H 6 since these are the most commonly used silicon containing source gases for poly-Si, other silicon containing source gases may be used in the invention.
- the result of the process according to the invention is that the seed layer is thin yet continuous as evidenced by the low surface roughness of the film.
- the inventors observed the roughness (Ra) of 100 ⁇ ⁇ -Si to be approximately 1.3 nm.
- the high surface roughness and the high R max value of 25 nm suggest that the film is semi-continuous. Surface roughness drops to less than 0.3 nm and R max drops to less than 4 nm with the process according to the invention indicating that the film is continuous.
- Characterization of the surface roughness and crystalline structure of the poly-SiGe deposited on the ⁇ -Si seed layer can be used to assess the effect of an improved ⁇ -Si seed layer on the poly-SiGe film.
- the GeH 4 :SiH 4 flow ratio can be modulated to adjust the Ge content in the film from pure ⁇ -Si to about 50 atomic % Ge (see FIG. 3 ).
- FIG. 3 shows the Ge content and deposition rate of poly-SiGe as a function of GeH 4 /SiH 4 ratio.
- Auger analysis shows that the poly-SiGe deposition process results in uniform Ge incorporation through the film ( FIG. 4 ). As shown in FIG. 4 , the ⁇ -Si seed layer is present at the interface with the oxide. The Ge content derived from Vegard's law which uses lattice spacing to estimate Ge content is in good agreement with Auger analysis (i.e. to within a few atomic %) confirming that the Ge occupies substitutional sites.
- the poly-SiGe film is also very conformal (see FIG. 5 ).
- the unique architecture of the parallel wafer processing reactor results in uniform film deposition, with 0.70% thickness uniformity for a 1617 ⁇ film.
- the uniformity is defined by dividing the standard deviation of the thickness to the mean thickness.
- the influence of the ⁇ -Si seed layer on the roughness of the poly-SiGe is dramatic. In the absence of a seed layer, the surface roughness of a 800 ⁇ poly-SiGe is about 39 ⁇ (see FIG. 6A ). In contrast, when a 800 ⁇ poly-SiGe is deposited on a 50 ⁇ ⁇ -Si seed layer described above, the surface roughness of the poly-SiGe film drops dramatically to about 21 ⁇ (see FIG. 6B ).
- the poly-SiGe film deposited on a smooth and continuous 50 ⁇ ⁇ -Si seed layer also has a well defined crystal structure as exemplified by the ⁇ -2 ⁇ X-ray XRD (X-ray defraction) scan (see FIG. 7 ).
- poly-SiGe/poly-Si stack For poly-SiGe/poly-Si stack, the morphology of poly-Si deposited on poly-SiGe is poor. The grain size distribution is broader compared to poly-Si deposited directly on the gate dielectric. The mean grain size is also larger since poly-Si growth on poly-SiGe is quasi-heteroepitaxial, i.e. the lattice spacing of poly-Si crystallites tends to follow the larger lattice spacing of the underlying poly-SiGe.
- the method according to the invention for forming a poly-SiGe/poly-Si stack includes the step of inserting of a thin ⁇ -Si layer in between the poly-SiGe and poly-Si layers.
- the ⁇ -Si layer retains its amorphous microstructure at the poly-Si deposition temperature.
- the growth of poly-Si on poly-SiGe with an intervening layer of ⁇ -Si is not hetero-epitaxial.
- the poly-Si grain structure is more akin to that obtained when the film is deposited directly on an amorphous surface such as thermal SiO 2 .
- the smaller poly-Si grain size that is obtained when the poly-Si is deposited on poly-SiGe with an interposed layer of ⁇ -Si is confirmed by the reduced surface roughness of the stack.
- the surface roughness of the stack is about 58 ⁇ (see FIG. 8A ).
- the surface roughness decreases to about 34 ⁇ (see FIG. 8B ) when a 100 ⁇ ⁇ -Si is interposed between the poly-Si and the poly-SiGe.
- the surface roughness of 1500 ⁇ poly-Si deposited directly on thermal SiO 2 is about 30 ⁇ .
- the deposition temperature is chosen to be the same as that for the poly-SiGe so that the ⁇ -Si seed layer, the poly-SiGe and ⁇ -Si interfacial layer are all deposited at the same temperature before the temperature is raised for the poly-Si deposition.
- ⁇ -Si Materials other than ⁇ -Si may be used for the interfacial layer, but ⁇ -Si is best suited since it gets transformed to poly-Si during subsequent thermal annealing performed to activate and to diffuse implanted dopants. Following the anneal, a poly-SiGe/poly-Si stack results. The ⁇ -Si seed layer gets transformed to poly-SiGe during the anneal since the Ge from the poly-SiGe diffuses into the ⁇ -Si seed layer. Another advantage is that the ⁇ -Si can be deposited at the same temperature using the same reactants as poly-SiGe.
- HSG hemispherical grained silicon
- ⁇ -Si is deposited with SiH 4 or SiH 4 diluted in He, H 2 , N 2 , or Ar at pressures of 0.5-1.5 Torr and temperatures from 560° C.-600° C. At an intermediate temperature between 560° C. and 600° C., the morphology of the ⁇ -Si changes from smooth films to rough films with hemispherical grains.
- the temperature window for this mode of deposition is 10° C., which is generally too narrow to control in a production environment.
- the deposition approach discussed above could be modified to make the process more manufacturable.
- the key concept is to dope the ⁇ -Si with Ge and adjust the deposition temperature to achieve hemispherical grain growth.
- Ge doping helps amorphous phase transition to the polycrystalline phase; thereby reducing the demands on temperature control. This transition temperature can drop 100° C. from 580° C. to 480° C. for high Ge content.
- Addition of Ge also increases the grain size that enlarges the size of the hemispherical grain.
- a common source for Ge is GeH 4 .
- GeH 4 is an etchant for SiO 2 native oxides thereby suppressing their growth. Native oxides tend to inhibit the formation of HSG-Si.
- the HSG-SiGe can be capped with an undoped layer of ⁇ -Si if necessary for process integration.
- Ge doping can be advantageously used in the other two HSG-Si deposition techniques as well. Some of the potential improvements are described as following.
- One of the techniques is to deposit a Ge doped ⁇ -Si layer and then vacuum anneal or anneal in an ambient of H 2 or GeH 4 /H 2 to form HSG-SiGe. If GeH 4 is used it should be sufficiently dilute to prevent Ge deposition, but high enough to etch native oxides that may grow during anneal. Native oxides tend to reduce surface diffusion and tend to inhibit the formation of HSG film.
- the other technique is to seed the ⁇ -Si base layer with SiGe nuclei instead of pure Si nuclei and then vacuum anneal or anneal in an ambient of H 2 or GeH 4 /H 2 to form HSG-SiGe. If GeH 4 is used it should be sufficiently dilute to prevent Ge deposition, but high enough to etch native oxides that may grow during anneal. Native oxides tend to reduce surface diffusion and tend to inhibit the formation of HSG film.
- the increase in surface roughness with the addition of Ge is seen in FIG. 9 .
- the surface roughness of the film increases sharply at a Ge content less than about 30%.
- the deposition temperature and the transition temperature are similar.
- deposition temperature as well as Ge content can control the transition to the HSG-SiGe phase. If the deposition temperature is increased at this critical Ge content, the surface roughness drops as the film transitions from the HSG-SiGe phase to the poly-SiGe phase.
- SiGe Yet another application for SiGe is the deposition of in-situ doped poly-Si.
- In-situ doped Si films are commonly used in memory devices as gate electrodes, word lines, bit lines, capacitor electrodes and capacitor plates. Generally, these films are deposited as ⁇ -Si that are in-situ doped with phosphorus, boron or arsenic. A high temperature post-deposition furnace anneal or rapid thermal anneal is performed to activate the dopant and transform the film into large grained low resistivity poly-Si.
- in-situ doped poly-SiGe films are obtained at process temperatures that would normally yield in-situ doped ⁇ -Si.
- These poly-SiGe films may be capped with ⁇ -Si or poly-Si.
- a seed layer of undoped or in-situ doped ⁇ -Si may be necessary to initiate poly-SiGe deposition.
- MEMS micromechanical systems
- TFT thin film transistor
- Thermal budget is a serious constraint for MEMS processing. Typically processing temperatures must remain below 600° C. to avoid damage to the micro-machined components. For applications such as these, a low temperature ( ⁇ 600° C.) in-situ doped poly-Si film with activated dopant is desirable.
- a low temperature ( ⁇ 600° C.) in-situ doped poly-Si film with activated dopant is desirable.
- Ge doping can be used to achieve such a film.
- First in-situ doped ⁇ -SiGe is deposited below the amorphous to polycrystalline transition for SiGe (typically 475-550° C.). The film is then annealed in-situ at temperatures below 600° C.
- the film transforms from the amorphous phase to the polycrystalline phase through a process known as solid phase recrystallization.
- Ge doping lowers the temperature for solid phase recrystallization of ⁇ -Si from above 600° C. to below 550° C.
- the poly-SiGe deposition techniques introduced for the primary application of advanced gate electrodes can be advantageously applied to HSG-Si formation, in-situ doped poly-Si deposition and low temperature in-situ doped poly-Si.
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US10/943,424 US20060060920A1 (en) | 2004-09-17 | 2004-09-17 | Poly-silicon-germanium gate stack and method for forming the same |
JP2007532373A JP2008514003A (ja) | 2004-09-17 | 2005-09-07 | ポリシリコンゲルマニウムゲートスタック及びその形成方法 |
PCT/US2005/031953 WO2006033838A2 (en) | 2004-09-17 | 2005-09-07 | Poly-silicon-germanium gate stack and method for forming the same |
EP05794913A EP1805802A2 (en) | 2004-09-17 | 2005-09-07 | Poly-silicon-germanium gate stack and method for forming the same |
CNA2005800314671A CN101027779A (zh) | 2004-09-17 | 2005-09-07 | 多晶-硅-锗栅极叠层及其形成方法 |
KR1020077007316A KR20070050493A (ko) | 2004-09-17 | 2005-09-07 | 폴리-실리콘-게르마늄 게이트 스택 및 그 제조 방법 |
US11/420,940 US7354848B2 (en) | 2004-09-17 | 2006-05-30 | Poly-silicon-germanium gate stack and method for forming the same |
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Also Published As
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WO2006033838A3 (en) | 2006-12-21 |
US7354848B2 (en) | 2008-04-08 |
CN101027779A (zh) | 2007-08-29 |
KR20070050493A (ko) | 2007-05-15 |
EP1805802A2 (en) | 2007-07-11 |
US20060231925A1 (en) | 2006-10-19 |
WO2006033838A2 (en) | 2006-03-30 |
JP2008514003A (ja) | 2008-05-01 |
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