TWM643324U

TWM643324U - Low power level converter with inhibit current circuit

Info

Publication number: TWM643324U
Application number: TW112201359U
Authority: TW
Inventors: 余建政; 黃聖源; 李泓毅
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2023-02-17
Filing date: 2023-02-17
Publication date: 2023-07-01

Abstract

本創作提出一種具有抑制電流電路之低功率電位轉換器，其係由一栓鎖電路(1)、一電位移位電路(2)、一第一電流抑制電路(3)以及一第二電流抑制電路(4)所組成，其中，該栓鎖電路(1)係用來保存和輸出差動輸入信號；該電位移位電路(2)係用以改變從該栓鎖電路(1)輸出的信號電位，以輸出該第二信號(V(OUT))；該第一電流抑制電路(3)係用來抑制電流流入該栓鎖電路(1)；而該第二電流抑制電路(4)係用以抑制電流流入該電位移位電路(2)。 This creation proposes a low-power potential converter with a current suppression circuit, which is composed of a latch circuit (1), a potential shift circuit (2), a first current suppression circuit (3) and a second current suppression circuit (4), wherein the latch circuit (1) is used to store and output differential input signals; the potential shift circuit (2) is used to change the signal potential output from the latch circuit (1) to output the second signal (V (OUT)); the first current suppression circuit (3) is used to suppress current flow into the latch circuit (1); and the second current suppression circuit (4) is used to suppress the current from flowing into the potential displacement circuit (2).

本創作所提出之具有抑制電流電路之低功率電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 The low-power potential converter with current suppression circuit proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and miniaturization of the device, and can effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

具有抑制電流電路之低功率電位轉換器 Low Power Potential Converter with Current Suppression Circuit

本創作提出一種具有抑制電流電路之低功率電位轉換器，尤指一由一栓鎖電路(1)、一電位移位電路(2)、一第一電流抑制電路(3)以及一第二電流抑制電路(4)所組成，以求獲得精確電壓位準轉換，同時亦能有效降低功率損耗之電子電路。 This creation proposes a low-power potential converter with a current suppression circuit, especially an electronic circuit composed of a latch circuit (1), a potential shift circuit (2), a first current suppression circuit (3) and a second current suppression circuit (4), in order to obtain accurate voltage level conversion and effectively reduce power loss.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC for short). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

第1圖係顯示另一先前技藝(prior art)之一鏡像型電位轉換器電路，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電位轉換器的性能也不會有太大的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 1 shows another prior art mirror-type potential converter circuit. The potential converter connects the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) together and to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The current of the crystal (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), therefore, Even if the output first high power supply voltage (VDDH) is changed, the performance of the potential converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

第2圖係顯示一先前技藝之一閂鎖型電位轉換器電路，其係使用一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 2 shows a latch-type potential shifter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), a second NMOS transistor (MN2) and an inverter (INV) to form a potential shifter circuit, wherein the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and ground (GND), and the first signal (V(IN) ) is also between the ground (GND) and the second highest power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the level shifter is in a stable state, no static current is generated in the latch type level shifter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down (pull down) and the first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up (pull up) and the second PMOS transistor (MP2) is turned off; When an NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will not be a current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional level shifter, when the second PMOS transistor (MP2) tends to be turned on (or turned off) and when the second NMOS transistor (MN2) is tended to be turned off (or turned on), there is a contention phenomenon for pulling up and pulling down the potential on the output terminal (OUT), so the second signal (V(OUT)) is relatively slow when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that the second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be instantaneously converted to 1.8 volts, the lower first signal (V(IN)) during the conversion period may not make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1) and the second NMOS transistor (MN2) completely turned on or completely turned off, which will cause a static current between the first high power supply voltage (VDDH) and the ground (GND). will increase power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。 Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), because the gate-source voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are the first high power supply voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high power supply voltage (VDDL). Therefore, the first high power supply that can make the latch-type potentiometer work normally is limited. response voltage (VDDH) range. When the second PMOS transistor (MP2) tends to be turned on (or turned off) and the second NMOS transistor (MN2) is turned off (or turned on), there is a contention phenomenon for pulling up and pulling down the potential on the output terminal (OUT), so the speed of the second signal (V(OUT)) is relatively slow when it changes to a low potential.

有鑑於此，本創作之主要目的係提出一種具有抑制電流電路之低功率電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 In view of this, the main purpose of this creation is to propose a low-power level converter with a current suppression circuit, which can not only accurately and quickly convert the first signal into a second signal, but also effectively reduce the competition between the pull-up path and the pull-down path, thereby reducing power loss.

由模擬結果證實，本創作所提出之具有抑制電流電路之低功率電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results prove that the low-power potential converter with the current suppression circuit proposed by this creation can not only convert the first signal into a second signal accurately and quickly, but also has multiple functions such as simple circuit structure and is conducive to the miniaturization of the device, and can effectively reduce power loss at the same time.

1:栓鎖電路 1: Latch circuit

2:電位移位電路 2: Potential displacement circuit

3:第一電流抑制電路 3: The first current suppression circuit

4:第二電流抑制電路 4: The second current suppression circuit

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: the third node

N4:第四節點 N4: the fourth node

N5:第五節點 N5: fifth node

N6:第六節點 N6: sixth node

N7:第七節點 N7: seventh node

I1:第一反相器 I1: the first inverter

GND:地 GND: ground

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: The second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: the first NMOS transistor

MN2:第二NMOS電晶體 MN2: The second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: The fourth NMOS transistor

INB:第二輸入端 INB: the second input terminal

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): the first signal

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): the second signal

EN:致能控制端 EN: enable console

ENB:反相致能控制端 ENB: Negative enable control terminal

VDDH:第一高電源供應電壓 VDDH: the first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

第1圖係顯示第一先前技藝中電位轉換器之電路圖；第2圖係顯示第二先前技藝中電位轉換器之電路圖；第3圖係顯示本創作較佳實施例之具有抑制電流電路之低功率電位轉換器之電路圖； Fig. 1 shows the circuit diagram of the potential converter in the first prior art; Fig. 2 shows the circuit diagram of the potential converter in the second prior art; Fig. 3 shows the circuit diagram of the low-power potential converter with the suppression current circuit of the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種具有抑制電流電路之低功率電位轉換器，如第3圖所示，其係由一栓鎖電路(1)、一電位移位電路(2)、一第一電流抑制電路(3)以及一第二電流抑制電路(4)所組成，其中，該栓鎖電路(1)係用來保存和輸出差動輸入信號；該電位移位電路(2)係用以改變從該栓鎖電路(1)輸出的信號電位，以輸出該第二信號(V(OUT))；該第一電流抑制電路(3)係用來抑制電流流入該栓鎖電路(1)；而該第二電流抑制電路(4)係用以抑制電流流入該電位移位電路(2)；該栓鎖電路(1)係由第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)、一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)、一第四PMOS電晶體(MP4)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三PMOS電晶體(MP3)的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第四PMOS電晶體(MP4)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該電位移位電路(2)係由一第六PMOS電晶體(MP6)以及一第三NMOS電晶體(MN3)所組成，其中，該第六PMOS電晶體(MP6)的源極連接至該第六節點(N6)，其閘極連接至該第三節點(N3)，而其汲極則與該第七節點(N7)相連接；該第三NMOS電晶體(MN3)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第七節點(N7)相連接；該第一電流抑制電路(3)係由一第四NMOS電晶體(MN4)所組成，其源極連接至地(GND)，其閘極連接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接；該第二電流抑制電路(4)係由一第五PMOS電晶體(MP5)所組成，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第六節點(N6)相連接；該第一高電源供應電壓(VDDH)係用以提供該具有抑制電流電路之低功率電位轉換器所需之第一高電源電壓；該第二高電源供應電壓(VDDL)係用以提供該具有抑制電流電路之低功率電位轉換器所需之第二高電源電壓；該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準；該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, this creation proposes a low-power potential converter with a current suppression circuit, as shown in Figure 3, it is composed of a latch circuit (1), a potential shift circuit (2), a first current suppression circuit (3) and a second current suppression circuit (4), wherein the latch circuit (1) is used to store and output differential input signals; the potential shift circuit (2) is used to change the signal potential output from the latch circuit (1) to output the second signal (V(OUT)); The first current suppression circuit (3) is used to suppress the current from flowing into the latch circuit (1); and the second current suppression circuit (4) is used to suppress the current from flowing into the potential displacement circuit (2); the latch circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4) and a The first inverter (I1) is formed, wherein the source of the first NMOS transistor (MN1) is connected to the fifth node (N5), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1) connected; the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the fourth PMOS transistor (MP4) The source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)) and provide a signal that is inverted from the first signal (V(IN)); the level shift circuit (2) is composed of a sixth PMOS transistor (MP6) and a third NMOS transistor ( MN3), wherein, the source of the sixth PMOS transistor (MP6) is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the seventh node (N7); the source of the third NMOS transistor (MN3) is connected to the ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the seventh node (N7); the first current suppression circuit (3) is It is composed of a fourth NMOS transistor (MN4), its source is connected to the ground (GND), its gate is connected to the inverting enabling control terminal (ENB), and its drain is connected to the fifth node (N5); the second current suppression circuit (4) is composed of a fifth PMOS transistor (MP5), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the enabling control terminal (EN), and its drain is connected to the sixth node (N6) is connected; the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the low power potential converter with the current suppression circuit; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the low power potential converter with the current suppression circuit High power supply voltage; the level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH); the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，當該致能控制端(EN)的信號為邏輯低位準時，該反相致能控制端(ENB)的信號為邏輯高位準，此時，該第五PMOS電晶體(MP5)和該第四NMOS電晶體(MN4)都導通(ON)，該電位轉換器處於主動(active)狀態；現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)截止(OFF)，該第三PMOS電晶體(MP3)導通(ON)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第二NMOS電晶體(MN2)、該第三NMOS電晶體(MN3)以及該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都導通(ON)，該第四PMOS電晶體(MP4)截止(OFF)，此時，由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通(ON)，而該第四PMOS電晶體(MP4)截止(OFF)，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，而該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，此時由於該第一PMOS電晶體 (MP1)和該第三PMOS電晶體(MP3)都導通，而該第一NMOS電晶體(MN1)截止，因此，該第三節點(N3)的電位會被拉升至一邏輯高位準，該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)都截止，而該第三NMOS電晶體(MN3)導通，因此，該第七節點(N7)的電位被拉降到一邏輯低位準(0伏特)，輸出端(OUT)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過具有抑制電流電路之低功率電位轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to FIG. 3 again, when the signal of the enable control terminal (EN) is at a logic low level, the signal at the inverting enable control terminal (ENB) is at a logic high level, at this time, the fifth PMOS transistor (MP5) and the fourth NMOS transistor (MN4) are both turned on (ON), and the potential converter is in an active state; now consider the steady-state operation of the potential converter when the first signal (V(IN)) is at a logic low level (0 volts): the first input terminal (IN) ) is simultaneously transmitted to the input of the first inverter (I1), the first NMOS transistor (MN1) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned off (OFF), the third PMOS transistor (MP3) is turned on (ON), and the first inverter (I1) transmits a logic high level (VDDL) to the second NMOS transistor (MN2), the third NMOS Transistor (MN3) and the gate of the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are both turned on (ON), and the fourth PMOS transistor (MP4) is turned off (OFF). The potential of the node (N4) will be pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) is transmitted to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on. (MP1) and the third PMOS transistor (MP3) are turned on, and the first NMOS transistor (MN1) is turned off, so the potential of the third node (N3) is pulled up to a logic high level, the logic high level of the third node (N3) makes the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) are turned off, and the third NMOS transistor (MN3) is turned on, so the potential of the seventh node (N7) is pulled Dropping to a logic low level (0 volts), the potential of the output terminal (OUT) will maintain a steady state value of a logic low level (0 volts). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by a low-power level converter with a current suppression circuit, and output from the output terminal (OUT).

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，具有抑制電流電路之低功率電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)導通(ON)，該第三PMOS電晶體(MP3)截止(OFF)，而該第一反相器(I1)傳送邏輯低位準到該第二NMOS電晶體(MN2)、該第三NMOS電晶體(MN3)以及該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都截止(OFF)，該第四PMOS電晶體(MP4)導通(ON)，此時，由於該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都導通，而該第三PMOS電晶體(MP3)截止(OFF)，該第三節點(N3)的電位會被拉降至一邏輯低位準，該第三節點(N3)上的邏輯低位準傳送到該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)的閘極，使得該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)都導通，此時由於該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都導通，而該第二NMOS電晶體(MN2)截止，該第四節點(N4)的電位會被拉升至一邏輯高位準，該第四節點(N4)的邏輯高位準使得該第一PMOS電晶體(MP1)截止，此時由於該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都截止，而該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都導通，因此，該第三節點(N3)的電位將維持在一邏輯低位準，而該第四節點(N4)的電位亦將維持在一邏輯高位準，由於該第三節點(N3)的邏輯低位準使得該第六PMOS電晶體(MP6)導通，此時，該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)都導通，而該第三NMOS電晶體(MN3)截止，因此，該第七節點(N7)的電位被拉升到一邏輯高位準，因此，輸出端(OUT)的電位會維持在一邏輯高位準的穩態值。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過具有抑制電流電路之低功率電位轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 Considering again that the first signal (V(IN)) is a logic high level (VDDL), the steady-state operation of the low-power level converter with a current suppression circuit: the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the gates of the first NMOS transistor (MN1) and the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned on (ON), and the third PMOS transistor (MP3) cut-off (OFF), and this first inverter (I1) transmits logic low level to the gate electrode of this second NMOS transistor (MN2), this 3rd NMOS transistor (MN3) and this 4th PMOS transistor (MP4), makes this 2nd NMOS transistor (MN2) and this 3rd NMOS transistor (MN3) all cut-off (OFF), this 4th PMOS transistor (MP4) conduction (ON), at this moment, due to this first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both turned on, and the third PMOS transistor (MP3) is turned off (OFF), the potential of the third node (N3) will be pulled down to a logic low level, and the logic low level on the third node (N3) is transmitted to the gates of the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6), so that both the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) are turned on, At this time due to the second PMOS transistor (MP2) and the The fourth PMOS transistor (MP4) is turned on, and the second NMOS transistor (MN2) is turned off, the potential of the fourth node (N4) will be pulled up to a logic high level, and the logic high level of the fourth node (N4) makes the first PMOS transistor (MP1) cut off. MN4) are all turned on, therefore, the potential of the third node (N3) will be maintained at a logic low level, and the potential of the fourth node (N4) will also be maintained at a logic high level, because the logic low level of the third node (N3) makes the sixth PMOS transistor (MP6) conduction, at this time, the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) are both turned on, and the third NMOS transistor (MN3) is turned off, so the seventh node ( The potential of N7) is pulled up to a logic high level, therefore, the potential of the output terminal (OUT) will maintain a steady state value of a logic high level. In other words, when the first signal (V(IN)) is a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by a low-power level converter with a current suppression circuit, and output from the output terminal (OUT).

請再參考圖3。當該致能控制端(EN)的信號為邏輯高位準，而反相致能控制端(ENB)的信號為邏輯低位準時，該第五PMOS電晶體(MP5)和該第四NMOS電晶體(MN4)都截止(OFF)，電位轉換器處於待機(standby)狀態。其工作原理於此不再累述。 Please refer to Figure 3 again. When the signal of the enable control terminal (EN) is logic high level and the signal of the inverting enable control terminal (ENB) is logic low level, both the fifth PMOS transistor (MP5) and the fourth NMOS transistor (MN4) are turned off (OFF), and the level switch is in a standby (standby) state. Its working principle will not be repeated here.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電壓位準轉換的目的便實現。 In summary, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and when the first signal (V(IN)) is at a logic high level (VDDL), the second signal (V(OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

本創作所提出之具有抑制電流電路之低功率電位轉換器經由Spice暫態分析模擬結果可証實，本創作所提出之具有抑制電流電路之低功率電位轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且可有效地減少輸出端(OUT)的上拉路徑與下拉路徑之間的互相競爭，進而降低功率損耗。 The low-power potential converter with suppressing current circuit proposed by this creation has been The simulation results of the Spice transient analysis can prove that the low-power level converter with the current suppression circuit proposed by this creation can not only quickly and accurately convert the first signal into a second signal, but also effectively reduce the competition between the pull-up path and the pull-down path of the output terminal (OUT), thereby reducing power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 While the invention has particularly disclosed and described selected preferred embodiments, those skilled in the art will appreciate that any possible changes in form or detail would not depart from the spirit and scope of the invention. Therefore, all changes in the relevant technical categories are included in the patent application scope of this creation.

1:栓鎖電路 1: Latch circuit

2:電位移位電路 2: Potential displacement circuit

3:第一電流抑制電路 3: The first current suppression circuit

4:第二電流抑制電路 4: The second current suppression circuit

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: the third node

N4:第四節點 N4: the fourth node

N5:第五節點 N5: fifth node

N6:第六節點 N6: sixth node

N7:第七節點 N7: seventh node

I1:第一反相器 I1: the first inverter

GND:地 GND: ground

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: The second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: the first NMOS transistor

MN2:第二NMOS電晶體 MN2: The second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: The fourth NMOS transistor

INB:第二輸入端 INB: the second input terminal

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): the first signal

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): the second signal

EN:致能控制端 EN: enable console

ENB:反相致能控制端 ENB: Negative enable control terminal

VDDH:第一高電源供應電壓 VDDH: the first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

Claims

一種具有抑制電流電路之低功率電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極以及一第三PMOS電晶體(MP3)的源極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極以及一第四PMOS電晶體(MP4)的源極連接在一起；一第三節點(N3)，用以將該第二PMOS電晶體(MP2)的閘極、該第三PMOS電晶體(MP3)的汲極以及一第一NMOS電晶體(MN1)的汲極連接在一起；一第四節點(N4)，用以將該第一PMOS電晶體(MP1)的閘極、該第四PMOS電晶體(MP4)的汲極以及一第二NMOS電晶體(MN2)的汲極連接在一起；一第五節點(N5)，用以將該第一NMOS電晶體(MN1)的源極、該第二NMOS電晶體(MN2)的源極以及一第四NMOS電晶體(MN4)的汲極連接在一起；一第六節點(N6)，用以將一第五PMOS電晶體(MP5)的汲極以及一第六PMOS電晶體(MP6)的源極連接在一起；一第七節點(N7)，用以將該第六PMOS電晶體(MP6)的汲極以及一第三NMOS電晶體(MN3)的汲極連接在一起；一第一輸入端(IN)，耦接於該第一NMOS電晶體(MN1)以及該第三PMOS電晶體(MP3)的閘極，用以提供該第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)的閘極、該第二NMOS電晶體(MN2)的閘極以及該第三NMOS電晶體(MN3)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第七節點(N7)，用以輸出該第二信號(V(OUT))；一致能控制端(EN)，耦接於該第五PMOS電晶體(MP5)的閘極，用以提供一致能控制信號；一反相致能控制端(ENB)，耦接於該第四NMOS電晶體(MN4)的閘極，用以提供與該致能控制信號反相的信號；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)以及該第五PMOS電晶體(MP5)的源極，用以提供該電位轉換器所需之第一高電源電壓；一第二高電源供應電壓(VDDL)，用以提供該電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一栓鎖電路(1)，耦接於該第一高電源供應電壓(VDDH)以及該第一輸入端(IN)，用來保存和輸出差動輸入信號；一電位移位電路(2)，耦接於該栓鎖電路(1)，用來改變從該栓鎖電路(1)輸出的信號電位，以輸出該第二信號(V(OUT))；一第一電流抑制電路(3)，耦接於該栓鎖電路(1)，用來抑制電流流入該栓鎖電路(1)；以及一第二電流抑制電路(4)，耦接於該電位移位電路(2)，用來抑制電流流入該電位移位電路(2)。 A low-power potential converter with a current suppression circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for connecting a drain of a first PMOS transistor (MP1) and a source of a third PMOS transistor (MP3); a second node (N2) for connecting a drain of a second PMOS transistor (MP2) and a source of a fourth PMOS transistor (MP4); A third node (N3) is used to connect the gate of the second PMOS transistor (MP2), the drain of the third PMOS transistor (MP3) and the drain of a first NMOS transistor (MN1); a fourth node (N4) is used to connect the gate of the first PMOS transistor (MP1), the drain of the fourth PMOS transistor (MP4) and the drain of a second NMOS transistor (MN2); a fifth node (N5) is used to connect the first The source of the NMOS transistor (MN1), the source of the second NMOS transistor (MN2) and the drain of a fourth NMOS transistor (MN4) are connected together; a sixth node (N6) is used to connect the drain of a fifth PMOS transistor (MP5) and the source of a sixth PMOS transistor (MP6); a seventh node (N7) is used to connect the drain of the sixth PMOS transistor (MP6) to a third NMOS transistor (MN 3) drains connected together; a first input terminal (IN), coupled to the gates of the first NMOS transistor (MN1) and the third PMOS transistor (MP3), for providing the first signal (V(IN)); A second input terminal (INB), coupled to the gate of the fourth PMOS transistor (MP4), the gate of the second NMOS transistor (MN2) and the gate of the third NMOS transistor (MN3), for providing an inversion signal of the first signal (V(IN)); an output terminal (OUT), coupled to the seventh node (N7), for outputting the second signal (V(OUT)); an enable control terminal (EN), coupled to the fifth PMOS The gate of the transistor (MP5) is used to provide an enable control signal; an inverting enable control terminal (ENB) is coupled to the gate of the fourth NMOS transistor (MN4) to provide a signal that is inverse to the enable control signal; a first high power supply voltage (VDDH) is coupled to the sources of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the fifth PMOS transistor (MP5) to provide the first voltage required by the potential converter. High power supply voltage; a second high power supply voltage (VDDL), used to provide the second high power supply voltage required by the level converter, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH); a latch circuit (1), coupled to the first high power supply voltage (VDDH) and the first input terminal (IN), used to store and output differential input signals; a potential shift circuit (2), coupled to the latch circuit (1), used to change from the latch circuit (1) The signal potential output by the lock circuit (1) to output the second signal (V(OUT)); a first current suppression circuit (3), coupled to the latch circuit (1), used to inhibit current from flowing into the latch circuit (1); and A second current suppression circuit (4), coupled to the potential displacement circuit (2), is used to suppress current from flowing into the potential displacement circuit (2).

如申請專利範圍第1項所述的具有抑制電流電路之低功率電位轉換器，其中該栓鎖電路(1)包括：一第一NMOS電晶體(MN1)，其源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第二NMOS電晶體(MN2)，其源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第三PMOS電晶體(MP3)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第四PMOS電晶體(MP4)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 As the low-power potential converter with current suppression circuit described in item 1 of the scope of the patent application, wherein the latch circuit (1) includes: a first NMOS transistor (MN1), its source is connected to the fifth node (N5), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a second NMOS transistor (MN2), its source is connected to the fifth node (N5), and its gate is connected to the second input terminal (INB ), and its drain is connected to the fourth node (N4); a first PMOS transistor (MP1), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the The second node (N2) is connected; a third PMOS transistor (MP3), its source is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a fourth PMOS transistor (MP4), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and A first inverter (I1), coupled to the first input terminal (IN), is used to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)).

如申請專利範圍第2項所述的具有抑制電流電路之低功率電位轉換器，其中該電位移位電路(2)包括：一第六PMOS電晶體(MP6)，其源極連接至該第六節點(N6)，其閘極連接至該第三節點(N3)，而其汲極則與該第七節點(N7)相連接；以及一第三NMOS電晶體(MN3)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第七節點(N7)相連接。 As the low-power potential converter with current suppression circuit described in item 2 of the scope of the patent application, wherein the potential shift circuit (2) includes: a sixth PMOS transistor (MP6), its source is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the seventh node (N7); and a third NMOS transistor (MN3), its source is connected to the ground (GND), and its gate is connected to the second input terminal (INB), And its drain is connected with the seventh node ( N7 ).

如申請專利範圍第3項所述的具有抑制電流電路之低功率電位轉換器，其中該第一電流抑制電路(3)係由一第四NMOS電晶體(MN4)所組成，其源極連接至地(GND)，其閘極連接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接。 As the low-power potential converter with current suppression circuit described in item 3 of the scope of patent application, wherein the first current suppression circuit (3) is composed of a fourth NMOS transistor (MN4), its source is connected to the ground (GND), its gate is connected to the inverting enabling control terminal (ENB), and its drain is connected to the fifth node (N5).

如申請專利範圍第4項所述的具有抑制電流電路之低功率電位轉換器，其中該第二電流抑制電路(4)係由一第五PMOS電晶體(MP5)所組成，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第六節點(N6)相連接。 As the low-power potential converter with current suppression circuit described in item 4 of the scope of patent application, wherein the second current suppression circuit (4) is composed of a fifth PMOS transistor (MP5), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the enabling control terminal (EN), and its drain is connected to the sixth node (N6).

如申請專利範圍第1項所述的具有抑制電流電路之低功率電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The low-power level converter with a current suppression circuit as described in claim 1 of the patent application, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL).

如申請專利範圍第6項所述的具有抑制電流電路之低功率電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The low-power level converter with a current suppression circuit as described in claim 6 of the patent application, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH).

如申請專利範圍第2項所述的具有抑制電流電路之低功率電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 According to the low-power level converter with current suppression circuit described in item 2 of the scope of the patent application, the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).