TWM649184U - Low voltage to high voltage signal level translator with improved performance - Google Patents

Low voltage to high voltage signal level translator with improved performance Download PDF

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TWM649184U
TWM649184U TW112202098U TW112202098U TWM649184U TW M649184 U TWM649184 U TW M649184U TW 112202098 U TW112202098 U TW 112202098U TW 112202098 U TW112202098 U TW 112202098U TW M649184 U TWM649184 U TW M649184U
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node
pmos transistor
drain
signal
nmos transistor
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TW112202098U
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Chinese (zh)
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余建政
李泓毅
黃聖源
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修平學校財團法人修平科技大學
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Abstract

本創作提出一種具改進性能之電壓位準轉換器，其係由一輸入電路(1)、一栓鎖電路(2)、一輸出控制電路(3)以及一電流抑制電路(4)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用來保存來自該輸入電路(1)的差動輸入信號；該輸出控制電路(3)係用以控制該電壓位準轉換器的輸出信號之電位；該電流抑制電路(4)係用來抑制電流流入該電壓位準轉換器。 This invention proposes a voltage level converter with improved performance, which is composed of an input circuit (1), a latch circuit (2), an output control circuit (3) and a current suppression circuit (4). Among them, the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); the output control circuit (3) is used To control the potential of the output signal of the voltage level converter; the current suppression circuit (4) is used to inhibit current from flowing into the voltage level converter.

本創作提出之具改進性能之電壓位準轉換器，不但能精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The voltage level converter with improved performance proposed by this invention can not only accurately convert the first signal into a second signal, but also effectively reduce power loss.

Description

具改進性能之電壓位準轉換器 Voltage level converter with improved performance

本創作係有關一種具改進性能之電壓位準轉換器，尤指利用一輸入電路(1)、一栓鎖電路(2)、一輸出控制電路(3)以及一電流抑制電路(4)所組成，以求獲得精確電壓位準轉換且有效地降低功率損耗之電子電路。 The invention relates to a voltage level converter with improved performance, in particular, it is composed of an input circuit (1), a latch circuit (2), an output control circuit (3) and a current suppression circuit (4) , in order to achieve accurate voltage level conversion and effectively reduce the power loss of electronic circuits.

電壓位準轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level converter is an electronic circuit used to communicate signals between different integrated circuits (ICs for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the voltage level converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal. .

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準轉換器，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一具改進性能之電壓位準轉換器，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而輸入電壓(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。輸入電壓(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連 接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電壓位準轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)截止(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而截止第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)截止時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而截止第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a prior art latch-type voltage level converter using a first PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistor (MP1) , a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2) and an inverter (INV) to form a voltage level converter with improved performance, wherein the bias voltage of the inverter (INV) is the second highest potential voltage (VDDL) and ground (GND), and the input voltage (V(IN )) is also between ground (GND) and the second highest potential voltage (VDDL). The input voltage (V(IN)) and the inverted input voltage signal output through the inverter (INV) are connected respectively. Connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled manner of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the latch-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, thereby pulling up the gate potential of the second PMOS transistor (MP2) and turning off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, causing the first PMOS transistor (MP2) to be turned on. The gate potential of the transistor (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準轉換器在第二PMOS電晶體(MP2)趨近於導通(或截止)與在第二NMOS電晶體(MN2)趨近於截止(或導通)的過程中，對於輸出節點(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此輸出電壓信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當輸入電壓(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無 法瞬間轉換至1.8伏特，因此，在轉換期間的較低輸入電壓(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全截止，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional voltage level converter, when the second PMOS transistor (MP2) approaches to be turned on (or turned off) and the second NMOS transistor (MN2) approaches to be turned off (or turned on), for The rising and falling potentials on the output node (OUT) compete with each other, so the output voltage signal (V(OUT)) is slower when it transitions to a low potential. In addition, consider that when the input voltage (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) turns on, and the gate of the second PMOS transistor (MP2) becomes low, so that the The two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts has no cannot instantaneously convert to 1.8 volts, therefore the lower input voltage (V(IN)) during conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor ( MN1) and the second NMOS transistor (MN2) are fully turned on or completely cut off, which will cause a static current (static current) to exist between the first high potential voltage (VDDH) and the ground (GND). This static current will Increased power loss.

再者，閂鎖型的電壓位準轉換器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準轉換器正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH) due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The voltage is the first high potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that allows the latch-type voltage level converter to operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準轉換器，該電壓位準轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型電壓位準轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準轉換器的性能也不會有太大的改變。因此，鏡像型的電壓位準轉換器可以適用在各種輸出電壓電路。 Figure 2 shows another prior art mirror type voltage level converter. The voltage level converter is connected by connecting the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror voltage level converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes, the voltage The performance of the level converter will not change much either. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)截止時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種具改進性能之電壓位準轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地抑制上拉路徑和下拉路徑之間的競爭，進而降低功率損耗。 In view of this, the main purpose of this invention is to propose a voltage level converter with improved performance, which not only can accurately and quickly convert the first signal into a second signal, but also can effectively suppress the pull-up path and pull-down competition between paths, thereby reducing power loss.

本創作提出一種具改進性能之電壓位準轉換器，其係由一輸入電路(1)、一栓鎖電路(2)、一輸出控制電路(3)以及一電流抑制電路(4)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用來保存來自該輸入電路(1)的差動輸入信號；該輸出控制電路(3)係用以控制該電壓位準轉換器的輸出信號之電位；該電流抑制電路(4)係用來抑制電流流入該電壓位準轉換器。 This invention proposes a voltage level converter with improved performance, which is composed of an input circuit (1), a latch circuit (2), an output control circuit (3) and a current suppression circuit (4). Among them, the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); the output control circuit (3) is used To control the potential of the output signal of the voltage level converter; the current suppression circuit (4) is used to inhibit current from flowing into the voltage level converter.

由模擬結果證實，本創作所提出之具改進性能之電壓位準轉換器，不但能精確且快速地將一第一信號轉換為一第二信號，並且可以有效地減少功率損耗。 The simulation results confirm that the voltage level converter with improved performance proposed in this invention can not only convert a first signal into a second signal accurately and quickly, but also can effectively reduce power loss.

1:輸入電路 1:Input circuit

2:栓鎖電路 2:Latching circuit

3:輸出控制電路 3: Output control circuit

4:電流抑制電路 4: Current suppression circuit

N1:第一節點 N1: first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: fourth node

N5:第五節點 N5: fifth node

GND:地 GND: ground

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: The second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: The fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: The second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: The fourth NMOS transistor

MN5:第五NMOS電晶體 MN5: The fifth NMOS transistor

EN:致能控制端 EN: Enable control terminal

IN:第一輸入端 IN: first input terminal

V(IN):第一信號 V(IN): first signal

INB:第二輸入端 INB: second input terminal

I1:第一反相器 I1: first inverter

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): second signal

OUTB:反相輸出端 OUTB: inverting output terminal

V(OUTB):反相輸出信號 V(OUTB): inverted output signal

VDDH:第一高電源供應電壓 VDDH: first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: second highest power supply voltage

第1圖 係顯示第一先前技藝中電壓位準轉換器之電路圖； 第2圖 係顯示第二先前技藝中電壓位準轉換器之電路圖；第3圖 係顯示本創作較佳實施例之具改進性能之電壓位準轉換器之電路圖； Figure 1 is a circuit diagram showing a first prior art voltage level converter; Figure 2 is a circuit diagram showing a second prior art voltage level converter; Figure 3 is a circuit diagram showing a voltage level converter with improved performance according to the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種具改進性能之電壓位準轉換器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)、一輸出控制電路(3)以及一電流抑制電路(4)所組成，其中，該輸入電路(1)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號；其係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三NMOS電晶體(MN3)的源極相連接；該第二NMOS電晶體(MN2)的源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四NMOS電晶體(MN4)的源極相連接；該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係用來保存轉換的輸出電位並且控制漏電流；其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三NMOS電晶體(MN3)、一第四NMOS電晶體(MN4)、一第五PMOS電晶體(MP5)以及一第六PMOS電晶體(MP6)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節 點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三NMOS電晶體(MN3)的源極連接至該第一NMOS電晶體(MN1)的汲極，其閘極連接至該第四節點(N4)，而其汲極則與該第三節點(N3)相連接；該第四NMOS電晶體(MN4)的源極連接至該第二NMOS電晶體(MN2)的汲極，其閘極連接至該第三節點(N3)，而其汲極則與該第四節點(N4)相連接；該第五PMOS電晶體(MP5)的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)的汲極相連接；該第六PMOS電晶體(MP6)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該輸出控制電路(3)係用以控制該電壓位準轉換器的輸出信號之電位；其係由一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該電流抑制電路(4)係用來抑制電流流入該電壓位準轉換器；其係由一第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連接至該致能控 制端(EN)，而其汲極則與該第五節點(N5)相連接；該第一高電源供應電壓(VDDH)係用以提供該電壓位準轉換器所需之第一高電源電壓，該第二高電源供應電壓(VDDL)係用以提供該電壓位準轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，而該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, this invention proposes a voltage level converter with improved performance, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2), and an output control circuit (3 ) and a current suppression circuit (4), wherein the input circuit (1) is used to provide the first signal (V(IN)) and the inverted signal of the first signal (V(IN)); It is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to To the fifth node (N5), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the third NMOS transistor (MN3); the second NMOS transistor The source of (MN2) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the fourth NMOS transistor (MN4) ; The first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal with the first signal (V(IN) ) inverted signal; the latch circuit (2) is used to preserve the converted output potential and control the leakage current; it is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a It is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth PMOS transistor (MP5) and a sixth PMOS transistor (MP6), wherein the first PMOS transistor ( The source of MP1) is connected to the first high power supply voltage (VDDH), and its gate is connected to the fourth node point (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), and its gate is connected to to the third node (N3), and its drain is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the drain of the first NMOS transistor (MN1) pole, its gate is connected to the fourth node (N4), and its drain is connected to the third node (N3); the source of the fourth NMOS transistor (MN4) is connected to the second NMOS transistor The drain electrode of the crystal (MN2), its gate electrode is connected to the third node (N3), and its drain electrode is connected to the fourth node (N4); the source electrode of the fifth PMOS transistor (MP5) is connected To the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the drain of the third node (N3); the sixth PMOS transistor (MP6 ) has its source connected to the second node (N2), its gate connected to the second input terminal (INB), and its drain connected to the fourth node (N4); the output control circuit (3 ) is used to control the potential of the output signal of the voltage level converter; it is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the third PMOS transistor The source of (MP3) is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); The source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2 ) are connected to each other; the current suppression circuit (4) is used to suppress the flow of current into the voltage level converter; it is composed of a fifth NMOS transistor (MN5), its source is connected to the ground (GND), and its source is connected to the ground (GND). The gate is connected to the enable control The control terminal (EN), and its drain is connected to the fifth node (N5); the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the voltage level converter , the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the voltage level converter, and the level of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage. The level of the supply voltage (VDDH), the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is between 0 volts and Corresponding waveforms between 1.8 volts.

請再參閱第3圖，當該致能控制端(EN)的信號為邏輯高位準時，該第五NMOS電晶體(MN5)導通(ON)，該電壓位準轉換器處於主動(active)狀態；現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)、該第五PMOS電晶體(MP5)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)關閉(OFF)，而該第三PMOS電晶體(MP3)和該第五PMOS電晶體(MP5)都導通(ON)，此時該第三節點(N3)的電位被拉升至一接近第一高電位電壓(VDDH)之高電位，該第三節點(N3)的高電位使得該第二PMOS電晶體(MP2)關閉(OFF)、該第四NMOS電晶體(MN4)導通(ON)；而該第一反相器(I1)傳送第二高電位電壓(VDDL)到該第二NMOS電晶體(MN2)、該第六PMOS電晶體(MP6)以及該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)導通(ON)，而該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都關閉(OFF)，此時，由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通(ON)，該第二PMOS電晶體(MP2)、該第四PMOS 電晶體(MP4)和該第六PMOS電晶體(MP6)都關閉(OFF)，因此，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，而該第四節點(N4)的低電位使得該第一PMOS電晶體(MP1)導通(ON)、該第三NMOS電晶體(MN3)關閉(OFF)，此時，由於該第一PMOS電晶體(MP1)、該第三PMOS電晶體(MP3)和該第五PMOS電晶體(MP5)都導通(ON)，而該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都關閉(OFF)，因此，該第三節點(N3)的電位會維持在一邏輯高位準，而該第四節點(N4)的的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過電壓位準轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to Figure 3 again. When the signal of the enable control terminal (EN) is at a logic high level, the fifth NMOS transistor (MN5) is turned on (ON), and the voltage level converter is in an active state; Now consider the steady-state operation of the voltage level converter when the first signal (V(IN)) is a logic low level (0 volts): the logic low level on the first input terminal (IN) is simultaneously transmitted to the first The input terminal of the inverter (I1), the first NMOS transistor (MN1), the fifth PMOS transistor (MP5) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) is turned off (OFF), and the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned on (ON). At this time, the potential of the third node (N3) is pulled up to a Close to the high potential of the first high potential voltage (VDDH), the high potential of the third node (N3) causes the second PMOS transistor (MP2) to turn off (OFF) and the fourth NMOS transistor (MN4) to turn on (ON) ); and the first inverter (I1) transmits the second high potential voltage (VDDL) to the second NMOS transistor (MN2), the sixth PMOS transistor (MP6) and the fourth PMOS transistor (MP4 ) gate, causing the second NMOS transistor (MN2) to be turned on (ON), while the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned off (OFF). At this time, due to The second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on (ON), and the second PMOS transistor (MP2) and the fourth PMOS The transistor (MP4) and the sixth PMOS transistor (MP6) are both turned OFF. Therefore, the potential of the fourth node (N4) will be pulled down to a logic low level (0 volts), and the fourth node (N4) will be pulled down to a logic low level (0 volts). The low potential of the node (N4) causes the first PMOS transistor (MP1) to be turned on (ON) and the third NMOS transistor (MN3) to be turned off (OFF). At this time, due to the first PMOS transistor (MP1), The third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned on (ON), and the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off (OFF) , therefore, the potential of the third node (N3) will maintain a logic high level, and the potential of the fourth node (N4) will maintain a steady-state value of a logic low level (0 volts). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through the voltage level converter, and is output from the output terminal (OUT) output.

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)、該第五PMOS電晶體(MP5)以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)導通(ON)，而該第三PMOS電晶體(MP3)和該第五PMOS電晶體(MP5)都關閉(OFF)；而該第一反相器(I1)傳送一邏輯低位準(0伏特)到該第二NMOS電晶體(MN2)、該第六PMOS電晶體(MP6)以及該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)關閉(OFF)，而該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都導通(ON)，此時，由於該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都導通(ON)，而該第四NMOS電晶體(MN4)關閉(OFF)，因此，該第四節點(N4)的電位會被拉升至一 邏輯高位準，再者，該第四節點(N4)的高電位傳送到該第一PMOS電晶體(MP1)和該第一NMOS電晶體(MN1)的閘極，使得該第一PMOS電晶體(MP1)關閉(OFF)、該第三NMOS電晶體(MN3)導通(ON)，此時，由於該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都導通(ON)，而該第一PMOS電晶體(MP1)、該第三PMOS電晶體(MP3)以及該第五PMOS電晶體(MP5)都關閉(OFF)，因此，該第三節點(N3)的電位會被拉降至一邏輯低位準(0伏特)，再者，該第三節點(N3)的邏輯低位準傳送到該第二PMOS電晶體(MP2)和該第四NMOS電晶體(MN4)的閘極，使得該第二PMOS電晶體(MP2)導通(ON)、該第四NMOS電晶體(MN4)關閉(OFF)，此時由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都關閉，而該第二PMOS電晶體(MP2)、該第四PMOS電晶體(MP4)以及該第六PMOS電晶體(MP6)都導通(ON)，因此，該第四節點(N4)的電位會維持在邏輯高位準的穩態值。質言之，第一信號(V(IN))為邏輯高位準(1.2伏特)時，經過電壓位準轉換器轉換成具高位準(VDDH)的第二信號，由輸出端(OUT)輸出。 Consider again the steady-state operating situation of the voltage level converter when the first signal (V(IN)) is a logic high level (VDDL): the logic high level on the first input terminal (IN) is simultaneously transmitted to the first inverter. The input terminal of the inverter (I1), the first NMOS transistor (MN1), the fifth PMOS transistor (MP5) and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor ( MN1) is turned on (ON), and the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned off (OFF); and the first inverter (I1) transmits a logic low level (0 Volts) to the gates of the second NMOS transistor (MN2), the sixth PMOS transistor (MP6) and the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned off (OFF) , and the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned on (ON). At this time, because the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are turned on (ON), and the fourth NMOS transistor (MN4) is turned off (OFF), therefore, the potential of the fourth node (N4) will be pulled up to a level Logic high level, furthermore, the high potential of the fourth node (N4) is transmitted to the gates of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), so that the first PMOS transistor ( MP1) is turned off (OFF) and the third NMOS transistor (MN3) is turned on (ON). At this time, since the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned on (ON), The first PMOS transistor (MP1), the third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are all turned off (OFF). Therefore, the potential of the third node (N3) will be pulled drops to a logic low level (0 volts), and further, the logic low level of the third node (N3) is transmitted to the gates of the second PMOS transistor (MP2) and the fourth NMOS transistor (MN4), The second PMOS transistor (MP2) is turned on (ON) and the fourth NMOS transistor (MN4) is turned off (OFF). At this time, due to the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) ) are all turned off, and the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are all turned on (ON), therefore, the fourth node (N4) The potential will maintain a steady-state value at a logic high level. In other words, when the first signal (V(IN)) is at a logic high level (1.2 volts), it is converted into a second signal with a high level (VDDH) through the voltage level converter, and is output from the output terminal (OUT).

請再參考圖3。當該致能控制端(EN)的信號為邏輯低位準時，該第五NMOS電晶體(MN5)截止(OFF)，電壓位準轉換器處於待機(standby)狀態。其工作原理於此不再累述。 Please refer to Figure 3 again. When the signal of the enable control terminal (EN) is at a logic low level, the fifth NMOS transistor (MN5) is turned off (OFF), and the voltage level converter is in a standby state. Its working principle will not be repeated here.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電壓位準轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal When (V(IN)) is a logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

本創作所提出之電壓位準轉換器經由Spice暫態分析模擬結果可証實，本創作所提出之具改進性能之電壓位準轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The Spice transient analysis simulation results of the voltage level converter proposed in this creation can confirm that the voltage level converter with improved performance proposed in this creation can not only quickly and accurately convert the first signal into a second signal, and can effectively reduce power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes selected preferred embodiments, those familiar with the art will understand that any possible changes in form or details may be made without departing from the spirit and scope of the invention. Therefore, all changes within the relevant technical scope are included in the patentable scope of this creation.

1:輸入電路 1:Input circuit

2:栓鎖電路 2:Latching circuit

3:輸出控制電路 3: Output control circuit

4:電流抑制電路 4: Current suppression circuit

N1:第一節點 N1: first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: fourth node

N5:第五節點 N5: fifth node

GND:地 GND: ground

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: The second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: The fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: The second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: The fourth NMOS transistor

MN5:第五NMOS電晶體 MN5: The fifth NMOS transistor

EN:致能控制端 EN: Enable control terminal

IN:第一輸入端 IN: first input terminal

V(IN):第一信號 V(IN): first signal

INB:第二輸入端 INB: second input terminal

I1:第一反相器 I1: first inverter

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): second signal

OUTB:反相輸出端 OUTB: inverting output terminal

V(OUTB):反相輸出信號 V(OUTB): inverted output signal

VDDH:第一高電源供應電壓 VDDH: first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: second highest power supply voltage

Claims (8)

一種具改進性能之電壓位準轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極以及一第五PMOS電晶體(MP5)的源極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極以及一第六PMOS電晶體(MP6)的源極連接在一起；一第三節點(N3)，用以將該第二PMOS電晶體(MP2)的閘極、該第五PMOS電晶體(MP5)的汲極以及一第三NMOS電晶體(MN3)的汲極連接在一起；一第四節點(N4)，用以將該第一PMOS電晶體(MP1)的閘極、該第六PMOS電晶體(MP6)的汲極以及一第四NMOS電晶體(MN4)的汲極連接在一起；一第五節點(N5)，用以將一第一NMOS電晶體(MN1)的源極、一第二NMOS電晶體(MN2)的源極以及一第五NMOS電晶體(MN5)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)、該第五PMOS電晶體(MP5)以及該第一NMOS電晶體(MN1)的閘極，用以提供一第一信號(V(IN))； 一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)、該第六PMOS電晶體(MP6)以及該第二NMOS電晶體(MN2)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一反相輸出端(OUTB)，耦接於該第三節點(N3)，用以輸出該第二信號(V(OUT))的反相輸出信號(V(OUTB))；一致能控制端(EN)，耦接於該第五NMOS電晶體(MN5)的閘極，用以提供一致能控制信號；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)、該第三PMOS電晶體(MP3)以及該第四PMOS電晶體(MP4)的源極，用以提供該電壓位準轉換器所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，用以提供該電壓位準轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一輸入電路(1)，耦接於該第一輸入端(IN)，用以提供差動輸入信號；一栓鎖電路(2)，耦接於該第一高電源供應電壓(VDDH)，用來保存轉換的輸出電位並且控制漏電流； 一輸出控制電路(3)，用以控制該電壓位準轉換器的輸出信號之電位；以及一電流抑制電路(4)，耦接於該輸入電路(1)，用來抑制電流流入該電壓位準轉換器。 A voltage level converter with improved performance for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: a first node (N1) for Connect the drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the source of a fifth PMOS transistor (MP5) together; a second node (N2) , used to connect the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the source of a sixth PMOS transistor (MP6) together; a third node (N3), used to connect the gate electrode of the second PMOS transistor (MP2), the drain electrode of the fifth PMOS transistor (MP5) and the drain electrode of a third NMOS transistor (MN3) together; The fourth node (N4) is used to connect the gate of the first PMOS transistor (MP1), the drain of the sixth PMOS transistor (MP6) and the drain of a fourth NMOS transistor (MN4). Together; a fifth node (N5), used to connect the source of a first NMOS transistor (MN1), the source of a second NMOS transistor (MN2) and the drain of a fifth NMOS transistor (MN5). poles are connected together; a first input terminal (IN) is coupled to the gates of the third PMOS transistor (MP3), the fifth PMOS transistor (MP5) and the first NMOS transistor (MN1), Used to provide a first signal (V(IN)); A second input terminal (INB) is coupled to the gates of the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6) and the second NMOS transistor (MN2) to provide the third An inverted signal of a signal (V(IN)); an output terminal (OUT) coupled to the fourth node (N4) for outputting the second signal (V(OUT)); an inverted output terminal (OUTB), coupled to the third node (N3), for outputting the inverted output signal (V(OUTB)) of the second signal (V(OUT)); the consistent energy control terminal (EN) is coupled to The gate of the fifth NMOS transistor (MN5) is used to provide a consistent energy control signal; a first high power supply voltage (VDDH) is coupled to the first PMOS transistor (MP1) and the second PMOS The sources of the transistor (MP2), the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4) are used to provide the first high potential voltage required by the voltage level converter; a second A high power supply voltage (VDDL) is used to provide the second high potential voltage required by the voltage level converter. The potential of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage (VDDH). potential; an input circuit (1) coupled to the first input terminal (IN) for providing a differential input signal; a latch circuit (2) coupled to the first high power supply voltage (VDDH ), used to save the converted output potential and control leakage current; An output control circuit (3) for controlling the potential of the output signal of the voltage level converter; and a current suppression circuit (4) coupled to the input circuit (1) for suppressing current from flowing into the voltage level. Quasi-converter. 如申請專利範圍第1項所述的具改進性能之電壓位準轉換器，其中該輸入電路(1)包括：一第一NMOS電晶體(MN1)，其源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三NMOS電晶體(MN3)的源極相連接；一第二NMOS電晶體(MN2)，其源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四NMOS電晶體(MN4)的源極相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The voltage level converter with improved performance as described in item 1 of the patent application, wherein the input circuit (1) includes: a first NMOS transistor (MN1), the source of which is connected to the fifth node (N5 ), its gate is connected to the first input terminal (IN), and its drain is connected to the source of the third NMOS transistor (MN3); a second NMOS transistor (MN2), its source Connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its drain is connected to the source of the fourth NMOS transistor (MN4); and a first inverter The phase device (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal inverted with the first signal (V(IN)). . 如申請專利範圍第2項所述的具改進性能之電壓位準轉換器，其中該栓鎖電路(2)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接； 一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第五PMOS電晶體(MP5)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)的汲極相連接；一第六PMOS電晶體(MP6)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；一第三NMOS電晶體(MN3)，其源極連接至該第一NMOS電晶體(MN1)的汲極，其閘極連接至該第四節點(N4)，而其汲極則與該第三節點(N3)相連接；以及一第四NMOS電晶體(MN4)，其源極連接至該第二NMOS電晶體(MN2)的汲極，其閘極連接至該第三節點(N3)，而其汲極則與該第四節點(N4)相連接。 The voltage level converter with improved performance as described in item 2 of the patent application, wherein the latch circuit (2) includes: a first PMOS transistor (MP1), the source of which is connected to the first high power supply Supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); A second PMOS transistor (MP2) has its source connected to the first high power supply voltage (VDDH), its gate connected to the third node (N3), and its drain connected to the second node (N3). N2) is connected; a fifth PMOS transistor (MP5) has its source connected to the first node (N1), its gate connected to the first input terminal (IN), and its drain connected to the first node (N1). The drains of the three nodes (N3) are connected; a sixth PMOS transistor (MP6) has its source connected to the second node (N2), its gate connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); a third NMOS transistor (MN3) has its source connected to the drain of the first NMOS transistor (MN1) and its gate connected to the fourth node. node (N4), and its drain is connected to the third node (N3); and a fourth NMOS transistor (MN4), its source is connected to the drain of the second NMOS transistor (MN2), Its gate is connected to the third node (N3), and its drain is connected to the fourth node (N4). 如申請專利範圍第3項所述的具改進性能之電壓位準轉換器，其中該輸出控制電路(3)包括：一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及 一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 The voltage level converter with improved performance as described in item 3 of the patent application, wherein the output control circuit (3) includes: a third PMOS transistor (MP3), the source of which is connected to the first high power supply Supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); and A fourth PMOS transistor (MP4), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2) is connected. 如申請專利範圍第4項所述的具改進性能之電壓位準轉換器，其中該電流抑制電路(4)係由一第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連接至該致能控制端(EN)，而其汲極則與該第五節點(N5)相連接。 The voltage level converter with improved performance as described in item 4 of the patent application, wherein the current suppression circuit (4) is composed of a fifth NMOS transistor (MN5), the source of which is connected to the ground (GND). ), its gate is connected to the enable control terminal (EN), and its drain is connected to the fifth node (N5). 如申請專利範圍第1項所述的具改進性能之電壓位準轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The voltage level converter with improved performance as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). 如申請專利範圍第6項所述的具改進性能之電壓位準轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 In the voltage level converter with improved performance as described in claim 6, the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). 如申請專利範圍第2項所述的具改進性能之電壓位準轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The voltage level converter with improved performance as described in claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).
TW112202098U 2023-03-10 2023-03-10 Low voltage to high voltage signal level translator with improved performance TWM649184U (en)

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