TWM586017U - Low power level shifter circuit - Google Patents

Low power level shifter circuit Download PDF

Info

Publication number
TWM586017U
TWM586017U TW108204329U TW108204329U TWM586017U TW M586017 U TWM586017 U TW M586017U TW 108204329 U TW108204329 U TW 108204329U TW 108204329 U TW108204329 U TW 108204329U TW M586017 U TWM586017 U TW M586017U
Authority
TW
Taiwan
Prior art keywords
node
signal
nmos transistor
gate
drain
Prior art date
Application number
TW108204329U
Other languages
Chinese (zh)
Inventor
余建政
邱崑霖
賴永瑄
黃柏偉
Original Assignee
修平學校財團法人修平科技大學
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 修平學校財團法人修平科技大學 filed Critical 修平學校財團法人修平科技大學
Priority to TW108204329U priority Critical patent/TWM586017U/en
Publication of TWM586017U publication Critical patent/TWM586017U/en

Links

Landscapes

  • Logic Circuits (AREA)

Abstract

本創作提出一種低功率電位轉換器，其係由一電位轉換電路(1)、一輸入電路(2)、一輸出控制開關(3)以及一電流阻隔開關(4)所組成，其中，該電位轉換電路(1)係用來做為電位轉換；該輸入電路(2)係用來提供差動輸入信號；該輸出控制開關(3)用以減少在待機模式時之暫態電流消耗；而該電流阻隔開關(4)係用以控制該電位轉換器之不同操作模式。 This creation proposes a low-power potential converter, which is composed of a potential conversion circuit (1), an input circuit (2), an output control switch (3), and a current blocking switch (4). The conversion circuit (1) is used for potential conversion; the input circuit (2) is used to provide a differential input signal; the output control switch (3) is used to reduce the transient current consumption in the standby mode; and the The current blocking switch (4) is used to control different operation modes of the potential converter.

本創作所提出之低功率電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率消耗。 The low-power potential converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and can also effectively suppress the The pull path and the pull path compete with each other, thereby reducing power consumption.

Description

低功率電位轉換器 Low power potentiometer

本創作提出一種低功率電位轉換器，其係由一電位轉換電路(1)、一輸入電路(2)、一輸出控制開關(3)以及一電流阻隔開關(4)所組成，以求獲得精確電壓位準轉換，同時亦能有效降低功率消耗之電子電路。 This creation proposes a low-power potential converter, which consists of a potential conversion circuit (1), an input circuit (2), an output control switch (3), and a current blocking switch (4), in order to obtain accurate Electronic circuit for voltage level conversion, which can also effectively reduce power consumption.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the potential converter is responsible for converting low-voltage working signals into high-voltage working signals.

第1圖係顯示一先前技藝(prior art)之一閂鎖型電位轉換器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地 (GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the potential of the first signal (V (IN)) is also between the ground (GND) and the second high potential voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, because of the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potentiometer. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉 降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the process of the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) approaches to turn on (or off) and the second NMOS transistor (MN2) approaches to turn off (or on), the output terminal Pulling up and pulling the potential on (OUT) There is a phenomenon of contention, so the second signal (V (OUT)) is slower when it transitions to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are fully turned on or turned off completely. This will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND). ), This quiescent current will increase power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type potential converter is affected by the first high potential voltage (VDDH). Since the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is The first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch type potential converter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電位轉換器電路，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區， 並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電位轉換器的性能也不會有太大的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 2 shows one of the other prior art mirror-type potential converter circuits. The potential converter is connected and connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). To the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in a saturation region, And its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, the potential conversion The performance of the device will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於閂鎖型的電位轉換器在其輸出端上的電位有互相競爭的現象，本創作之主要目的係提出一種低功率電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率消耗。 In view of the fact that the potentials of the latch-type potential converters compete with each other at the output, the main purpose of this creation is to propose a low-power potential converter that can accurately and quickly convert the first signal into a The second signal can effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

本創作提出一種低功率電位轉換器，其係由一電位轉換電路(1)、一輸入電路(2)、一輸出控制開關(3)以及一電流阻隔開關(4)所組成，其中，該電位轉換電路(1)係用來做為電位轉換；該輸入電路(2)係用來提供差動輸入信號；該輸出控制開關(3)用以減少在待 機模式時之暫態電流消耗；而該電流阻隔開關(4)係用以控制該電位轉換器之不同操作模式。 This creation proposes a low-power potential converter, which is composed of a potential conversion circuit (1), an input circuit (2), an output control switch (3), and a current blocking switch (4). The conversion circuit (1) is used for potential conversion; the input circuit (2) is used to provide a differential input signal; the output control switch (3) is used to reduce And the current blocking switch (4) are used to control different operation modes of the potential converter.

由模擬結果證實，本創作所提出之低功率電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率消耗。 The simulation results confirm that the low-power potential converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. At the same time, it can effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power consumption.

1‧‧‧電位轉換電路 1‧‧‧potential conversion circuit

2‧‧‧輸入電路 2‧‧‧input circuit

3‧‧‧輸出控制開關 3‧‧‧Output control switch

4‧‧‧電流阻隔開關 4‧‧‧Current blocking switch

I1‧‧‧第一反相器 I1‧‧‧first inverter

I2‧‧‧第二反相器 I2‧‧‧Second Inverter

N1‧‧‧第一節點 N1‧‧‧First Node

N2‧‧‧第二節點 N2‧‧‧Second Node

N3‧‧‧第三節點 N3‧‧‧ third node

N4‧‧‧第四節點 N4‧‧‧ fourth node

N5‧‧‧第五節點 N5‧‧‧ fifth node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧The first PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧Second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧Third PMOS Transistor

EN‧‧‧致能控制端 EN‧‧‧Enable control terminal

ENB‧‧‧反相致能控制端 ENB‧‧‧ Inverted Enable Control Terminal

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧The first NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

MN3‧‧‧第三NMOS電晶體 MN3‧‧‧The third NMOS transistor

MN4‧‧‧第四NMOS電晶體 MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧第五NMOS電晶體 MN5‧‧‧Fifth NMOS transistor

GND‧‧‧地 GND‧‧‧ Ground

IN‧‧‧第一輸入端 IN‧‧‧first input

V(IN)‧‧‧第一信號 V (IN) ‧‧‧First Signal

OUT‧‧‧輸出端 OUT‧‧‧output

V(OUT)‧‧‧第二信號 V (OUT) ‧‧‧Second signal

INB‧‧‧第二輸入端 INB‧‧‧Second Input

V(INB)‧‧‧反相第一信號 V (INB) ‧‧‧Inverted first signal

VDDH‧‧‧第一高電源供應電壓 VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧第二高電源供應電壓 VDDL‧‧‧The second highest power supply voltage

第1圖 係顯示第一先前技藝中電位轉換器之電路圖；第2圖 係顯示第二先前技藝中電位轉換器之電路圖；第3圖 係顯示本創作較佳實施例之低功率電位轉換器之電路圖；第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; and Figure 3 shows the low power potential converter in the preferred embodiment of the present invention Circuit diagram; Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種低功率電位轉換器，如第3圖所示，其係由一電位轉換電路(1)、一輸入電路(2)、一輸出控制開關(3)以及一電流阻隔開關(4)所組成，其中，該電位轉換電路(1)係用來做為電位轉換之用；該輸入電路(2)係用來提供差動輸入信號；該輸出控制開關(3)係用以減少在待機模式時之暫態電流消耗；而該電流阻隔開關(4)係用以控制該電位轉換器之不同操作模式；該電位轉換電路(1)係耦接於該第一高電源供應電壓(VDDH)以及一輸入電路(2)，其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體 (MP2)、一第三NMOS電晶體(MN3)以及一第四NMOS電晶體(MN4)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三NMOS電晶體(MN3)的源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；該第四NMOS電晶體(MN4)的源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接；該輸入電路(2)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一反相器(I1)耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供該第一信號(V(IN))的反相信號；該輸出控制開關(3)係由一第三PMOS電晶體(MP3)所組成，其源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第三節點(N3)相連接；該電流阻隔開關(4)係由一第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連 接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接；該第一高電源供應電壓(VDDH)係用以提供該低功率電位轉換器所需之第一高電源電壓，該第二高電源供應電壓(VDDL)係用以提供該低功率電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes a low-power potential converter, as shown in FIG. 3, which is composed of a potential conversion circuit (1), an input circuit (2), an output control switch (3), and a current It consists of a blocking switch (4), wherein the potential conversion circuit (1) is used for potential conversion; the input circuit (2) is used to provide a differential input signal; the output control switch (3) is The current blocking switch (4) is used to control the different operation modes of the potential converter; the potential conversion circuit (1) is coupled to the first high power source. Supply voltage (VDDH) and an input circuit (2), which are composed of a first PMOS transistor (MP1) and a second PMOS transistor (MP2), a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH) ), Its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first high power supply Voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the third node Three-node (N3), whose gate is connected to the second input (INB), and its drain is connected to the first node (N1); the source of the fourth NMOS transistor (MN4) is connected to The gate of the fourth node (N4) is connected to the first input terminal (IN), and its drain is connected to the second node (N2); the input circuit (2) is formed by a first NMOS A transistor (MN1), a second NMOS transistor (MN2), and a first inverter (I1). The source of the first NMOS transistor (MN1) is connected to the fifth node (N5). ), Its gate is connected to the first input terminal (IN), and its drain is It is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)), and Provide the inverted signal of the first signal (V (IN)); the output control switch (3) is composed of a third PMOS transistor (MP3), and its source is connected to the first high power supply voltage (VDDH) ), Its gate is connected to the enable control terminal (EN), and its drain is connected to the third node (N3); the current blocking switch (4) is a fifth NMOS transistor (MN5) Composed of a source connected to ground (GND) and a gate connected It is connected to the inverting enable control terminal (ENB), and its drain is connected to the fifth node (N5); the first high power supply voltage (VDDH) is used to provide the low power potential converter. The first high power supply voltage required, the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the low power potential converter, and the level of the second high power supply voltage (VDDL) Is a level lower than the first high power supply voltage (VDDH), the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a correspondence between 0 volts and 1.8 volts Waveform, the first high power supply voltage (VDDH) is 1.8 volts, the second high power supply voltage (VDDL) is 1.2 volts, and the first signal (V (IN)) is between 0 volts and 1.2 volts Rectangular wave, the second signal (V (OUT)) is a corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，茲依低功率電位轉換器之工作模式說明圖3之工作原理如下： Please refer to Figure 3 again. The working mode of the low-power potentiometer is described below. The working principle of Figure 3 is as follows:

(I)主動模式(Active mode) (I) Active mode

在主動模式下，亦即，當該致能控制端(EN)是在邏輯低位準時，該第三PMOS電晶體(MP3)和第五NMOS電晶體(MN5)均呈導通(ON)狀態。 In the active mode, that is, when the enable control terminal (EN) is at a logic low level, the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are both in an ON state.

現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，低功率電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第四NMOS電晶體(MN4)的閘極，使得該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都截止(OFF)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第二NMOS電晶體(MN2)以及該第三NMOS電晶體(MN3)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都導通(ON)，此時，由於該第四NMOS 電晶體(MN4)截止，而該第二NMOS電晶體(MN2)導通，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，而該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，此時由於該第一PMOS電晶體(MP1)和該第三NMOS電晶體(MN3)都導通，而該第一NMOS電晶體(MN1)截止，因此，該第三節點(N3)的電位會被拉升至一邏輯高位準，該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)截止，由於該第四NMOS電晶體(MN4)和該第二PMOS電晶體(MP2)都截止，而該第二NMOS電晶體(MN2)導通，因此，該第四節點(N4)的電位將維持在邏輯低位準(0伏特)，輸出端(OUT)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過低功率電位轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Now consider the steady-state operation of the low-power potential converter when the first signal (V (IN)) is a logic low level (0 volts): the logic low level on the first input (IN) is simultaneously transmitted to the first The input terminal of the inverter (I1), the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) make the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both OFF, and the first inverter (I1) transmits a logic high level (VDDL) to the gates of the second NMOS transistor (MN2) and the third NMOS transistor (MN3), Both the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are turned on. At this time, since the fourth NMOS transistor The transistor (MN4) is turned off and the second NMOS transistor (MN2) is turned on, the potential of the fourth node (N4) is pulled down to a logic low level (0 volts), and the fourth node (N4) The logic low level is transmitted to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on. At this time, the first PMOS transistor (MP1) and the third NMOS transistor are turned on. The crystal (MN3) is turned on, and the first NMOS transistor (MN1) is turned off. Therefore, the potential of the third node (N3) will be pulled up to a logic high level, and the logic high of the third node (N3) The second PMOS transistor (MP2) is turned off. Since both the fourth NMOS transistor (MN4) and the second PMOS transistor (MP2) are turned off, and the second NMOS transistor (MN2) is turned on, therefore, The potential of the fourth node (N4) will be maintained at a logic low level (0 volts), and the potential of the output terminal (OUT) will be maintained at a steady state value of a logic low level (0 volts). In other words, when the first signal (V (IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by a low-power potential converter, and the output terminal (OUT) Output.

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，低功率電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第四NMOS電晶體(MN4)的閘極，使得該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都導通(ON)，而該第一反相器(I1)傳送邏輯低位準到該第二NMOS電晶體(MN2)以及該第三NMOS電晶體(MN3)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都截止(OFF)，此時，由於該第一NMOS電晶體(MN1)導通，而該第三NMOS電晶體(MN3)截止(OFF)，該第三節點(N3)的電位會被拉降至一邏輯低位準，該第三節點(N3)上的邏輯低位準傳送到該第二PMOS電晶體(MP2)的閘極，使得該第二 PMOS電晶體(MP2)導通，此時由於該第二PMOS電晶體(MP2)和該第四NMOS電晶體(MN4)都導通，而該第二NMOS電晶體(MN2)截止，因此，該第四節點(N4)的電位會被拉升至一邏輯高位準，該第四節點(N4)的邏輯高位準使得該第一PMOS電晶體(MP1)截止，此時由於該第一PMOS電晶體(MP1)和該第三NMOS電晶體(MN3)都截止，而該第一NMOS電晶體(MN1)導通，因此，該第三節點(N3)的電位將維持在一邏輯低位準，而該第四節點(N4)的電位亦將維持在一邏輯高位準，因此，輸出端(OUT)的電位會維持在一邏輯高位準的穩態值。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過低功率電位轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 Consider again the steady-state operation of the low-power potential converter when the first signal (V (IN)) is a logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is simultaneously transmitted to the The input terminal of the first inverter (I1), the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) make the first NMOS transistor (MN1) and the fourth NMOS transistor The transistor (MN4) is turned on, and the first inverter (I1) transmits a logic low level to the gates of the second NMOS transistor (MN2) and the third NMOS transistor (MN3), so that The second NMOS transistor (MN2) and the third NMOS transistor (MN3) are both turned OFF. At this time, because the first NMOS transistor (MN1) is turned on, the third NMOS transistor (MN3) is turned on. At OFF, the potential of the third node (N3) is pulled down to a logic low level, and the logic low level at the third node (N3) is transmitted to the gate of the second PMOS transistor (MP2) So that the second The PMOS transistor (MP2) is turned on. At this time, because the second PMOS transistor (MP2) and the fourth NMOS transistor (MN4) are both turned on, and the second NMOS transistor (MN2) is turned off, the fourth The potential of the node (N4) is pulled up to a logic high level. The logic high level of the fourth node (N4) causes the first PMOS transistor (MP1) to be turned off. At this time, the first PMOS transistor (MP1) is turned off. ) And the third NMOS transistor (MN3) are turned off, and the first NMOS transistor (MN1) is turned on. Therefore, the potential of the third node (N3) will be maintained at a logic low level, and the fourth node The potential of (N4) will also be maintained at a logic high level. Therefore, the potential of the output terminal (OUT) will be maintained at a steady state value of a logic high level. In other words, when the first signal (V (IN)) is at a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) by a low power potential converter, and the output terminal ( OUT) output.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電壓位準轉換的目的便實現。 In summary, when the first signal (V (IN)) is a logic low level (0 volts), the second signal (V (OUT)) is also a logic low level (0 volts); and the first signal When (V (IN)) is a logic high level (VDDL), the second signal (V (OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

(II)待機模式(Standby mode) (II) Standby mode

請再參考圖3。在待機狀態下，亦即，當該致能控制端(EN)是在邏輯高位準狀態時，該第三PMOS電晶體(MP3)和第五NMOS電晶體(MN5)均呈關閉(OFF)狀態，此時，該電位轉換器停止動作。因此，任何第一信號(V(IN))的輸入均不會影響到已被拴鎖住的第二信號(V(OUT))值。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is at a logic high level state, the third PMOS transistor (MP3) and the fifth NMOS transistor (MN5) are in an OFF state. At this time, the potential converter stops operating. Therefore, the input of any first signal (V (IN)) will not affect the value of the second signal (V (OUT)) that has been locked. Its working principle is not repeated here.

本創作所提出之低功率電位轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之低功率電位轉換 器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且可有效地減少輸出端(OUT)的上拉路徑與下拉路徑之間的互相競爭，進而降低功率損耗。 The simulation results of Spice transient analysis of the low-power potential converter proposed in this work are shown in Figure 4. From the simulation results, it can be confirmed that the low-power potential conversion proposed by this work The device can not only quickly and accurately convert the first signal into a second signal, but also effectively reduce the competition between the pull-up path and the pull-down path of the output terminal (OUT), thereby reducing power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (9)

一種低功率電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極以及一第三NMOS電晶體(MN3)的汲極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極以及一第四NMOS電晶體(MN4)的汲極連接在一起；一第三節點(N3)，用以將該第二PMOS電晶體(MP2)的閘極、該第三NMOS電晶體(MN3)的源極、一第三PMOS電晶體(MP3)的汲極以及一第一NMOS電晶體(MN1)的汲極連接在一起；一第四節點(N4)，用以將該第一PMOS電晶體(MP1)的閘極、該第四NMOS電晶體(MN4)的源極以及一第二NMOS電晶體(MN2)的汲極連接在一起；一第五節點(N5)，用以將該第一NMOS電晶體(MN1)、該第二NMOS電晶體(MN2)的源極以及一第五NMOS電晶體(MN5)的汲極連接在一起；一第一輸入端(IN)，耦接於該第一NMOS電晶體(MN1)的閘極以及一第一反相器(I1)的輸入端，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第二NMOS電晶體(MN2)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號(V(INB))；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個該第一信號(V(IN))的反相信號(V(INB))；一第二反相器(I2)，耦接於該致能控制端(EN)，用以提供一反相致能控制信號；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)以及該第三PMOS電晶體(MP3)的源極，用以提供該電位轉換器電路所需之第一高電源電壓；一第二高電源供應電壓(VDDL)，用以提供該電位轉換器電路所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一致能控制端(EN)，耦接於該第三PMOS電晶體(MP3)的閘極以及該第二反相器(I2)的輸入端，用以提供一致能控制信號；一反相致能控制端(ENB)，耦接於該第五NMOS電晶體(MN5)的閘極，用以提供一反相致能控制信號；一電位轉換電路(1)，耦接於該第一高電源供應電壓(VDDH)以及一輸入電路(2)，用來抑制該輸出端(OUT)電位的競爭現象；一輸入電路(2)，耦接於該第一輸入端(IN)，用來提供差動輸入信號；一輸出控制開關(3)，用以減少在待機模式時之暫態電流消耗；以及一電流阻隔開關(4)，用以控制該電位轉換器電路之不同操作模式。A low-power potential converter is used to convert a first signal (V (IN)) into a second signal (V (OUT)). It includes a first node (N1) for converting a first signal (N1) The drain of the PMOS transistor (MP1) and the drain of a third NMOS transistor (MN3) are connected together; a second node (N2) is used to connect the drain of a second PMOS transistor (MP2) and The drains of a fourth NMOS transistor (MN4) are connected together; a third node (N3) is used to gate the second PMOS transistor (MP2) and the third NMOS transistor (MN3) The source, the drain of a third PMOS transistor (MP3) and the drain of a first NMOS transistor (MN1) are connected together; a fourth node (N4) is used to connect the first PMOS transistor ( The gate of MP1), the source of the fourth NMOS transistor (MN4) and the drain of a second NMOS transistor (MN2) are connected together; a fifth node (N5) is used to connect the first NMOS The transistor (MN1), the source of the second NMOS transistor (MN2) and the drain of a fifth NMOS transistor (MN5) are connected together; a first input terminal (IN) is coupled to the first Gate of NMOS transistor (MN1) and input of a first inverter (I1) Terminal for providing a first signal (V (IN)); a second input terminal (INB) coupled to the gate of the second NMOS transistor (MN2) and the first inverter (I1) An output terminal for providing an inverted signal (V (INB)) of the first signal (V (IN)); an output terminal (OUT) coupled to the fourth node (N4) for outputting the A second signal (V (OUT)); a first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V (IN)), and providing a The inverted signal (V (INB)) of the first signal (V (IN)); a second inverter (I2) is coupled to the enable control terminal (EN) to provide an inverted enable A control signal; a first high power supply voltage (VDDH) is coupled to the source of the first PMOS transistor (MP1), the second PMOS transistor (MP2) and the third PMOS transistor (MP3), For providing a first high power supply voltage required by the potential converter circuit; a second high power supply voltage (VDDL) for providing a second high power supply voltage required by the potential converter circuit; the second high power supply The potential of the supply voltage (VDDL) is less than the potential of the first high power supply voltage (VDDH); The energy control terminal (EN) is coupled to the gate of the third PMOS transistor (MP3) and the input terminal of the second inverter (I2) to provide a uniform energy control signal; an inverter enable control Terminal (ENB), coupled to the gate of the fifth NMOS transistor (MN5), for providing an inverted enabling control signal; a potential conversion circuit (1), coupled to the first high power supply voltage (VDDH) and an input circuit (2) to suppress the competition of the potential of the output terminal (OUT); an input circuit (2) is coupled to the first input terminal (IN) to provide a differential input Signals; an output control switch (3) to reduce the transient current consumption in the standby mode; and a current blocking switch (4) to control different operation modes of the potential converter circuit. 如申請專利範圍第1項所述的低功率電位轉換器，其中該電位轉換電路(1)包括：一第一PMOS電晶體(MP1)，其源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第三NMOS電晶體(MN3)，其源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；以及一第四NMOS電晶體(MN4)，其源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接。The low-power potential converter according to item 1 of the patent application scope, wherein the potential conversion circuit (1) includes: a first PMOS transistor (MP1), the source of which is connected to a first high power supply voltage (VDDH) , Its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the first high power supply Voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a third NMOS transistor (MN3), its source is connected to the The third node (N3), whose gate is connected to the second input (INB), and whose drain is connected to the first node (N1); and a fourth NMOS transistor (MN4), whose source is The electrode is connected to the fourth node (N4), the gate is connected to the first input terminal (IN), and the drain is connected to the second node (N2). 如申請專利範圍第2項所述的低功率電位轉換器，其中該輸入電路(2)包括：一第一NMOS電晶體(MN1)，其源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第二NMOS電晶體(MN2)，其源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。The low-power potential converter according to item 2 of the scope of patent application, wherein the input circuit (2) includes: a first NMOS transistor (MN1), the source of which is connected to the fifth node (N5), and the gate Is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a second NMOS transistor (MN2), and its source is connected to the fifth node (N5) , Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)) and provide a signal that is inverse to the first signal (V (IN)). 如申請專利範圍第3項所述的低功率電位轉換器，其中該輸出控制開關(3)係由一第三PMOS電晶體(MP3)所組成，其源極連接至第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第三節點(N3)相連接。The low-power potential converter according to item 3 of the scope of patent application, wherein the output control switch (3) is composed of a third PMOS transistor (MP3), and its source is connected to the first high power supply voltage ( VDDH), its gate is connected to the enable control terminal (EN), and its drain is connected to the third node (N3). 如申請專利範圍第4項所述的低功率電位轉換器，其中該電流阻隔開關(4)係由一第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接。The low-power potential converter according to item 4 of the scope of patent application, wherein the current blocking switch (4) is composed of a fifth NMOS transistor (MN5), the source of which is connected to the ground (GND), and the gate The electrode is connected to the inverting enable control terminal (ENB), and its drain is connected to the fifth node (N5). 如申請專利範圍第1項所述的低功率電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。The low-power potential converter according to item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). 如申請專利範圍第6項所述的低功率電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。The low-power potentiometer according to item 6 of the patent application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). 如申請專利範圍第7項所述的低功率電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。The low-power potential converter according to item 7 of the scope of the patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL). 如申請專利範圍第8項所述的低功率電位轉換器，其中該第二反相器(I2)的電壓源為該第一高電源供應電壓(VDDH)。The low-power potential converter according to item 8 of the scope of patent application, wherein the voltage source of the second inverter (I2) is the first high power supply voltage (VDDH).
TW108204329U 2019-04-10 2019-04-10 Low power level shifter circuit TWM586017U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW108204329U TWM586017U (en) 2019-04-10 2019-04-10 Low power level shifter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW108204329U TWM586017U (en) 2019-04-10 2019-04-10 Low power level shifter circuit

Publications (1)

Publication Number Publication Date
TWM586017U true TWM586017U (en) 2019-11-01

Family

ID=69189524

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108204329U TWM586017U (en) 2019-04-10 2019-04-10 Low power level shifter circuit

Country Status (1)

Country Link
TW (1) TWM586017U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817389B (en) * 2022-03-15 2023-10-01 智原科技股份有限公司 Level shifter and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI817389B (en) * 2022-03-15 2023-10-01 智原科技股份有限公司 Level shifter and electronic device

Similar Documents

Publication Publication Date Title
TWM616390U (en) Low power voltage level shifter
TWM586017U (en) Low power level shifter circuit
TWM598009U (en) Voltage level shifter having output control circuit
TWM576365U (en) Low power voltage level converter
TWM565921U (en) Voltage level shifter
TWM576366U (en) Level conversion circuit with auxiliary circuit
TWM531694U (en) Voltage level converter
TWM625120U (en) Voltage level converter with leakage current reduction
TWM649184U (en) Low voltage to high voltage signal level translator with improved performance
TWM604082U (en) Low power voltage level converter
TWM587403U (en) Voltage level converter with low-power consumption
TWM628475U (en) Low power and high performance voltage level converting circuit
TWM626414U (en) Voltage level converter with stack transistors
TWM598007U (en) High performance voltage level converter
TWM626417U (en) High-speed low-power level shifter circuit
TWM647689U (en) High speed voltage level converter with low power consumption
TWM601491U (en) Voltage level shifter with low power consumption
TWM639384U (en) High-speed low-power level shifter circuit for integrated circuits having multiple power supplies
TWM625119U (en) Voltage level converting circuit with reduced power consumption
TWM645482U (en) High speed voltage level converter having low power consumption
TWM628446U (en) Contention-free level converting circuit for data receiving circuit
TWM618862U (en) Voltage level shifter with low power consumption
TWM626307U (en) Contention-reduced level converting circuit
TWM599059U (en) Voltage level shifter having output buffer circuit
TWM643324U (en) Low power level converter with inhibit current circuit

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees