TWM618862U

TWM618862U - Voltage level shifter with low power consumption

Info

Publication number: TWM618862U
Application number: TW110203814U
Authority: TW
Inventors: 余建政; 邱崑霖; 賴永瑄
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2021-11-01

Abstract

本創作提出一種低功耗電位轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一輸出控制電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號，並能抑制該輸出端(OUT)電位的競爭現象；而該輸出控制電路(3)係用以控制該低功耗電位轉換器的輸出信號。 This creation proposes a low power consumption potential converter, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) is used for Provides a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1), and can suppress the competition phenomenon of the output terminal (OUT) potential; and the output control circuit ( 3) It is used to control the output signal of the low power consumption potential converter.

本創作所提出之低功耗電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 The low-power level converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and can effectively suppress The pull-up path and the pull-down path compete with each other, thereby reducing power loss.

Description

低功耗電位轉換器 Low-power potential converter

本創作提出一種低功耗電位轉換器，尤指一由一輸入電路(1)、一栓鎖電路(2)以及一輸出控制電路(3)所組成，以求獲得精確電壓位準轉換，同時亦能有效降低功率損耗之電子電路。 This creation proposes a low-power level converter, especially one composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), in order to obtain accurate voltage level conversion, and at the same time It can also effectively reduce the power loss of electronic circuits.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage working signal into a high-voltage working signal.

第1圖係顯示另一先前技藝(prior art)之一鏡像型電位轉換器電路，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電位轉換器的性能也不會有太大的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 1 shows another prior art mirror-type potential converter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the The saturation region and its gate voltage make the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too Big change. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

第2圖係顯示一先前技藝之一閂鎖型電位轉換器電路，其係使用一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS 電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 2 shows a latch-type potential converter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , A second NMOS transistor (MN2) and an inverter (INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type There is no static current in the potential converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the second PMOS The gate potential of the transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will not be a current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is approaching to turn on (or off) and the second NMOS transistor (MN2) is approaching to turn off (or on), the output terminal The rise and fall of the potential on the (OUT) are contention, so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase the power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。 Furthermore, the performance of the latch type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) It is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch-type level converter operate normally is limited. In the second PMOS transistor (MP2) tends to turn on (or off) and in When the second NMOS transistor (MN2) is close to turning off (or on), there is a competition (contention) for the rise and fall of the potential on the output terminal (OUT), so the second signal (V (OUT)) The speed is slow when changing to a low potential.

有鑑於此，本創作之主要目的係提出一種低功耗電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 In view of this, the main purpose of this creation is to propose a low-power level converter, which can not only accurately and quickly convert the first signal into a second signal, but also can effectively reduce the interaction between the pull-up path and the pull-down path. Competition, thereby reducing power loss.

本創作提出一種低功耗電位轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一輸出控制電路(3)所組成，其中，該輸入電路(1)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號，並能抑制該輸出端(OUT)電位的競爭現象；而該輸出控制電路(3)係用以控制該低功耗電位轉換器的輸出信號。 This creation proposes a low power consumption potential converter, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3), wherein the input circuit (1) is used for Provide the first signal (V(IN)) and the inverted signal of the first signal (V(IN)); the latch circuit (2) is used to save the differential input signal from the input circuit (1) , And can suppress the competition phenomenon of the output terminal (OUT) potential; and the output control circuit (3) is used to control the output signal of the low power consumption potential converter.

由模擬結果證實，本創作所提出之低功耗電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results confirm that the low-power potential converter proposed by this creation not only can accurately and quickly convert the first signal to a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. , At the same time can effectively reduce power loss.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latching circuit

3:輸出控制電路 3: Output control circuit

I1:第一反相器 I1: The first inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: third node

N4:第四節點 N4: Fourth node

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五NMOS電晶體 MP5: Fifth NMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): second signal

IN:第一輸入端 IN: the first input

V(IN):第一信號 V(IN): the first signal

INB:第二輸入端 INB: second input

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: the second highest power supply voltage

GND:地 GND: ground

第1圖係顯示第一先前技藝中電位轉換器之電路圖；第2圖係顯示第二先前技藝中電位轉換器之電路圖；第3圖係顯示本創作較佳實施例之低功耗電位轉換器之電路圖；第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; Figure 3 shows the low-power potential converter in the preferred embodiment of this creation The circuit diagram; Figure 4 shows the transient analysis timing of the first signal and the second signal of the preferred embodiment of this creation picture;

根據上述之目的，本創作提出一種低功耗電位轉換器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)以及一輸出控制電路(3)所組成，其中，該輸入電路(1)係用來提供一第一信號(V(IN))以及該第一信號(V(IN))的反相信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號，並抑制該輸出端(OUT)電位的競爭現象；而該輸出控制電路(3)係用以控制該低功耗電位轉換器的輸出信號；該輸入電路(1)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第五PMOS電晶體(MP5)以及一第六PMOS電晶體(MP6)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第五PMOS電晶體(MP5) 的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第六PMOS電晶體(MP6)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該輸出控制電路(3)係由一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該第一高電源供應電壓(VDDH)係用以提供該低功耗電位轉換器所需之第一高電源電壓，該第二高電源供應電壓(VDDL)係用以提供該低功耗電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above-mentioned purpose, this creation proposes a low power consumption potential converter, as shown in Figure 3, which is composed of an input circuit (1), a latch circuit (2) and an output control circuit (3) , Wherein the input circuit (1) is used to provide a first signal (V(IN)) and the inverted signal of the first signal (V(IN)); the latch circuit (2) is used to save The differential input signal from the input circuit (1) and suppress the competition phenomenon of the output terminal (OUT) potential; and the output control circuit (3) is used to control the output signal of the low power consumption potential converter; the The input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the first NMOS transistor (MN1) The source is connected to the ground (GND), the gate is connected to the first input (IN), and the drain is connected to the third node (N3); the second NMOS transistor (MN2) The source is connected to the ground (GND), its gate is connected to the second input (INB), and its drain is connected to the fourth node (N4); the first inverter (I1) is coupled Connected to the first input terminal (IN) to receive the first signal (V(IN)) and provide a signal that is inverse to the first signal (V(IN)); the latch circuit (2 ) Is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a fifth PMOS transistor (MP5) and a sixth PMOS transistor (MP6), where the first The source of the PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1) ; The source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node ( N2) phase connection; the fifth PMOS transistor (MP5) The source of is connected to the first node (N1), its gate is connected to the first input (IN), and its drain is connected to the third node (N3); the sixth PMOS transistor ( The source of MP6) is connected to the second node (N2), its gate is connected to the second input (INB), and its drain is connected to the fourth node (N4); the output control circuit ( 3) It is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), wherein the source of the third PMOS transistor (MP3) is connected to the first high power supply voltage ( VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first High power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the first high power supply voltage (VDDH) is used In order to provide the first high power supply voltage required by the low power consumption level converter, the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the low power consumption level converter. The level of the second high power supply voltage (VDDL) is smaller than the level of the first high power supply voltage (VDDH), the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is Corresponding waveforms between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN )) is a rectangular wave between 0 volt and 1.2 volt, and the second signal (V(OUT)) is a corresponding waveform between 0 volt and 1.8 volt.

請再參閱第3圖，現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，低功耗電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第三PMOS電晶體(MP3)、該第五PMOS電晶體(MP5)以及該第一NMOS電晶體(MN1)的閘極，使得該第三PMOS電晶體(MP3)和該第五PMOS電晶體(MP5)都導通(ON)，而該第一NMOS電晶體(MN1)截止(OFF)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第四PMOS電晶體(MP4)、該第六PMOS電晶體(MP6)以及該第二NMOS電晶體(MN2)的閘極，使得該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都截止(OFF)，而該第二NMOS電晶體(MN2)導通(ON)，此時，由於該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都截止(OFF)，該第二NMOS電晶體(MN2)導通，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，而該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，此時由於該第一PMOS電晶體(MP1)和該第五PMOS電晶體(MP5)都導通，而該第一NMOS電晶體(MN1)截止，因此，該第三節點(N3)的電位會被拉升至一邏輯高位準，該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)截止，由於該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)都截止，而該第二NMOS電晶體(MN2)導通，因此，該第四節點(N4)的電位將維持在邏輯低位準(0伏特)，輸出端(OUT)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過電位轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to Figure 3 again. Now consider the steady-state operation of the low-power level converter when the first signal (V(IN)) is at a logic low level (0 volts): the logic on the first input (IN) The low level is simultaneously transmitted to the input terminal of the first inverter (I1), the third PMOS transistor (MP3), the fifth PMOS transistor (MP5), and the gate of the first NMOS transistor (MN1) , Making this The third PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are both turned on (ON), and the first NMOS transistor (MN1) is turned off (OFF), and the first inverter (I1) transmits The logic high level (VDDL) to the gates of the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6), and the second NMOS transistor (MN2), so that the fourth PMOS transistor (MP4) And the sixth PMOS transistor (MP6) are both turned off (OFF), and the second NMOS transistor (MN2) is turned on (ON), at this time, due to the fourth PMOS transistor (MP4) and the sixth PMOS transistor The transistors (MP6) are all turned off (OFF), the second NMOS transistor (MN2) is turned on, the potential of the fourth node (N4) will be pulled down to a logic low level (0V), and the fourth node ( The logic low level on N4) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on. At this time, due to the first PMOS transistor (MP1) and the fifth PMOS transistor (MP1). The PMOS transistors (MP5) are all turned on, and the first NMOS transistor (MN1) is turned off. Therefore, the potential of the third node (N3) will be pulled up to a logic high level. The logic high level makes the second PMOS transistor (MP2) cut off, since both the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) are cut off, and the second NMOS transistor (MN2) is turned on, Therefore, the potential of the fourth node (N4) will be maintained at a logic low level (0 volt), and the potential of the output terminal (OUT) will be maintained at a steady-state value of a logic low level (0 volt). In a nutshell, when the first signal (V(IN)) is at a logic low level (0 volt), it is converted into a second signal with a logic low level (0 volt) by the potential converter, and is output by the output terminal (OUT).

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，低功耗電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第三PMOS電晶體(MP3)、該第五PMOS電晶體(MP5)以及該第一NMOS電晶體(MN1)的閘極，使得該第三PMOS電晶體(MP3)和該第五PMOS電晶體(MP5)都截止(OFF)，而該第一NMOS電晶體(MN1)導通(ON)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第四PMOS電晶體(MP4)、該第六PMOS電晶體(MP6)以及該第二NMOS電晶體(MN2)的閘極，使得該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都導通(ON)，而該第二NMOS電晶體(MN2)截止(OFF)，由於該第四PMOS電晶體(MP4)和該第六PMOS電晶體(MP6)都截止(OFF)，該第二NMOS電晶體(MN2)導通，該第四節點(N4)的電位會被拉升至一邏輯高位準，而該第四節點(N4)上的邏輯高位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)截止，此時由於該第一PMOS電晶體(MP1)和該第五PMOS電晶體(MP5)都截止，而該第一NMOS電晶體(MN1)導通，因此，該第三節點(N3)的電位會被拉降至一邏輯低位準，該第三節點(N3)的邏輯低位準使得該第二PMOS電晶體(MP2)導通，此時由於該第二PMOS電晶體(MP2)和該第六PMOS電晶體(MP6)都導通，而該第二NMOS電晶體(MN2)截止，因此，該第四節點(N4)的電位將被維持在邏輯高位準，輸出端(OUT)的電位會維持在一邏輯高位準的穩態值。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過低功耗電位轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 Then consider the steady-state operation of the low-power level converter when the first signal (V(IN)) is at the logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is simultaneously transmitted to The input terminal of the first inverter (I1), the third PMOS transistor (MP3), the fifth PMOS transistor (MP5), and the gate of the first NMOS transistor (MN1) make the third Both the PMOS transistor (MP3) and the fifth PMOS transistor (MP5) are turned off (OFF), and the first NMOS transistor The body (MN1) is turned on (ON), and the first inverter (I1) transmits a logic high level (VDDL) to the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6) and the second The gate of the NMOS transistor (MN2) makes the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) both conductive (ON), and the second NMOS transistor (MN2) is turned off (OFF) Since the fourth PMOS transistor (MP4) and the sixth PMOS transistor (MP6) are both turned off (OFF), the second NMOS transistor (MN2) is turned on, and the potential of the fourth node (N4) will be pulled Rise to a logic high level, and the logic high level on the fourth node (N4) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned off. The first PMOS transistor (MP1) and the fifth PMOS transistor (MP5) are both turned off, and the first NMOS transistor (MN1) is turned on, therefore, the potential of the third node (N3) will be pulled down to A logic low level. The logic low level of the third node (N3) makes the second PMOS transistor (MP2) turn on. At this time, due to the second PMOS transistor (MP2) and the sixth PMOS transistor (MP6) Both are turned on, and the second NMOS transistor (MN2) is turned off. Therefore, the potential of the fourth node (N4) will be maintained at a logic high level, and the potential of the output terminal (OUT) will be maintained at a logic high level. State value. In a nutshell, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) by the low-power level converter. (OUT) output.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電位轉換的目的便實現。 In summary, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal When (V(IN)) is the logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of potential conversion is achieved.

本創作所提出之低功耗電位轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之低功耗電位轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且可有效地減少輸出端(OUT)的上拉路徑與下拉路徑之間的互相競爭，進而降低功率損耗。 The simulation results of Spice transient analysis of the low-power potential converter proposed in this creation are shown in Figure 4. The simulation results can confirm that the low-power potential conversion proposed in this creation Not only can it quickly and accurately convert the first signal into a second signal, but it can also effectively reduce the competition between the pull-up path and the pull-down path of the output terminal (OUT), thereby reducing power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although this creation specifically discloses and describes the selected best embodiment, those skilled in the art can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latching circuit

3:輸出控制電路 3: Output control circuit

I1:第一反相器 I1: The first inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: third node

N4:第四節點 N4: Fourth node

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: second PMOS transistor

MP3:第三PMOS電晶體 MP3: The third PMOS transistor

MP4:第四PMOS電晶體 MP4: The fourth PMOS transistor

MP5:第五NMOS電晶體 MP5: Fifth NMOS transistor

MP6:第六PMOS電晶體 MP6: The sixth PMOS transistor

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): second signal

IN:第一輸入端 IN: the first input

V(IN):第一信號 V(IN): the first signal

INB:第二輸入端 INB: second input

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: the second highest power supply voltage

GND:地 GND: ground

Claims

一種低功耗電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極以及一第五PMOS電晶體(MP5)的源極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極以及一第六PMOS電晶體(MP6)的源極連接在一起；一第三節點(N3)，用以將一第一NMOS電晶體(MN1)的汲極、該第五PMOS電晶體(MP5)的汲極以及該第二PMOS電晶體(MP2)的閘極連接在一起；一第四節點(N4)，用以將一第二NMOS電晶體(MN2)的汲極、該第六PMOS電晶體(MP6)的汲極以及該第一PMOS電晶體(MP1)的閘極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)、該第五PMOS電晶體(MP5)以及該第一NMOS電晶體(MN1)的閘極，用以提供該第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)、該第六PMOS電晶體(MP6)以及該第二NMOS電晶體(MN2)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)、該第三PMOS電晶體(MP3)以及該第四PMOS電晶體(MP4)的源極，用以提供該低功耗電位轉換器所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，用以提供該低功耗電位轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一輸入電路(1)，耦接於該第一輸入端(IN)，用以提供差動輸入信號；一栓鎖電路(2)，用以保存來自該輸入電路(1)的差動輸入信號；以及一輸出控制電路(3)，用以控制該低功耗電位轉換器的輸出信號之電位。 A low-power level converter for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes: a first node (N1) for converting a first signal (N1) The drain of a PMOS transistor (MP1), the drain of a third PMOS transistor (MP3), and the source of a fifth PMOS transistor (MP5) are connected together; a second node (N2) is used for Connect the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the source of a sixth PMOS transistor (MP6) together; a third node (N3) , For connecting the drain of a first NMOS transistor (MN1), the drain of the fifth PMOS transistor (MP5) and the gate of the second PMOS transistor (MP2) together; a fourth node (N4) for connecting the drain of a second NMOS transistor (MN2), the drain of the sixth PMOS transistor (MP6) and the gate of the first PMOS transistor (MP1) together; The first input terminal (IN) is coupled to the gate of the third PMOS transistor (MP3), the fifth PMOS transistor (MP5) and the first NMOS transistor (MN1) to provide the first Signal (V(IN)); a second input terminal (INB), coupled to the fourth PMOS transistor (MP4), the sixth PMOS transistor (MP6), and the second NMOS transistor (MN2) The gate is used to provide the inverted signal of the first signal (V(IN)); An output terminal (OUT), coupled to the fourth node (N4), for outputting the second signal (V(OUT)); a first high power supply voltage (VDDH), coupled to the first PMOS The source of the transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) are used to provide the low power consumption potential converter The first high potential voltage required; a second high power supply voltage (VDDL), used to provide the second high potential voltage required by the low-power level converter, the potential of the second high power supply voltage (VDDL) Is a potential less than the first high power supply voltage (VDDH); an input circuit (1) coupled to the first input terminal (IN) for providing a differential input signal; a latch circuit (2), It is used to save the differential input signal from the input circuit (1); and an output control circuit (3) is used to control the potential of the output signal of the low power consumption potential converter.

如申請專利範圍第1項所述的低功耗電位轉換器，其中該輸入電路(1)包括：一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接收該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The low-power level converter described in item 1 of the scope of patent application, wherein the input circuit (1) includes: a first NMOS transistor (MN1), the source of which is connected to the ground (GND), and the gate is connected To the first input terminal (IN), and its drain is connected to the third node (N3); a second NMOS transistor (MN2), its source is connected to ground (GND), and its gate is connected To the second input terminal (INB), and its drain is connected to the fourth node (N4); and A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal.

如申請專利範圍第2項所述的低功耗電位轉換器，其中該栓鎖電路(2)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第五PMOS電晶體(MP5)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；以及一第六PMOS電晶體(MP6)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接。 As described in the second item of the scope of patent application, the low power consumption potential converter, wherein the latch circuit (2) includes: a first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage ( VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), the source of which is connected to the first node (N1) High power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a fifth PMOS transistor (MP5), its source Connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); and a sixth PMOS transistor (MP6) , Its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4).

如申請專利範圍第3項所述的低功耗電位轉換器，其中該輸出控制電路(3)包括：一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 As described in the third item of the scope of patent application, the output control circuit (3) includes: a third PMOS transistor (MP3) whose source is connected to the first high power supply voltage ( VDDH), the gate of which is connected to the first input terminal (IN), and the drain of which is connected to the first node (N1); and A fourth PMOS transistor (MP4) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2) Connected.

如申請專利範圍第1項所述的低功耗電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 In the low-power level converter described in the first item of the scope of patent application, the amplitude of the first signal (V(IN)) is between 0 volt and the second high power supply voltage (VDDL).

如申請專利範圍第5項所述的低功耗電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 In the low-power level converter according to the fifth item of the scope of patent application, the amplitude of the second signal (V(OUT)) is between 0 volt and the first high power supply voltage (VDDH).

如申請專利範圍第2項所述的低功耗電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 In the low-power level converter described in the second item of the scope of patent application, the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).