TWM604082U - Low power voltage level converter - Google Patents
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Abstract
本創作提出一種低功率電壓位準轉換器,其係由一輸入電路(1)、一栓鎖電路(2)、一電流阻隔開關(3)以及一電流阻隔開關(4)所組成,其中,該輸入電路(1)係用來提供差動輸入信號;該栓鎖電路(2)係用以保存並且抑制輸出電位的競爭現象;該電流阻隔開關(3)係用以在該電流阻隔開關(3)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置;而該電流阻隔開關(4)係用以在該電流阻隔開關(4)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置。 This creation proposes a low-power voltage level converter, which is composed of an input circuit (1), a latch circuit (2), a current blocking switch (3) and a current blocking switch (4), among which, The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the current blocking switch (3) is used to switch the current blocking switch ( 3) When it is in the off state and the output voltage level is higher than the input voltage level, the current flow is prevented to prevent damage to the device; and the current blocking switch (4) is used when the current blocking switch (4) is in the off state And when the output voltage level is higher than the input voltage level, the current flow is prevented to prevent damage to the device.
本創作所提出之低功率電壓位準轉換器,不但能精確地將第一信號轉換為一第二信號,並且兼具電路結構簡單以及有利於裝置之小型化等多重功效,同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭,進而降低功率損耗。 The low-power voltage-level converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and it can also effectively The competition between the pull-up path and the pull-down path is suppressed, thereby reducing power loss.
Description
本創作提出一種低功率電壓位準轉換器,尤指一由一輸入電路(1)、一栓鎖電路(2)、一電流阻隔開關(3)以及一電流阻隔開關(4)所組成,以求獲得精確電壓位準轉換同時亦能有效降低功率損耗之電子電路。 This creation proposes a low-power voltage level converter, especially one consisting of an input circuit (1), a latch circuit (2), a current blocking switch (3), and a current blocking switch (4). Seek to obtain accurate voltage level conversion and at the same time can effectively reduce the power loss of the electronic circuit.
電壓位準轉換器係一種用來溝通不同的積體電路(Integrated Circuit,簡稱IC)之間的信號傳遞之電子電路。在許多應用中,當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時,電壓位準轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level converter is an electronic circuit used to communicate signals between different integrated circuits (ICs). In many applications, when the application system needs to transmit the signal from the core logic with a lower voltage level to the peripheral device with a higher voltage level, the voltage level converter is responsible for converting the low-voltage working signal into a high-voltage working signal .
第1圖係顯示另一先前技藝(prior art)之一鏡像型電壓位準轉換器電路,該電壓位準轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極,使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路,第一PMOS電晶體(MP1)是處於飽和區,並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流,而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電壓位準轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定,因 此,即使輸出的第一高電源供應電壓(VDDH)改變,電壓位準轉換器的性能也不會有太大的改變。因此,鏡像型的電壓位準轉換器可以適用在各種輸出電壓電路。 Figure 1 shows another prior art mirror-type voltage level converter circuit. The voltage level converter combines a first PMOS transistor (MP1) and a second PMOS transistor (MP2) The gates of the first PMOS transistor (MP1) are connected together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor ( MP1) is in the saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) Are also equal. Since the performance of the mirrored voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), Therefore, even if the output first high power supply voltage (VDDH) changes, the performance of the voltage level converter will not change much. Therefore, the mirrored voltage level converter can be applied to various output voltage circuits.
然而,當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時,第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降,使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此,在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).
第2圖係顯示一先前技藝之一閂鎖型電壓位準轉換器電路,其係使用一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電壓位準轉換器電路,其中,該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND),而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此,在同一時間內,第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外,由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式,使得當電壓位準轉換器的輸出(OUT)處於一個穩定的狀態時,閂鎖型的電壓位準轉換器中沒有靜態電流(static current)產生。尤其,當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時,第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通,以致拉升(pull up) 第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2);再者,當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時,第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通,以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此,在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 2 shows a latch-type voltage-level converter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor ( MN1), a second NMOS transistor (MN2) and an inverter (INV) form a voltage level converter circuit, wherein the bias voltage of the inverter (INV) is the second high power supply voltage ( VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the lock-type voltage level converter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and Make the first PMOS transistor (MP1) turn on, so as to pull up (pull up) The gate potential of the second PMOS transistor (MP2) turns off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the second The gate potential of the PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1) . Therefore, there will not be a current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).
然而,上述習知電壓位準轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中,對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象,因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外,考慮當第一信號(V(IN))由0伏特改變至1.8伏特時,第一NMOS電晶體(MN1)導通,而第二PMOS電晶體(MP2)的閘極變為低電位,使得第二PMOS電晶體(MP2)導通。所以,輸出為一第一高電源供應電壓(VDDH)。但是,由於0伏特無法瞬間轉換至1.8伏特,因此,在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉,如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current),此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional voltage level converter, when the second PMOS transistor (MP2) is approaching to turn on (or off) and the second NMOS transistor (MN2) is approaching to turn off (or on), for The pull-up and pull-down of the potential on the output terminal (OUT) have a contention phenomenon, so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase power loss.
再者,閂鎖型的電壓位準轉換器的性能是受到第一高電源供應電壓(VDDH)的影響,由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH),而第一NMOS電晶體 (MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此,限制了可以使閂鎖型電壓位準轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中,對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象,因此第二信號(V(OUT))在轉變成低電位時速度較慢。 Furthermore, the performance of the latch-type voltage level converter is affected by the first high power supply voltage (VDDH), due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The pole voltage is the first high power supply voltage (VDDH), and the first NMOS transistor The gate-source voltage of (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited. When the second PMOS transistor (MP2) is approaching to turn on (or off) and the second NMOS transistor (MN2) is approaching to turn off (or on), the potential on the output terminal (OUT) is pulled There is a contention phenomenon between rising and pulling down, so the second signal (V(OUT)) is slower when it changes to a low potential.
有鑑於此,本創作之主要目的係提出一種低功率電壓位準轉換器,其不但能精確且快速地將第一信號轉換為一第二信號,並且可有效地減少上拉路徑與下拉路徑的互相競爭,進而降低功率損耗。 In view of this, the main purpose of this creation is to propose a low-power voltage-level converter, which can not only accurately and quickly convert the first signal to a second signal, but also can effectively reduce the pull-up path and the pull-down path. Compete with each other to reduce power loss.
本創作提出一種低功率電壓位準轉換器,其係由一輸入電路(1)、一栓鎖電路(2)、一電流阻隔開關(3)以及一電流阻隔開關(4)所組成,其中,該輸入電路(1)係用來提供差動輸入信號;該栓鎖電路(2)係用以保存並且抑制輸出電位的競爭現象;該電流阻隔開關(3)係用以在該電流阻隔開關(3)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置;而該電流阻隔開關(4)係用以在該電流阻隔開關(4)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置。 This creation proposes a low-power voltage level converter, which is composed of an input circuit (1), a latch circuit (2), a current blocking switch (3) and a current blocking switch (4), among which, The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the current blocking switch (3) is used to switch the current blocking switch ( 3) When it is in the off state and the output voltage level is higher than the input voltage level, the current flow is prevented to prevent damage to the device; and the current blocking switch (4) is used when the current blocking switch (4) is in the off state And when the output voltage level is higher than the input voltage level, the current flow is prevented to prevent damage to the device.
由模擬結果證實,本創作所提出之低功率電壓位準轉換器,不但能精確且快速地將第一信號轉換為一第二信號,並且兼具電路結構簡單以及有利於裝置之小型化等多重功效,同時亦能有效地減少功率損耗。 The simulation results confirm that the low-power voltage-level converter proposed in this creation not only can accurately and quickly convert the first signal to a second signal, but also has the advantages of simple circuit structure and miniaturization of the device. Efficacy, while also effectively reducing power loss.
1:輸入電路 1: Input circuit
2:栓鎖電路 2: Latch circuit
3:電流阻隔開關 3: Current blocking switch
4:電流阻隔開關 4: Current blocking switch
I1:第一反相器 I1: First inverter
N1:第一節點 N1: the first node
N2:第二節點 N2: second node
N3:第三節點 N3: third node
N4:第四節點 N4: Fourth node
N5:第五節點 N5: fifth node
N6:第六節點 N6: sixth node
MP1:第一PMOS電晶體 MP1: The first PMOS transistor
MP2:第二PMOS電晶體 MP2: second PMOS transistor
MP3:第三PMOS電晶體 MP3: third PMOS transistor
MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor
MP5:第五PMOS電晶體 MP5: The fifth PMOS transistor
MN1:第一NMOS電晶體 MN1: The first NMOS transistor
MN2:第二NMOS電晶體 MN2: Second NMOS transistor
MN3:第三NMOS電晶體 MN3: The third NMOS transistor
GND:地 GND: ground
OUT:輸出端 OUT: output terminal
V(OUT):第二信號 V(OUT): second signal
IN:第一輸入端 IN: the first input
V(IN):第一信號 V(IN): the first signal
INB:第二輸入端 INB: second input
EN:致能控制端 EN: Enable control terminal
ENB:反相致能控制端 ENB: Reverse enable control terminal
VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage
VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage
第1圖 係顯示第一先前技藝中電壓位準轉換器之電路圖;第2圖 係顯示第二先前技藝中電壓位準轉換器之電路圖;第3圖 係顯示本創作較佳實施例之低功率電壓位準轉換器之電路圖;第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖; Figure 1 shows the circuit diagram of the voltage level converter in the first prior art; Figure 2 shows the circuit diagram of the voltage level converter in the second prior art; Figure 3 shows the low power of the preferred embodiment of this creation The circuit diagram of the voltage level converter; Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of this creation;
根據上述之目的,本創作提出一種低功率電壓位準轉換器,如第3圖所示,其係由一輸入電路(1)、一栓鎖電路(2)、一電流阻隔開關(3)以及一電流阻隔開關(4)所組成,其中,該輸入電路(1)係用來提供差動輸入信號;該栓鎖電路(2)係用以保存並且抑制輸出電位的競爭現象;該電流阻隔開關(3)係用以在該電流阻隔開關(3)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置;而該電流阻隔開關(4)係用以在該電流阻隔開關(4)處於關閉狀態,並且輸出電壓位準高於輸入電壓位準時,阻止電流的流動,以防止損壞裝置;該輸入電路(1)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成,其中,該第一NMOS電晶體(MN1)的源極連接至該第五節點(N5),其閘極連接至該第一輸入端(IN),而其汲極則與該第三節點(N3)相連接;該第二NMOS電晶體(MN2)的源極連接至該第五節點(N5),其閘極連接至該第二輸入端(INB),而其汲極則與該第四節點(N4)相連接;該第一反相 器(I1)係耦接於該第一輸入端(IN),用以接受該第一信號(V(IN)),並提供一個與該第一信號(V(IN))反相的信號;該栓鎖電路(2)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第四PMOS電晶體(MP4)以及一第五PMOS電晶體(MP5)所組成,其中,該第一PMOS電晶體(MP1)的源極連接至該第六節點(N6),其閘極連接至該第四節點(N4),而其汲極則與該第一節點(N1)相連接;該第二PMOS電晶體(MP2)的源極連接至該第六節點(N6),其閘極連接至該第三節點(N3),而其汲極則與該第二節點(N2)相連接;該第四PMOS電晶體(MP4)的源極連接至該第一節點(N1),其閘極連接至該第二輸入端(INB),而其汲極則與該第三節點(N3)相連接;該第五PMOS電晶體(MP5)的源極連接至該第二節點(N2),其閘極連接至該第一輸入端(IN),而其汲極則與該第四節點(N4)相連接;該電流阻隔開關(3)係由一第三NMOS電晶體(MN3)所組成,其源極連接至地(GND),其閘極連接至該反相致能控制端(ENB),而其汲極則與該第五節點(N5)相連接;該電流阻隔開關(4)係由一第三PMOS電晶體(MP3)所組成,其源極連接至該第一高電源供應電壓(VDDH),其閘極連接至該致能控制端(EN),而其汲極則與該第六節點(N6)相連接;該第一高電源供應電壓(VDDH)係用以提供該低功率電壓位準轉換器所需之第一高電源電壓;該第二高電源供應電壓(VDDL)係用以提供該低功率電壓位準轉換器所需之第二高電源電壓;該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準;該第一信號為介於0伏特及1.2伏特間的矩形波,而該第二信號則為介於0伏特及1.8伏特間的對應波形,該第一高電源供應電壓(VDDH)為1.8伏特,而 該第二高電源供應電壓(VDDL)為1.2伏特,該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波,該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above-mentioned purpose, this creation proposes a low-power voltage-level converter, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2), a current blocking switch (3), and It is composed of a current blocking switch (4), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the current blocking switch (3) When the current blocking switch (3) is in the closed state and the output voltage level is higher than the input voltage level, it prevents the flow of current to prevent damage to the device; and the current blocking switch (4) is used When the current blocking switch (4) is in the off state and the output voltage level is higher than the input voltage level, the current flow is prevented to prevent damage to the device; the input circuit (1) is composed of a first NMOS transistor ( MN1), a second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the fifth node (N5), which The gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the fifth node (N5) , Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the first inverting The device (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)) and providing a signal that is inverse to the first signal (V(IN)); The latch circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a fourth PMOS transistor (MP4), and a fifth PMOS transistor (MP5) , Wherein the source of the first PMOS transistor (MP1) is connected to the sixth node (N6), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1) ) Are connected; the source of the second PMOS transistor (MP2) is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the second node ( N2) phase connection; the source of the fourth PMOS transistor (MP4) is connected to the first node (N1), its gate is connected to the second input terminal (INB), and its drain is connected to the third Node (N3) is connected; the source of the fifth PMOS transistor (MP5) is connected to the second node (N2), its gate is connected to the first input (IN), and its drain is connected to the The fourth node (N4) is connected; the current blocking switch (3) is composed of a third NMOS transistor (MN3), its source is connected to ground (GND), and its gate is connected to the inverting enable The control terminal (ENB), and its drain is connected to the fifth node (N5); the current blocking switch (4) is composed of a third PMOS transistor (MP3), and its source is connected to the A high power supply voltage (VDDH), its gate is connected to the enable control terminal (EN), and its drain is connected to the sixth node (N6); the first high power supply voltage (VDDH) is Used to provide the first high power supply voltage required by the low power voltage level converter; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the low power voltage level converter The level of the second high power supply voltage (VDDL) is less than the level of the first high power supply voltage (VDDH); the first signal is a rectangular wave between 0 volts and 1.2 volts, and the first The two signals have corresponding waveforms between 0 volts and 1.8 volts. The first high power supply voltage (VDDH) is 1.8 volts, and The second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V(OUT)) is a medium Corresponding waveforms between 0 volts and 1.8 volts.
請再參閱第3圖,當該致能控制端(EN)的信號為邏輯低位準,而反相致能控制端(ENB)的信號為邏輯高位準時,該第三PMOS電晶體(MP3)和該第三NMOS電晶體(MN3)都導通(ON),現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時,低功率電壓位準轉換器的穩態操作情形:第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第四PMOS電晶體(MP4)以及該第一NMOS電晶體(MN1)的閘極,使得該第四PMOS電晶體(MP4)導通(ON),該第一NMOS電晶體(MN1)截止(OFF),而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第五PMOS電晶體(MP5)以及該第二NMOS電晶體(MN2)的閘極,使得該第五PMOS電晶體(MP5)截止(OFF),該第二NMOS電晶體(MN2)導通(ON),此時,由於該第五PMOS電晶體(MP5)截止(OFF),而該第二NMOS電晶體(MN2)和該第五NMOS電晶體(MN5)都導通(ON),該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特),該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極,使得該第一PMOS電晶體(MP1)導通(ON),此時由於該第一PMOS電晶體(MP1)和該第四PMOS電晶體(MP4)都導通(ON),而該第一NMOS電晶體(MN1)截止(OFF),因此,該第三節點(N3)的電位會被拉升至一邏輯高位準,該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)截止(OFF),此時由於該第二PMOS電晶體(MP2)和該第五PMOS電晶體(MP5)都截止(OFF),而該第二NMOS電晶體(MN2) 和該第五NMOS電晶體(MN5)都導通(ON),因此,該第四節點(N4)的電位會維持在一邏輯低位準(0伏特),輸出端(OUT)的電位亦維持在一邏輯低位準(0伏特)的穩態值。質言之,第一信號(V(IN))為邏輯低位準(0伏特)時,經過低功率電壓位準轉換器轉換成具邏輯低位準(0伏特)的第二信號,由輸出端(OUT)輸出。 Please refer to Figure 3 again. When the signal of the enable control terminal (EN) is at a logic low level and the signal of the inverted enable control terminal (ENB) is at a logic high level, the third PMOS transistor (MP3) and The third NMOS transistors (MN3) are all turned on (ON). Now consider the steady-state operation of the low-power voltage-level converter when the first signal (V(IN)) is at a logic low level (0 volts): The logic low level on an input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the fourth PMOS transistor (MP4) and the gate of the first NMOS transistor (MN1), The fourth PMOS transistor (MP4) is turned on (ON), the first NMOS transistor (MN1) is turned off (OFF), and the first inverter (I1) transmits the logic high level (VDDL) to the fifth The gate of the PMOS transistor (MP5) and the second NMOS transistor (MN2) turns off (OFF) the fifth PMOS transistor (MP5), and turns on (ON) the second NMOS transistor (MN2). At this time, since the fifth PMOS transistor (MP5) is turned off (OFF), and the second NMOS transistor (MN2) and the fifth NMOS transistor (MN5) are both turned on (ON), the fourth node (N4) Will be pulled down to a logic low level (0V), and the logic low level on the fourth node (N4) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on (ON). At this time, since the first PMOS transistor (MP1) and the fourth PMOS transistor (MP4) are both turned on (ON), and the first NMOS transistor (MN1) is turned off (OFF) Therefore, the potential of the third node (N3) will be pulled up to a logic high level, and the logic high level of the third node (N3) makes the second PMOS transistor (MP2) turn off (OFF). Since the second PMOS transistor (MP2) and the fifth PMOS transistor (MP5) are both turned off (OFF), and the second NMOS transistor (MN2) Both the fifth NMOS transistor (MN5) and the fifth NMOS transistor (MN5) are turned on (ON). Therefore, the potential of the fourth node (N4) is maintained at a logic low level (0V), and the potential at the output terminal (OUT) is also maintained at a The steady-state value of the logic low level (0 volts). In a nutshell, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) by the low-power voltage-level converter, and the output terminal ( OUT) output.
再考慮第一信號(V(IN))為邏輯高位準時,低功率電壓位準轉換器的穩態操作情形:第一輸入端(IN)上的邏輯高位準同時傳送到該第一反相器(I1)的輸入端、該第四PMOS電晶體(MP4)以及該第一NMOS電晶體(MN1)的閘極,使得該第四PMOS電晶體(MP4)截止(OFF),該第一NMOS電晶體(MN1)導通(ON),而該第一反相器(I1)傳送邏輯低位準到該第五PMOS電晶體(MP5)以及該第二NMOS電晶體(MN2)的閘極,使得該第五PMOS電晶體(MP5)導通(ON),該第二NMOS電晶體(MN2)截止(OFF),此時,由於該第一NMOS電晶體(MN1)導通(ON),而該第四PMOS電晶體(MP4)截止(OFF),該第三節點(N3)的電位會被拉降至一邏輯低位準,該第三節點(N3)上的邏輯低位準傳送到該第二PMOS電晶體(MP2)的閘極,使得該第二PMOS電晶體(MP2)導通(ON),此時由於該第二PMOS電晶體(MP2)和該第五PMOS電晶體(MP5)都導通(ON),而該第二NMOS電晶體(MN2)截止(OFF),因此,該第四節點(N4)的電位會被拉升至一邏輯高位準,該第四節點(N4)的邏輯高位準傳送到該第一PMOS電晶體(MP1)的閘極,使得該第一PMOS電晶體(MP1)截止(OFF),此時由於該第一PMOS電晶體(MP1)和該第四PMOS電晶體(MP4)都截止(OFF),該第一NMOS電晶體(MN1)導通(ON),而該第二PMOS電晶體(MP2)和該第五PMOS電晶體 (MP5)都導通(ON),該第二NMOS電晶體(MN2)截止(OFF),因此,該第三節點(N3)的電位將維持在一邏輯低位準,而該第四節點(N4)的電位亦將維持在一邏輯高位準,輸出端(OUT)的電位亦將維持在一邏輯高位準的穩態值。質言之,第一信號(V(IN))為一第二高電源供應電壓(VDDL)時,經過低功率電壓位準轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號,由輸出端(OUT)輸出。 Consider the steady-state operation of the low-power voltage-level converter when the first signal (V(IN)) is at the logic high level: the logic high level on the first input terminal (IN) is simultaneously transmitted to the first inverter The input terminal of (I1), the fourth PMOS transistor (MP4) and the gate of the first NMOS transistor (MN1) make the fourth PMOS transistor (MP4) turn off (OFF), and the first NMOS transistor The transistor (MN1) is turned on (ON), and the first inverter (I1) transmits a logic low level to the gate of the fifth PMOS transistor (MP5) and the second NMOS transistor (MN2), so that the Five PMOS transistor (MP5) is turned on (ON), the second NMOS transistor (MN2) is turned off (OFF), at this time, because the first NMOS transistor (MN1) is turned on (ON), and the fourth PMOS transistor The transistor (MP4) is turned off (OFF), the potential of the third node (N3) will be pulled down to a logic low level, and the logic low level on the third node (N3) is transmitted to the second PMOS transistor (MP2) ), the second PMOS transistor (MP2) is turned on (ON). At this time, the second PMOS transistor (MP2) and the fifth PMOS transistor (MP5) are both turned on (ON). The second NMOS transistor (MN2) is turned off (OFF). Therefore, the potential of the fourth node (N4) is pulled up to a logic high level, and the logic high level of the fourth node (N4) is transmitted to the first The gate of the PMOS transistor (MP1) turns off the first PMOS transistor (MP1). At this time, the first PMOS transistor (MP1) and the fourth PMOS transistor (MP4) are both off ( OFF), the first NMOS transistor (MN1) is turned on (ON), and the second PMOS transistor (MP2) and the fifth PMOS transistor (MP5) are all turned on (ON), the second NMOS transistor (MN2) is turned off (OFF), therefore, the potential of the third node (N3) will be maintained at a logic low level, and the fourth node (N4) The potential of, will also be maintained at a logic high level, and the potential of the output terminal (OUT) will also be maintained at a steady-state value at a logic high level. In short, when the first signal (V(IN)) is a second high power supply voltage (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by the low-power voltage level converter , Output by the output terminal (OUT).
綜上所述,該第一信號(V(IN))為邏輯低位準(0伏特)時,該第二信號(V(OUT))亦為邏輯低位準(0伏特);而該第一信號(V(IN))為第二高電源供應電壓(VDDL)時,該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此,電壓位準轉換的目的便實現。 In summary, when the first signal (V(IN)) is at a logic low level (0V), the second signal (V(OUT)) is also at a logic low level (0V); and the first signal When (V(IN)) is the second high power supply voltage (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.
本創作所提出之低功率電壓位準轉換器之Spice暫態分析模擬結果,如第4圖所示,由該模擬結果可証實,本創作所提出之低功率電壓位準轉換器,其不但仍能快速且精確地將第一信號轉換為一第二信號,並且可有效地減少輸出端(OUT)的上拉路徑與下拉路徑之間的互相競爭,進而降低功率損耗。 The Spice transient analysis simulation results of the low-power voltage-level converter proposed in this creation are shown in Figure 4. The simulation results can confirm that the low-power voltage-level converter proposed in this creation is not only The first signal can be quickly and accurately converted into a second signal, and the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power loss.
雖然本創作特別揭露並描述了所選之最佳實施例,但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此,所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although this creation specifically discloses and describes the selected best embodiment, anyone familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.
1:輸入電路 1: Input circuit
2:栓鎖電路 2: Latch circuit
3:電流阻隔開關 3: Current blocking switch
4:電流阻隔開關 4: Current blocking switch
I1:第一反相器 I1: First inverter
N1:第一節點 N1: the first node
N2:第二節點 N2: second node
N3:第三節點 N3: third node
N4:第四節點 N4: Fourth node
N5:第五節點 N5: fifth node
N6:第六節點 N6: sixth node
MP1:第一PMOS電晶體 MP1: The first PMOS transistor
MP2:第二PMOS電晶體 MP2: second PMOS transistor
MP3:第三PMOS電晶體 MP3: third PMOS transistor
MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor
MP5:第五PMOS電晶體 MP5: The fifth PMOS transistor
MN1:第一NMOS電晶體 MN1: The first NMOS transistor
MN2:第二NMOS電晶體 MN2: Second NMOS transistor
MN3:第三NMOS電晶體 MN3: The third NMOS transistor
GND:地 GND: ground
OUT:輸出端 OUT: output terminal
V(OUT):第二信號 V(OUT): second signal
IN:第一輸入端 IN: the first input
V(IN):第一信號 V(IN): the first signal
INB:第二輸入端 INB: second input
EN:致能控制端 EN: Enable control terminal
ENB:反相致能控制端 ENB: Reverse enable control terminal
VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage
VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4K | Annulment or lapse of a utility model due to non-payment of fees |