TWM626415U - Voltage level shifter with reduced static leakage current - Google Patents

Voltage level shifter with reduced static leakage current Download PDF

Info

Publication number
TWM626415U
TWM626415U TW110214206U TW110214206U TWM626415U TW M626415 U TWM626415 U TW M626415U TW 110214206 U TW110214206 U TW 110214206U TW 110214206 U TW110214206 U TW 110214206U TW M626415 U TWM626415 U TW M626415U
Authority
TW
Taiwan
Prior art keywords
pmos transistor
node
drain
signal
gate
Prior art date
Application number
TW110214206U
Other languages
Chinese (zh)
Inventor
余建政
賴永瑄
邱崑霖
Original Assignee
修平學校財團法人修平科技大學
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 修平學校財團法人修平科技大學 filed Critical 修平學校財團法人修平科技大學
Priority to TW110214206U priority Critical patent/TWM626415U/en
Publication of TWM626415U publication Critical patent/TWM626415U/en

Links

Images

Classifications

    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Logic Circuits (AREA)

Abstract

本創作提出一種減少靜態漏電流之電位轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一節電控制開關電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存轉換的輸出電位並且減少靜態漏電流；該節電控制開關電路(3)係用以在待機狀態時，阻止電流的流動，以減少功率損耗。 The present invention proposes a potential converter for reducing static leakage current, which is composed of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), wherein the input circuit (1) is used to provide differential input signal; the latch circuit (2) is used to save the converted output potential and reduce static leakage current; the power saving control switch circuit (3) is used to prevent the flow of current in the standby state , to reduce power loss.

本創作所提出之減少靜態漏電流之電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少閒置狀態下的漏電流，進而降低功率損耗。 The potential converter for reducing static leakage current proposed in this work can not only accurately convert the first signal into a second signal, but also has multiple functions such as a simple circuit structure and the miniaturization of the device, and at the same time, it can effectively ground to reduce the leakage current in the idle state, thereby reducing the power loss.

Description

減少靜態漏電流之電位轉換器 Potential Shifter to Reduce Static Leakage Current

本創作提出一種減少靜態漏電流之電位轉換器，尤指一由一輸入電路(1)、一栓鎖電路(2)以及一節電控制開關電路(3)所組成，以求獲得精確電壓位準轉換，同時亦能有效降低功率損耗之電子電路。 The present invention proposes a potential converter for reducing static leakage current, especially one consisting of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), in order to obtain accurate voltage levels It can also effectively reduce the power loss of electronic circuits.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal.

第1圖係顯示另一先前技藝(prior art)之一鏡像型電位轉換器，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電位轉換器的性能也不會有太大 的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 FIG. 1 shows another prior art mirror-type potential converter by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) to together and connected to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the currents flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too great change. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is created between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

第2圖係顯示一先前技藝之一閂鎖型電位轉換器，其係使用一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)所組成，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位 被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 FIG. 2 shows a prior art latch-type potential converter using a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1), A second NMOS transistor (MN2) and an inverter (INV), wherein the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and the ground (GND), and the first The potential of a signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type There is no static current generated in the potential converter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is on and the second NMOS transistor (MN2) is off, the gate potential of the second PMOS transistor (MP2) It is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up and the first PMOS transistor (MP1) is turned off. Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), the output terminal is The pull-up and pull-down of the potential on (OUT) have a phenomenon of contention, so the speed of the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) are fully turned on or turned off, which will cause a static current (static current) between the first high power supply voltage (VDDH) and the ground (GND). current), this quiescent current will increase the power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在 第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。 Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) in which the latch-type potential converter can operate normally is limited. When the second PMOS transistor (MP2) tends to turn on (or off) and the When the second NMOS transistor (MN2) tends to be turned off (or turned on), there is a phenomenon of contention for the pull-up and pull-down of the potential on the output terminal (OUT), so the second signal (V (OUT)) is slower when transitioning to a low potential.

有鑑於此，本創作之主要目的係提出一種減少靜態漏電流之電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少閒置狀態下的漏電流，進而降低功率損耗。 In view of this, the main purpose of this creation is to provide a potential converter for reducing static leakage current, which can not only accurately and quickly convert a first signal into a second signal, but also effectively reduce leakage current in an idle state. , thereby reducing power loss.

本創作提出一種減少靜態漏電流之電位轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一節電控制開關電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存轉換的輸出電位並且減少閒置狀態下的漏電流；該節電控制開關電路(3)係用以在待機狀態時，阻止電流的流動，以減少功率損耗。 The present invention proposes a potential converter for reducing static leakage current, which is composed of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and reduce the leakage current in the idle state; the power saving control switch circuit (3) is used to prevent the flow of current to reduce power loss.

由模擬結果證實，本創作所提出之減少靜態漏電流之電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results confirm that the potential converter for reducing static leakage current proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is conducive to the miniaturization of the device, etc. Multiple functions, while also effectively reducing power consumption.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:節電控制開關 3: Power saving control switch

GND:地 GND: ground

I1:第一反相器 I1: first inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

N5:第五節點 N5: Fifth node

N6:第六節點 N6: sixth node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MP7:第七PMOS電晶體 MP7: seventh PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: the third NMOS transistor

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): Second signal

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

EN:致能控制端 EN: Enable control terminal

ENB:反相致能控制端 ENB: Inverting enable control terminal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

第1圖 係顯示第一先前技藝中電位轉換器之電路圖； FIG. 1 is a circuit diagram showing a potential converter in the first prior art;

第2圖 係顯示第二先前技藝中電位轉換器之電路圖； FIG. 2 is a circuit diagram showing a potential converter in the second prior art;

第3圖 係顯示本創作較佳實施例之減少靜態漏電流之電位轉換器之電路 圖； Figure 3 shows the circuit of the potential converter for reducing static leakage current according to the preferred embodiment of the present invention picture;

第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； FIG. 4 is a timing chart of transient analysis of the first signal and the second signal according to the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種減少靜態漏電流之電位轉換器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)以及一節電控制開關電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存轉換的輸出電位並且減少靜態漏電流；該節電控制開關電路(3)係用以在待機狀態時，阻止電流的流動，以減少功率損耗；該輸入電路(1)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第二NMOS電晶體(MN2)的源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)、一第四PMOS電晶體(MP4)、一第六PMOS電晶體(MP6)以及一第七PMOS電晶體(MP7)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第六節點(N6)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第六節點(N6)，其閘極連接至該第 三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三PMOS電晶體(MP3)的源極連接至該第六節點(N6)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第六節點(N6)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該第六PMOS電晶體(MP6)的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第七PMOS電晶體(MP7)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該節電控制開關電路(3)係由一第五PMOS電晶體(MP5)、一第三NMOS電晶體(MN3)、一致能控制端(EN)以及一反相致能控制端(ENB)所組成，其中，該第五PMOS電晶體(MP5)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第六節點(N6)相連接；該第三NMOS電晶體(MN3)的源極連接至地(GND)，其閘極連接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接；該致能控制端(EN)係耦接於該第五PMOS電晶體(MP5)的閘極，用以提供一致能信號；該反相致能控制端(ENB)係耦接於該第三NMOS電晶體(MN3)的閘極，用以提供一反相致能信號；該第一高電源供應電壓(VDDH)係用以提供該減少靜態漏電流之電位轉換器所需之第一高電源電壓；該第二高電源供應電壓(VDDL)係用以提供該減少靜態漏電流之電位轉換器所需之第二高電源電壓；該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位 準；該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes a potential converter for reducing static leakage current, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2) and a power-saving control switch circuit (3) ), wherein the input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and reduce static leakage current; the power-saving control switch circuit (3) It is used to prevent the flow of current in the standby state to reduce power loss; the input circuit (1) is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter A phase device (I1) is formed, wherein the source of the first NMOS transistor (MN1) is connected to the fifth node (N5), the gate is connected to the first input terminal (IN), and the drain is is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)), and provide a signal inverse to the first signal (V(IN)); the latch circuit (2) consists of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a first PMOS transistor (MP2), and a It consists of three PMOS transistors (MP3), a fourth PMOS transistor (MP4), a sixth PMOS transistor (MP6) and a seventh PMOS transistor (MP7), wherein the first PMOS transistor (MP1) ) source is connected to the sixth node (N6), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the second PMOS transistor ( The source of MP2) is connected to the sixth node (N6), and its gate is connected to the sixth node (N6). Three nodes (N3), and its drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the sixth node (N6), and its gate is connected to the A first input terminal (IN), and its drain is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the sixth node (N6), and its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); the source of the sixth PMOS transistor (MP6) is connected to the first node (N1), and its gate The electrode is connected to the first input terminal (IN), and the drain electrode is connected to the third node (N3); the source electrode of the seventh PMOS transistor (MP7) is connected to the second node (N2), Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the power saving control switch circuit (3) is composed of a fifth PMOS transistor (MP5), A third NMOS transistor (MN3), an enable control terminal (EN) and an inversion enable control terminal (ENB), wherein the source of the fifth PMOS transistor (MP5) is connected to the first High power supply voltage (VDDH), its gate is connected to the enable control terminal (EN), and its drain is connected to the sixth node (N6); the source of the third NMOS transistor (MN3) Connected to ground (GND), its gate is connected to the inversion enabling control terminal (ENB), and its drain is connected to the fifth node (N5); the enabling control terminal (EN) is coupled to The gate of the fifth PMOS transistor (MP5) is used to provide an enable signal; the inversion enable control terminal (ENB) is coupled to the gate of the third NMOS transistor (MN3) for use An inversion enable signal is provided; the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the level shifter for reducing static leakage current; the second high power supply voltage (VDDL) It is used to provide the second high power supply voltage required by the potential converter for reducing static leakage current; the level of the second high power supply voltage (VDDL) is smaller than the level of the first high power supply voltage (VDDH) standard; the first signal is a rectangular wave between 0 volts and 1.2 volts, the second signal is a corresponding waveform between 0 volts and 1.8 volts, and the first high power supply voltage (VDDH) is 1.8 volts, the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, the second signal (V(OUT)) is the corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，茲依減少靜態漏電流之電位轉換器之工作模式說明圖3之工作原理如下： Please refer to Figure 3 again to illustrate the working mode of the potential converter for reducing static leakage current. The working principle of Figure 3 is as follows:

(I)主動模式(Active mode) (I) Active mode

當該致能控制端(EN)的信號為邏輯低位準，而反相致能控制端(ENB)的信號為邏輯高位準時，該第五PMOS電晶體(MP5)和該第三NMOS電晶體(MN3)都導通(ON)，電位轉換器處於主動(active)狀態；現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第三PMOS電晶體(MP3)、該第六PMOS電晶體(MP6)以及該第一NMOS電晶體(MN1)的閘極，使得該第一NMOS電晶體(MN1)截止(OFF)，該第三PMOS電晶體(MP3)和該第六PMOS電晶體(MP6)都導通(ON)；而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第四PMOS電晶體(MP4)、該第七PMOS電晶體(MP7)以及該第二NMOS電晶體(MN2)的閘極，使得該第二NMOS電晶體(MN2)導通(ON)，該第七PMOS電晶體(MP7)和該第四PMOS電晶體(MP4)都截止(OFF)，此時，由於該第七PMOS電晶體(MP7)和該第四PMOS電晶體(MP4)都截止(OFF)，而該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都導通(ON)，該第四節點(N4)的電位會被拉降至一邏輯 低位準(0伏特)，該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通(ON)，此時由於該第一PMOS電晶體(MP1)、該第三PMOS電晶體(MP3)和該第六PMOS電晶體(MP6)都導通(ON)，而該第一NMOS電晶體(MN1)截止(OFF)，因此，該第三節點(N3)的電位會被拉升至一邏輯高位準，該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)截止(OFF)，此時由於該第二PMOS電晶體(MP2)、該第四PMOS電晶體(MP4)和該第七PMOS電晶體(MP7)都截止(OFF)，而該第二NMOS電晶體(MN2)導通(ON)，因此，該第四節點(N4)的電位會維持在一邏輯低位準(0伏特)的穩態值，在輸出端(OUT)輸出一邏輯低位準(0伏特)的電位。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過減少靜態漏電流之電位轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 When the signal of the enable control terminal (EN) is at a logic low level and the signal at the inversion enable control terminal (ENB) is at a logic high level, the fifth PMOS transistor (MP5) and the third NMOS transistor ( MN3) are all turned on (ON), and the potential converter is in an active state; now consider the steady-state operation of the potential converter when the first signal (V(IN)) is a logic low level (0 volts): first The logic low level on the input terminal (IN) is simultaneously transmitted to the input terminal of the first inverter (I1), the third PMOS transistor (MP3), the sixth PMOS transistor (MP6) and the first NMOS the gate of the transistor (MN1), so that the first NMOS transistor (MN1) is turned off (OFF), the third PMOS transistor (MP3) and the sixth PMOS transistor (MP6) are both turned on (ON); and The first inverter (I1) transmits a logic high level (VDDL) to the gates of the fourth PMOS transistor (MP4), the seventh PMOS transistor (MP7) and the second NMOS transistor (MN2), The second NMOS transistor (MN2) is turned on (ON), and the seventh PMOS transistor (MP7) and the fourth PMOS transistor (MP4) are both turned off (OFF). At this time, due to the seventh PMOS transistor (MP7) and the fourth PMOS transistor (MP4) are both turned off (OFF), while the second NMOS transistor (MN2) and the third NMOS transistor (MN3) are both turned on (ON), the fourth node ( The potential of N4) will be pulled down to a logic Low level (0 volts), the logic low level on the fourth node (N4) is transmitted to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on (ON), this When the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the sixth PMOS transistor (MP6) are all turned on (ON), the first NMOS transistor (MN1) is turned off (OFF). ), therefore, the potential of the third node (N3) will be pulled up to a logic high level, and the logic high level of the third node (N3) makes the second PMOS transistor (MP2) turned off (OFF), which Since the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) are all turned off (OFF), the second NMOS transistor (MN2) is turned on (ON). ), therefore, the potential of the fourth node (N4) maintains a steady state value of a logic low level (0 volts), and outputs a logic low level (0 volts) potential at the output terminal (OUT). In other words, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through a potential converter that reduces static leakage current, and is sent from the output terminal. (OUT) output.

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第三PMOS電晶體(MP3)、該第六PMOS電晶體(MP6)以及該第一NMOS電晶體(MN1)的閘極，使得該第一NMOS電晶體(MN1)導通(ON)，該第六PMOS電晶體(MP6)和該第三PMOS電晶體(MP3)都截止(OFF)，該第三節點(N3)的電位會被拉降至一邏輯低位準(0伏特)，該第三節點(N3)的邏輯低位準使得該第二PMOS電晶體(MP2)導通(ON)；而該第一反相器(I1)傳送邏輯低位準到該第四PMOS電晶體(MP4)、該第七PMOS電晶體(MP7)以及該第二NMOS電晶體(MN2)的閘極，使得該第二NMOS電晶體(MN2)截止(OFF)，該第七PMOS電晶體(MP7)和該第四PMOS 電晶體(MP4)都導通(ON)，此時，由於該第二PMOS電晶體(MP2)、該第四PMOS電晶體(MP4)和該第七PMOS電晶體(MP7)都導通(ON)，而該第二NMOS電晶體(MN2)截止(OFF)，因此，該第四節點(N4)的電位會被拉升至一邏輯高位準，該第四節點(N4)的邏輯高位準使得該第一PMOS電晶體(MP1)截止(OFF)，此時由於該第一PMOS電晶體(MP1)、該第三PMOS電晶體(MP3)和該第六PMOS電晶體(MP6)都截止(OFF)，該第一NMOS電晶體(MN1)導通(ON)，該第三節點(N3)的電位會維持在一邏輯低位準，而該第四節點(N4)的電位會維持在一邏輯高位準的穩態值，在輸出端(OUT)輸出一邏輯高位準的電位。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過減少靜態漏電流之電位轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 Then consider the steady state operation of the potential converter when the first signal (V(IN)) is at a logic high level (VDDL): the logic high level (VDDL) on the first input terminal (IN) is simultaneously transmitted to the first The input terminal of the inverter (I1), the third PMOS transistor (MP3), the sixth PMOS transistor (MP6), and the gate of the first NMOS transistor (MN1), so that the first NMOS transistor (MN1) is turned on (ON), the sixth PMOS transistor (MP6) and the third PMOS transistor (MP3) are both turned off (OFF), and the potential of the third node (N3) will be pulled down to a logic low level level (0 volts), the logic low level of the third node (N3) makes the second PMOS transistor (MP2) conductive (ON); and the first inverter (I1) transmits a logic low level to the fourth The gates of the PMOS transistor (MP4), the seventh PMOS transistor (MP7) and the second NMOS transistor (MN2) make the second NMOS transistor (MN2) cut off (OFF), and the seventh PMOS transistor (MN2) is turned off. crystal (MP7) and the fourth PMOS The transistors (MP4) are all turned on (ON). At this time, since the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the seventh PMOS transistor (MP7) are all turned on (ON), And the second NMOS transistor (MN2) is turned off (OFF), therefore, the potential of the fourth node (N4) is pulled to a logic high level, and the logic high level of the fourth node (N4) makes the fourth node (N4) high. A PMOS transistor (MP1) is turned off (OFF). At this time, since the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the sixth PMOS transistor (MP6) are all turned off (OFF), The first NMOS transistor (MN1) is turned on (ON), the potential of the third node (N3) is maintained at a logic low level, and the potential of the fourth node (N4) is maintained at a logic high level stable The state value is outputted at the output terminal (OUT) with a logic high level potential. In other words, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with a first high power supply voltage (VDDH) through a potential converter that reduces static leakage current, and is generated by Output terminal (OUT) output.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電位轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a logic low level (0 volts), the second signal (V(OUT)) is also at a logic low level (0 volts); and the first signal When (V(IN)) is a logic high level (VDDL), the second signal (V(OUT)) is a first high power supply voltage (VDDH). In this way, the purpose of potential conversion is achieved.

(II)待機模式(Standby mode) (II) Standby mode (Standby mode)

請再參考圖3。當該致能控制端(EN)的信號為邏輯高位準，而反相致能控制端(ENB)的信號為邏輯低位準時，該第五PMOS電晶體(MP5)和該第三NMOS電晶體(MN3)都截止(OFF)，電位轉換器處於待機(standby)狀態。其工作原理於此不再累述。 Please refer to Figure 3 again. When the signal of the enable control terminal (EN) is at a logic high level and the signal at the inversion enable control terminal (ENB) is at a logic low level, the fifth PMOS transistor (MP5) and the third NMOS transistor ( MN3) are all turned off (OFF), and the potential converter is in a standby state. Its working principle is not repeated here.

本創作所提出之減少靜態漏電流之電位轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之減少 靜態漏電流之電位轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且可有效地減少靜態漏電流，進而降低功率損耗。 The simulation results of Spice transient analysis of the potential converter to reduce static leakage current proposed in this work are shown in Figure 4. The simulation results can confirm that the reduction proposed in this work The potential converter for static leakage current can not only convert the first signal into a second signal quickly and accurately, but also can effectively reduce the static leakage current, thereby reducing power consumption.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:節電控制開關 3: Power saving control switch

GND:地 GND: ground

I1:第一反相器 I1: first inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

N5:第五節點 N5: Fifth node

N6:第六節點 N6: sixth node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MP7:第七PMOS電晶體 MP7: seventh PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: the third NMOS transistor

OUT:輸出端 OUT: output terminal

V(OUT):第二信號 V(OUT): Second signal

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

EN:致能控制端 EN: Enable control terminal

ENB:反相致能控制端 ENB: Inverting enable control terminal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

Claims (7)

一種減少靜態漏電流之電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括： A potential converter for reducing static leakage current for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: 一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極以及一第六PMOS電晶體(MP6)的源極連接在一起； A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the source of a sixth PMOS transistor (MP6) together; 一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極以及一第七PMOS電晶體(MP7)的源極連接在一起； A second node (N2) for connecting the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the source of a seventh PMOS transistor (MP7) together; 一第三節點(N3)，用以將該第二PMOS電晶體(MP2)的閘極、該第六PMOS電晶體(MP6)的汲極以及一第一NMOS電晶體(MN1)的汲極連接在一起； A third node (N3) for connecting the gate of the second PMOS transistor (MP2), the drain of the sixth PMOS transistor (MP6) and the drain of a first NMOS transistor (MN1) together; 一第四節點(N4)，用以將該第一PMOS電晶體(MP1)的閘極、該第七PMOS電晶體(MP7)的汲極以及一第二NMOS電晶體(MN2)的汲極連接在一起； A fourth node (N4) for connecting the gate of the first PMOS transistor (MP1), the drain of the seventh PMOS transistor (MP7) and the drain of a second NMOS transistor (MN2) together; 一第五節點(N5)，用以將該第一NMOS電晶體(MN1)、該第二NMOS電晶體(MN2)的源極以及一第三NMOS電晶體(MN3)的汲極連接在一起； a fifth node (N5) for connecting the first NMOS transistor (MN1), the source of the second NMOS transistor (MN2) and the drain of a third NMOS transistor (MN3) together; 一第六節點(N6)，用以將該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)、該第三PMOS電晶體(MP3)、該第四PMOS電晶體(MP4)的源極以及一第五PMOS電晶體(MP5)的汲極連接在一起； A sixth node (N6) for the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS transistor (MP4) The source and the drain of a fifth PMOS transistor (MP5) are connected together; 一第一輸入端(IN)，耦接於該第六PMOS電晶體(MP6)、該第一NMOS電晶體(MN1)、該第三PMOS電晶體(MP3)的閘極以及一第一反相器(I1)的輸入端，用以提供該第一信號(V(IN))； A first input terminal (IN) coupled to the sixth PMOS transistor (MP6), the first NMOS transistor (MN1), the gate of the third PMOS transistor (MP3) and a first inverting the input end of the device (I1) for providing the first signal (V(IN)); 一第二輸入端(INB)，耦接於該第七PMOS電晶體(MP7)、該第二NMOS電晶體(MN2)、該第四PMOS電晶體(MP4)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號； A second input terminal (INB) coupled to the seventh PMOS transistor (MP7), the second NMOS transistor (MN2), the gate of the fourth PMOS transistor (MP4) and the first inverting The output terminal of the device (I1) is used to provide the inverted signal of the first signal (V(IN)); 一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))； an output terminal (OUT) coupled to the fourth node (N4) for outputting the second signal (V(OUT)); 一第一高電源供應電壓(VDDH)，耦接於該第五PMOS電晶體(MP5)的源極，用以提供該電位轉換器所需之第一高電源電壓； a first high power supply voltage (VDDH) coupled to the source of the fifth PMOS transistor (MP5) for providing the first high power supply voltage required by the potential converter; 一第二高電源供應電壓(VDDL)，用以提供該電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位； A second high power supply voltage (VDDL) for providing the second high power supply voltage required by the level converter, and the potential of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage (VDDH) ) of the potential; 一輸入電路(1)，耦接於該第一輸入端(IN)，用來提供差動輸入信號； an input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal; 一栓鎖電路(2)，耦接於該第六節點(N6)以及該輸入電路(1)，用來保存轉換的輸出電位並且減少靜態漏電流；以及 a latch circuit (2), coupled to the sixth node (N6) and the input circuit (1), for preserving the converted output potential and reducing static leakage current; and 一節電控制開關電路(3)，係用以在待機狀態時，阻止電流的流動，以減少功率損耗。 A power-saving control switch circuit (3) is used for preventing the flow of current in a standby state, so as to reduce power consumption. 如申請專利範圍第1項所述的減少靜態漏電流之電位轉換器，其中該輸入電路(1)包括： The potential converter for reducing static leakage current as described in claim 1, wherein the input circuit (1) comprises: 一第一NMOS電晶體(MN1)，其源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接； A first NMOS transistor (MN1) whose source is connected to the fifth node (N5), whose gate is connected to the first input terminal (IN), and whose drain is connected to the third node (N3) connected; 一第二NMOS電晶體(MN2)，其源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及 A second NMOS transistor (MN2) whose source is connected to the fifth node (N5), whose gate is connected to the second input terminal (INB), and whose drain is connected to the fourth node (N4) connected; and 一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) inverted signal. 如申請專利範圍第2項所述的減少靜態漏電流之電位轉換器，其中該栓鎖電路(2)包括： The potential converter for reducing static leakage current as described in claim 2, wherein the latch circuit (2) comprises: 一第一PMOS電晶體(MP1)，其源極連接至該第六節點(N6)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接； A first PMOS transistor (MP1), its source is connected to the sixth node (N6), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1) connect; 一第二PMOS電晶體(MP2)，其源極連接至該第六節點(N6)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接； A second PMOS transistor (MP2), its source is connected to the sixth node (N6), its gate is connected to the third node (N3), and its drain is connected to the second node (N2) connect; 一第三PMOS電晶體(MP3)，其源極連接至該第六節點(N6)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接； A third PMOS transistor (MP3), whose source is connected to the sixth node (N6), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1) connected; 一第四PMOS電晶體(MP4)，其源極連接至該第六節點(N6)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接； A fourth PMOS transistor (MP4), whose source is connected to the sixth node (N6), whose gate is connected to the second input terminal (INB), and whose drain is connected to the second node (N2) connected; 一第六PMOS電晶體(MP6)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；以及 A sixth PMOS transistor (MP6) has its source connected to the first node (N1), its gate connected to the first input terminal (IN), and its drain connected to the third node (N3) connected; and 一第七PMOS電晶體(MP7)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接。 A seventh PMOS transistor (MP7), its source is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4) connected. 如申請專利範圍第3項所述的減少靜態漏電流之電位轉換器，其中該節電控制開關電路(3)包括： The potential converter for reducing static leakage current as described in claim 3, wherein the power-saving control switch circuit (3) comprises: 一第五PMOS電晶體(MP5)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該致能控制端(EN)，而其汲極則與該第六節點(N6)相連接； A fifth PMOS transistor (MP5), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the enable control terminal (EN), and its drain is connected to the sixth node (N6) is connected; 一第三NMOS電晶體(MN3)，其源極連接至地(GND)，其閘極連接至該反相致能控制端(ENB)，而其汲極則與該第五節點(N5)相連接； A third NMOS transistor (MN3), its source is connected to ground (GND), its gate is connected to the inverting enable control terminal (ENB), and its drain is connected to the fifth node (N5) connect; 一致能控制端(EN)，耦接於該第五PMOS電晶體(MP5)的閘極，用以提供一致能信號；以及 an enable control terminal (EN) coupled to the gate of the fifth PMOS transistor (MP5) for providing an enable signal; and 一反相致能控制端(ENB)，耦接於該第三NMOS電晶體(MN3)的閘極，用以提供一反相致能信號。 An inversion enable control terminal (ENB) is coupled to the gate of the third NMOS transistor (MN3) for providing an inversion enable signal. 如申請專利範圍第1項所述的減少靜態漏電流之電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The level converter for reducing static leakage current as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). 如申請專利範圍第5項所述的減少靜態漏電流之電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The level converter for reducing static leakage current as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). 如申請專利範圍第2項所述的減少靜態漏電流之電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The potential converter for reducing static leakage current as described in claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).
TW110214206U 2021-11-30 2021-11-30 Voltage level shifter with reduced static leakage current TWM626415U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW110214206U TWM626415U (en) 2021-11-30 2021-11-30 Voltage level shifter with reduced static leakage current

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110214206U TWM626415U (en) 2021-11-30 2021-11-30 Voltage level shifter with reduced static leakage current

Publications (1)

Publication Number Publication Date
TWM626415U true TWM626415U (en) 2022-05-01

Family

ID=82559095

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110214206U TWM626415U (en) 2021-11-30 2021-11-30 Voltage level shifter with reduced static leakage current

Country Status (1)

Country Link
TW (1) TWM626415U (en)

Similar Documents

Publication Publication Date Title
TWM616390U (en) Low power voltage level shifter
TWM598009U (en) Voltage level shifter having output control circuit
TWM586017U (en) Low power level shifter circuit
TWM576365U (en) Low power voltage level converter
TWM626415U (en) Voltage level shifter with reduced static leakage current
TWM565921U (en) Voltage level shifter
TWM576366U (en) Level conversion circuit with auxiliary circuit
TWM625119U (en) Voltage level converting circuit with reduced power consumption
TWM628475U (en) Low power and high performance voltage level converting circuit
TWM626414U (en) Voltage level converter with stack transistors
TWM625120U (en) Voltage level converter with leakage current reduction
TWM628446U (en) Contention-free level converting circuit for data receiving circuit
TWM618862U (en) Voltage level shifter with low power consumption
TWM643324U (en) Low power level converter with inhibit current circuit
TWM645482U (en) High speed voltage level converter having low power consumption
TWM643325U (en) Low power level converter with output control circuit
TWM629687U (en) High performance voltage level shifter
TWM647689U (en) High speed voltage level converter with low power consumption
TWM626307U (en) Contention-reduced level converting circuit
TWM601491U (en) Voltage level shifter with low power consumption
TWM599059U (en) Voltage level shifter having output buffer circuit
TWM635887U (en) Low-power voltage level converter with contention reduction
TWM629696U (en) High performance voltage level shifting circuit
TWM639384U (en) High-speed low-power level shifter circuit for integrated circuits having multiple power supplies
TWM604082U (en) Low power voltage level converter

Legal Events

Date Code Title Description
MM4K Annulment or lapse of a utility model due to non-payment of fees