TWM626414U

TWM626414U - Voltage level converter with stack transistors

Info

Publication number: TWM626414U
Application number: TW110214204U
Authority: TW
Inventors: 余建政; 賴永瑄; 邱崑霖
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-05-01

Abstract

本創作提出一種具電晶體堆疊結構之電壓位準轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)用來保存轉換的輸出電位並且控制漏電流；該模式控制開關(3)係設計成可因應不同操作模式而控制該第一節點(N1)和該第二節點(N2)之電壓位準，亦即該模式控制開關(3)於對應之該致能控制端(EN)的輸入信號為邏輯高位準時代表主動(active)模式，而該致能控制端(EN)的輸入信號為邏輯低位準時則為待機(standby)模式，俾藉此以於待機模式時，可有效降低功率的損耗。 The present invention provides a voltage level converter with a transistor stack structure, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit ( 1) is used to provide a differential input signal; the latch circuit (2) is used to save the converted output potential and control leakage current; the mode control switch (3) is designed to control the first The voltage levels of the node (N1) and the second node (N2), that is, the mode control switch (3) represents an active mode when the input signal of the corresponding enable control terminal (EN) is a logic high level , and when the input signal of the enable control terminal (EN) is at a logic low level, it is in a standby mode, so that the power consumption can be effectively reduced in the standby mode.

本創作所提出之具電晶體堆疊結構之電壓位準轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少漏電流，進而降低功率損耗。 The voltage level converter with the transistor stack structure proposed in this work can not only accurately convert the first signal into a second signal, but also has multiple functions such as a simple circuit structure and the miniaturization of the device, and at the same time It can also effectively reduce leakage current, thereby reducing power loss.

Description

具電晶體堆疊結構之電壓位準轉換器 Voltage level converter with transistor stack structure

本創作係有關一種具電晶體堆疊結構之電壓位準轉換器，尤指利用一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，以求獲得精確電壓位準轉換且有效地降低功率損耗之電子電路。 The present invention relates to a voltage level converter with a transistor stack structure, especially composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), in order to obtain accurate voltage Electronic circuits that convert levels and effectively reduce power consumption.

電壓位準轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level converter is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, ICs for short). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to the peripheral devices with a higher voltage level, the voltage level converter is responsible for converting the low-voltage operating signal into a high-voltage operating signal. .

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準轉換器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電壓位準轉換器電路，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極 (gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型電壓位準轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 FIG. 1 shows a prior art latch-type voltage level converter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor (MP1) ), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverting A voltage level converter circuit is formed by an inverter (INV), wherein the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and the ground (GND), and the first signal (V(IN) )) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverting input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) (gate). Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch There is no static current generated in the lock-in voltage level converter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體 (MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional voltage level converter, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), for The pull-up and pull-down of the potential on the output terminal (OUT) have a phenomenon of contention, so the speed of the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), first NMOS transistor (MN1) and the second NMOS transistor (MN2) turn on or off completely, which will cause a static current between the first high power supply voltage (VDDH) and the ground (GND). Current increases power loss.

再者，閂鎖型的電壓位準轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type voltage level converter is affected by the first high power supply voltage (VDDH), due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The gate voltage is the first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) in which the latch-type voltage level converter can operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準轉換器電路，該電壓位準轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的具電晶體堆疊結構之電壓位準轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電壓位準轉換器的性能也不會有太大的改變。因此，鏡像型的電壓位準轉換器可以適用在各種輸出電壓電路。 FIG. 2 shows another prior art mirror-type voltage level converter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) together and connected to the drain of the first PMOS transistor (MP1) so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) being in saturation region, and its gate voltage is such that the saturation current is equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type voltage-level converter with transistor stack structure is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power When the supply voltage (VDDH) changes, the performance of the voltage level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are on. In this way, a static current path is created between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種具電晶體堆疊結構之電壓位準轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少漏電流，進而降低功率損耗。 In view of this, the main purpose of this creation is to provide a voltage level converter with a transistor stack structure, which can not only accurately and quickly convert a first signal into a second signal, but also can effectively reduce leakage current, thereby reducing power loss.

本創作提出一種具電晶體堆疊結構之電壓位準轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)係耦接於該第一輸入端(IN)，用來提供差動輸入信號；該栓鎖電路(2)耦接於該第一高電源供應電壓(VDDH)，用來保存轉換的輸出電位並且控制漏電流；模式控制開關(3)係設計成可因應不同操作模式而控制該第一節點(N1)和該第二節點(N2)之電壓位準，亦即該模式控制開關(3)於對應之該致能控制端(EN)的輸入信號為邏輯高位準時代表主動(active)模式，而輸入信號為邏輯低位準時則為待機(standby)模式，俾藉此以於待機模式時，可有效降低功率的損耗；該第一高電源供應電壓(VDDH)係用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第一高電位電壓；而該第二高電源供應電壓(VDDL)係用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形。 The present invention provides a voltage level converter with a transistor stack structure, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit ( 1) is coupled to the first input terminal (IN) for providing a differential input signal; the latch circuit (2) is coupled to the first high power supply voltage (VDDH) for storing the converted output potential and control leakage current; the mode control switch (3) is designed to control the voltage levels of the first node (N1) and the second node (N2) according to different operation modes, that is, the mode control switch (3) ) When the input signal of the corresponding enable control terminal (EN) is a logic high level, it represents an active mode, and when the input signal is a logic low level, it is a standby mode, so that in the standby mode, The power loss can be effectively reduced; the first high power supply voltage (VDDH) is used to provide the first high potential voltage required by the voltage level converter with the transistor stack structure; and the second high power supply voltage (VDDL) is used to provide the second high potential voltage required by the voltage level converter with the transistor stack structure, and the potential of the second high power supply voltage (VDDL) is smaller than the first high power supply voltage ( VDDH), the level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH), and the first signal is a torque between 0 volts and 1.2 volts waveform, and the second signal is a corresponding waveform between 0 volts and 1.8 volts.

由模擬結果證實，本創作所提出之具電晶體堆疊結構之電壓位準轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 It is confirmed by the simulation results that the voltage level converter with the transistor stack structure proposed in this work can not only convert the first signal into a second signal accurately and quickly, but also has a simple circuit structure and is beneficial to the device. Multiple functions such as miniaturization can also effectively reduce power loss.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:模式控制開關 3: Mode control switch

EN:致能控制端 EN: Enable control terminal

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

OUT:輸出端 OUT: output terminal

GND:地 GND: ground

V(OUT):第二信號 V(OUT): Second signal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

I1:第一反相器 I1: first inverter

第1圖係顯示第一先前技藝中電壓位準轉換器之電路圖； FIG. 1 is a circuit diagram showing a first prior art voltage level converter;

第2圖係顯示第二先前技藝中電壓位準轉換器之電路圖； FIG. 2 is a circuit diagram showing a second prior art voltage level converter;

第3圖係顯示本創作較佳實施例之電壓位準轉換器之電路圖； Fig. 3 is a circuit diagram showing the voltage level converter of the preferred embodiment of the present invention;

第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； FIG. 4 is a timing chart of transient analysis of the first signal and the second signal according to the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種具電晶體堆疊結構之電壓位準轉換器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；其係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；而該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係耦接於該第一高電源供應電壓(VDDH)，用來保存轉換的輸出電位並且控制漏電流；其係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第三PMOS電晶體(MP3)的源極相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第四PMOS電晶體(MP4)的源極相連接；該第三PMOS電晶體(MP3)的源極連接至該第一PMOS電晶體(MP1)的汲極，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；而該第四PMOS電晶體(MP4)，其源極連接至該第二PMOS電晶體(MP2)的汲極，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該模式控制開關(3)係用以控制該具電晶體堆疊結構之電壓位準轉換器之不同操作模式；其係由一第五PMOS電晶體(MP5)、一第六PMOS電晶體(MP6)以及一致能控制端(EN)所組成，其中，該第五PMOS電晶體(MP5)的源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第一節點(N1)相連接；該第六PMOS電晶體(MP6)的源極連接至該第一高電源供應電壓 (VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第二節點(N2)相連接；而該致能控制端(EN)係耦接至該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號；該第一高電源供應電壓(VDDH)係用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第一高電位電壓；而該第二高電源供應電壓(VDDL)係用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特；該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention provides a voltage level converter with a transistor stack structure, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit (1) is used to provide a differential input signal; it is composed of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter A phase device (I1) is formed, wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input terminal (IN), and the drain is connected to the The first node (N1) is connected; the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate is connected to the second input terminal (INB), and the drain is connected to the first Two nodes (N2) are connected; and the first inverter (I1) is coupled to The first input terminal (IN) is used to receive the first signal (V(IN)) and provide a signal inverse to the first signal (V(IN)); the latch circuit (2) is a It is coupled to the first high power supply voltage (VDDH) for saving the converted output potential and controlling the leakage current; it is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a A third PMOS transistor (MP3) and a fourth PMOS transistor (MP4) are formed, wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), and its gate The electrode is connected to the second node (N2), and the drain electrode is connected to the source electrode of the third PMOS transistor (MP3); the source electrode of the second PMOS transistor (MP2) is connected to the first high voltage The power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the source of the fourth PMOS transistor (MP4); the third PMOS transistor (MP3) Its source is connected to the drain of the first PMOS transistor (MP1), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); and the A fourth PMOS transistor (MP4), its source is connected to the drain of the second PMOS transistor (MP2), its gate is connected to the second input terminal (INB), and its drain is connected to the second PMOS transistor (MP2) the node (N2) is connected; the mode control switch (3) is used for controlling different operation modes of the voltage level converter with the transistor stack structure; it is composed of a fifth PMOS transistor (MP5), a first composed of six PMOS transistors (MP6) and one enable control terminal (EN), wherein the source of the fifth PMOS transistor (MP5) is connected to the first high power supply voltage (VDDH), and the gate of the fifth PMOS transistor (MP5) is connected to the The gate of the sixth PMOS transistor (MP6) is connected to the enabling control terminal (EN), and the drain thereof is connected to the first node (N1); the sixth PMOS transistor (MP6) the source is connected to the first high power supply voltage (VDDH), the gate of which is connected to the gate of the fifth PMOS transistor (MP5) and to the enable control terminal (EN), and the drain of which is connected to the second node (N2); The enable control terminal (EN) is coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) for providing an enable signal; the first high power supply voltage (VDDH) is used to provide the first high potential voltage required by the voltage level converter with the transistor stack structure; and the second high power supply voltage (VDDL) is used to provide the transistor stack structure with a first high potential voltage. The second high potential voltage required by the voltage level converter, the potential of the second high power supply voltage (VDDL) is smaller than the potential of the first high power supply voltage (VDDH), the first high power supply voltage (VDDH) ) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts, the second signal (V( OUT)) is the corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，茲依具電晶體堆疊結構之電壓位準轉換器之工作模式說明圖3之工作原理如下： Please refer to Fig. 3 again, and the working principle of Fig. 3 is explained according to the working mode of the voltage level converter with the transistor stack structure as follows:

(I)主動模式(Active mode) (I) Active mode

在主動模式下，亦即，當該致能控制端(EN)是在高電位(VDDH)狀態時，該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)均呈關閉(OFF)狀態。 In the active mode, that is, when the enable control terminal (EN) is in a high potential (VDDH) state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both turned off ( OFF) state.

現在考慮第一信號(V(IN))為低電位(0伏特)時，具電晶體堆疊結構之電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的低電位同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)的閘極以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)關閉(OFF)、該第三 PMOS電晶體(MP3)導通，而該第一反相器(I1)傳送第二高電源供應電壓(VDDL)到該第二NMOS電晶體(MN2)、該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)導通、該第四PMOS電晶體(MP4)關閉，此時，由於該第二NMOS電晶體(MN2)導通、該第四PMOS電晶體(MP4)關閉，因此，該第二節點(N2)的電位會被拉降至一低電位(0伏特)，再者，該第二節點(N2)上的低電位傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，由於該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都導通，該第一NMOS電晶體(MN1)關閉，因此，該第一節點(N1)的電位會被拉升至第一高電位電壓(VDDH)，該第一節點(N1)的第一高電位電壓(VDDH)使得該第二PMOS電晶體(MP2)關閉，此時由於該第二NMOS電晶體(MN2)導通，該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都關閉(OFF)，因此，該第二節點(N2)的電位將維持在低電位(0伏特)的穩態值。質言之，第一信號(V(IN))為低電位(0伏特)時，經過具電晶體堆疊結構之電壓位準轉換器轉換成具低電位(0伏特)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Now consider the steady-state operation of a voltage level converter with a transistor stack structure when the first signal (V(IN)) is at a low potential (0 volts): the low potential on the first input terminal (IN) is simultaneously transmitted to the input of the first inverter (I1), the gate of the first NMOS transistor (MN1), and the gate of the third PMOS transistor (MP3), so that the first NMOS transistor (MN1) OFF, the third The PMOS transistor (MP3) is turned on, and the first inverter (I1) transmits a second high power supply voltage (VDDL) to the gates of the second NMOS transistor (MN2), the fourth PMOS transistor (MP4) The second NMOS transistor (MN2) is turned on and the fourth PMOS transistor (MP4) is turned off. At this time, since the second NMOS transistor (MN2) is turned on, the fourth PMOS transistor (MP4) is turned off. , therefore, the potential of the second node (N2) will be pulled down to a low potential (0 volts), and further, the low potential of the second node (N2) is transmitted to the first PMOS transistor (MP1) The gate of the first PMOS transistor (MP1) is turned on. Since both the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned on, the first NMOS transistor (MN1) is turned off. Therefore, the potential of the first node (N1) is pulled up to the first high potential voltage (VDDH), and the first high potential voltage (VDDH) of the first node (N1) makes the second PMOS transistor (MP2) ) is turned off. At this time, since the second NMOS transistor (MN2) is turned on, both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned off (OFF). Therefore, the second node (N2) ) will be maintained at a steady state value of low potential (0 volts). In other words, when the first signal (V(IN)) is at a low potential (0 volts), it is converted into a second signal (V( OUT)), output from the output terminal (OUT).

再考慮第一信號(V(IN))為第二高電位電壓(VDDL)時，具電晶體堆疊結構之電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的第二高電位電壓(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)的閘極以及該第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)導通(ON)、該第三PMOS電晶體(MP3)關閉(OFF)，此時由於該第一NMOS電晶體(MN1)導通(ON)，因此，該第一節點(N1)的電位會被拉降至一低電位(0伏特)，該第一節點(N1)上的低電位傳送到該第二PMOS 電晶體(MP2)的閘極，使得該第二PMOS電晶體(MP2)導通(ON)；而該第一反相器(I1)傳送一低電位到該第二NMOS電晶體(MN2)和該第四PMOS電晶體(MP4)的閘極，使得該第二NMOS電晶體(MN2)關閉(OFF)、該第四PMOS電晶體(MP4)導通(ON)，此時由於該第二PMOS電晶體(MP2)和該第四PMOS電晶體(MP4)都導通(ON)，而該第二NMOS電晶體(MN2)關閉(OFF)，該第二節點(N2)的電位會被拉升至一高電位；而該第二節點(N2)的高電位使得該第一PMOS電晶體(MP1)關閉(OFF)，此時由於該第一NMOS電晶體(MN1)導通(ON)，該第一PMOS電晶體(MP1)和該第三PMOS電晶體(MP3)都關閉(OFF)，該第一節點(N1)的電位會維持在低電位(0伏特)，而該第二節點(N2)的電位將維持在第一高電位電壓(VDDH)，因此，該輸出端(OUT)的電位會被拉升至一第一高電位電壓(VDDH)的穩態值。質言之，第一信號(V(IN))為第二高電位電壓(VDDL)時，經過具電晶體堆疊結構之電壓位準轉換器轉換成具第一高電位電壓(VDDH)的第二信號(V(OUT))，由輸出端(OUT)輸出。 Then consider the steady-state operation of the voltage level converter with the transistor stack structure when the first signal (V(IN)) is the second high potential voltage (VDDL): the second on the first input terminal (IN) A high potential voltage (VDDL) is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the gate of the third PMOS transistor (MP3), so that the The first NMOS transistor (MN1) is turned on (ON) and the third PMOS transistor (MP3) is turned off (OFF). At this time, since the first NMOS transistor (MN1) is turned on (ON), the first node The potential of (N1) is pulled down to a low potential (0 volts), and the low potential on the first node (N1) is transmitted to the second PMOS The gate of the transistor (MP2) makes the second PMOS transistor (MP2) conductive (ON); and the first inverter (I1) transmits a low potential to the second NMOS transistor (MN2) and the The gate of the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned off (OFF) and the fourth PMOS transistor (MP4) is turned on (ON). (MP2) and the fourth PMOS transistor (MP4) are both turned on (ON), and the second NMOS transistor (MN2) is turned off (OFF), the potential of the second node (N2) will be pulled to a high and the high potential of the second node (N2) makes the first PMOS transistor (MP1) off (OFF), at this time, because the first NMOS transistor (MN1) is turned on (ON), the first PMOS transistor (MP1) is turned on (ON), the first PMOS transistor (MP1) is turned off (OFF). The crystal (MP1) and the third PMOS transistor (MP3) are both turned off (OFF), the potential of the first node (N1) will be maintained at a low potential (0 volts), and the potential of the second node (N2) will be Maintained at the first high potential voltage (VDDH), therefore, the potential of the output terminal (OUT) will be pulled up to a steady state value of the first high potential voltage (VDDH). In other words, when the first signal (V(IN)) is the second high potential voltage (VDDL), it is converted into a second high potential voltage (VDDH) by a voltage level converter with a transistor stack structure. The signal (V(OUT)) is output from the output terminal (OUT).

綜上所述，第一信號(V(IN))為低電位(0伏特)時，第二信號(V(OUT))亦為低電位(0伏特)；而第一信號(V(IN))為第二高電位電壓(VDDL)時，第二信號(V(OUT))為第一高電位電壓(VDDH)。如此，電壓位準轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a low level (0 volts), the second signal (V(OUT)) is also at a low level (0 volts); and the first signal (V(IN) ) is the second high potential voltage (VDDL), the second signal (V(OUT)) is the first high potential voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

(II)待機模式(Standby mode) (II) Standby mode (Standby mode)

請再參考圖3。在待機狀態下，亦即，當該致能控制端(EN)是在低電位(0伏特)狀態時，該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)均呈導通(ON)狀態，此時，該具電晶體堆疊結構之電壓位準轉換器停止動作。因此，任何第一信號(V(IN))的輸入均不會影響到已被栓鎖住的第二信號(V(OUT))值。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential (0 volt) state, the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are both turned on (ON) state, at this time, the voltage level converter with the transistor stack structure stops working. Therefore, any input of the first signal (V(IN)) will not affect the latched second signal number (V(OUT)) value. Its working principle is not repeated here.

本創作所提出之具電晶體堆疊結構之電壓位準轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之具電晶體堆疊結構之電壓位準轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 Figure 4 shows the simulation result of Spice transient analysis of the voltage level converter with the transistor stack structure proposed in this work. The level converter can not only convert the first signal into a second signal quickly and accurately, but also can effectively reduce the power consumption.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included in the scope of the patent application of this creation.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:模式控制開關 3: Mode control switch

EN:致能控制端 EN: Enable control terminal

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

OUT:輸出端 OUT: output terminal

GND:地 GND: ground

V(OUT):第二信號 V(OUT): Second signal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

I1:第一反相器 I1: first inverter

Claims

一種具電晶體堆疊結構之電壓位準轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括： A voltage level converter with a transistor stack structure for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising:

一第一節點(N1)，用以將一第二PMOS電晶體(MP2)的閘極、一第三PMOS電晶體(MP3)的汲極以及一第五PMOS電晶體(MP5)的源極連接在一起； A first node (N1) for connecting the gate of a second PMOS transistor (MP2), the drain of a third PMOS transistor (MP3) and the source of a fifth PMOS transistor (MP5) together;

一第二節點(N2)，用以將一第一PMOS電晶體(MP1)的閘極、一第四PMOS電晶體(MP4)的汲極以及一第六PMOS電晶體(MP6)的源極連接在一起； A second node (N2) for connecting the gate of a first PMOS transistor (MP1), the drain of a fourth PMOS transistor (MP4) and the source of a sixth PMOS transistor (MP6) together;

一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)的閘極、一第一NMOS電晶體(MN1)的閘極以及一第一反相器(I1)的輸入端，用以提供一第一信號(V(IN))； A first input terminal (IN) coupled to the gate of the third PMOS transistor (MP3), the gate of a first NMOS transistor (MN1) and the input terminal of a first inverter (I1) , for providing a first signal (V(IN));

一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)的閘極、一第二NMOS電晶體(MN2)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號； A second input terminal (INB) coupled to the gate of the fourth PMOS transistor (MP4), the gate of a second NMOS transistor (MN2) and the output terminal of the first inverter (I1) , for providing the inverted signal of the first signal (V(IN));

一致能控制端(EN)，用以提供一致能信號； The unanimous control terminal (EN) is used to provide the unanimous signal;

一輸出端(OUT)，耦接於該第二節點(N2)，用以輸出該第二信號(V(OUT))； an output terminal (OUT) coupled to the second node (N2) for outputting the second signal (V(OUT));

一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)以及該第二PMOS電晶體(MP2)的源極，用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第一高電位電壓； A first high power supply voltage (VDDH) coupled to the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) for providing the voltage level of the transistor stack structure the first high potential voltage required by the converter;

一第二高電源供應電壓(VDDL)，用以提供該具電晶體堆疊結構之電壓位準轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位； A second high power supply voltage (VDDL) is used to provide a second high potential voltage required by the voltage level converter with the transistor stack structure, and the potential of the second high power supply voltage (VDDL) is lower than that of the the potential of the first high power supply voltage (VDDH);

一輸入電路(1)，耦接於該第一輸入端(IN)，用來提供差動輸入信號； an input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal;

一栓鎖電路(2)，耦接於該第一高電源供應電壓(VDDH)，用來保存轉換的輸出電位並且控制漏電流；以及 a latch circuit (2), coupled to the first high power supply voltage (VDDH), for preserving the converted output potential and controlling leakage current; and

一模式控制開關(3)，用以控制該具電晶體堆疊結構之電壓位準轉換器之不同操作模式。 A mode control switch (3) is used for controlling different operation modes of the voltage level converter with the transistor stack structure.

如申請專利範圍第1項所述的具電晶體堆疊結構之電壓位準轉換器，其中輸入電路(1)包括： The voltage level converter with a transistor stack structure as described in claim 1, wherein the input circuit (1) comprises:

一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接； a first NMOS transistor (MN1), its source is connected to ground (GND), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1);

一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；以及 a second NMOS transistor (MN2), its source is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); as well as

一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)) and providing a connection with the first signal (V(IN)) inverted signal.

如申請專利範圍第2項所述的具電晶體堆疊結構之電壓位準轉換器，其中該栓鎖電路(2)包括： The voltage level converter with a transistor stack structure as described in item 2 of the claimed scope, wherein the latch circuit (2) comprises:

一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第三PMOS電晶體(MP3)的源極相連接； A first PMOS transistor (MP1), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the third PMOS transistor The source of the crystal (MP3) is connected;

一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第四PMOS電晶體(MP4)的源極相連接； A second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the fourth PMOS transistor The source of the crystal (MP4) is connected;

一第三PMOS電晶體(MP3)，其源極連接至該第一PMOS電晶體(MP1)的汲極，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及 A third PMOS transistor (MP3), whose source is connected to the drain of the first PMOS transistor (MP1), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first PMOS transistor (MP1) a node (N1) is connected; and

一第四PMOS電晶體(MP4)，其源極連接至該第二PMOS電晶體(MP2)的汲極，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。 A fourth PMOS transistor (MP4), whose source is connected to the drain of the second PMOS transistor (MP2), whose gate is connected to the second input terminal (INB), and whose drain is connected to the first Two nodes (N2) are connected.

如申請專利範圍第3項所述的具電晶體堆疊結構之電壓位準轉換器，其中該模式控制開關(3)包括： The voltage-level converter with a transistor stack structure as described in claim 3, wherein the mode control switch (3) comprises:

一第五PMOS電晶體(MP5)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第一節點(N1)相連接； A fifth PMOS transistor (MP5), the source of which is connected to the first high power supply voltage (VDDH), and the gate of which is connected to the gate of the sixth PMOS transistor (MP6) and connected to the enable a control terminal (EN), and its drain is connected to the first node (N1);

一第六PMOS電晶體(MP6)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第二節點(N2)相連接；以及 A sixth PMOS transistor (MP6), the source of which is connected to the first high power supply voltage (VDDH), and the gate of which is connected to the gate of the fifth PMOS transistor (MP5) and connected to the enable a control terminal (EN) with its drain connected to the second node (N2); and

一致能控制端(EN)，耦接於該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號。 An enable control terminal (EN) is coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) for providing an enable signal.

如申請專利範圍第2項所述的具電晶體堆疊結構之電壓位準轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The voltage level converter with a transistor stack structure as described in claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

如申請專利範圍第1項所述的具電晶體堆疊結構之電壓位準轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The voltage level converter with a transistor stack structure as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). between.

如申請專利範圍第6項所述的具電晶體堆疊結構之電壓位準轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The voltage level converter with a transistor stack structure as described in claim 6, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH) between.