TWM599059U

TWM599059U - Voltage level shifter having output buffer circuit

Info

Publication number: TWM599059U
Application number: TW109201853U
Authority: TW
Inventors: 余建政; 李泓頡; 阮禮皓; 林宗毅
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2020-02-20
Filing date: 2020-02-20
Publication date: 2020-07-21

Abstract

本創作提出一種具輸出緩衝電路之電位轉換器，其係由一由一輸入電路(1)、一栓鎖電路(2)以及一輸出緩衝電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號；而該輸出緩衝電路(3)係用以抑制輸出電位的競爭並輸出該第二信號(V(OUT))。 This creation proposes a potential converter with an output buffer circuit, which is composed of an input circuit (1), a latch circuit (2) and an output buffer circuit (3), wherein the input circuit (1) ) Is used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); and the output buffer circuit (3) is used to suppress the output potential competition And output the second signal (V(OUT)).

本創作所提出之具輸出緩衝電路之電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 The potential converter with output buffer circuit proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device, and it is also effective The ground suppresses the competition between the pull-up path and the pull-down path, thereby reducing power loss.

Description

具輸出緩衝電路之電位轉換器 Potential converter with output buffer circuit

本創作提出一種具輸出緩衝電路之電位轉換器，尤指一由一輸入電路(1)、一栓鎖電路(2)以及一輸出緩衝電路(3)所組成，以求獲得精確電壓位準轉換同時亦能有效降低功率損耗之電子電路。 This creation proposes a potential converter with an output buffer circuit, especially one composed of an input circuit (1), a latch circuit (2) and an output buffer circuit (3), in order to obtain accurate voltage level conversion At the same time, it can effectively reduce the power loss of the electronic circuit.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signals between different integrated circuits (IC). In many applications, when the application system needs to transmit signals from the core logic with a lower voltage level to peripheral devices with a higher voltage level, the potential converter is responsible for converting the low-voltage working signal into a high-voltage working signal.

第1圖係顯示另一先前技藝(prior art)之一鏡像型電位轉換器電路，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電位轉換器的性能也不會有太大的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 1 shows another prior art mirror-type potential converter circuit by connecting the gates of a first PMOS transistor (MP1) and a second PMOS transistor (MP2) Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, and the first PMOS transistor (MP1) is in the The saturation region and its gate voltage make the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high power supply voltage (VDDH) changes, the potential The performance of the converter will not be too Big change. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

第2圖係顯示一先前技藝之一閂鎖型電位轉換器電路，其係使用一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS 電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 2 shows a latch-type potential converter circuit of the prior art, which uses a first PMOS transistor (MP1), a second PMOS transistor (MP2), and a first NMOS transistor (MN1) , A second NMOS transistor (MN2) and an inverter (INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second high power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V(IN)) is also between the ground (GND) and the second high power supply voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output through the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on (ON). In addition, due to the cross-coupled method of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potential converter. In particular, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so as to pull up the gate potential of the second PMOS transistor (MP2) and turn off the second PMOS transistor (MP2); furthermore, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the second PMOS The gate potential of the transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the gate potential of the first PMOS transistor (MP1) is pulled up to turn off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) is close to turning on (or off) and the second NMOS transistor (MN2) is close to turning off (or on), the output terminal There is a contention phenomenon between the pull-up and pull-down of the potential on the (OUT), so the second signal (V(OUT)) is slower when it changes to a low potential. In addition, consider that when the first signal (V(IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion period may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), The first NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current (static) between the first high power supply voltage (VDDH) and ground (GND). current), this quiescent current will increase power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。 Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The first high power supply voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type level converter operate normally is limited. When the second PMOS transistor (MP2) tends to be on (or off) and in When the second NMOS transistor (MN2) is close to turning off (or on), there is a contention phenomenon for the rise and fall of the potential on the output terminal (OUT), so the second signal (V (OUT)) The speed is slow when changing to a low potential.

有鑑於此，本創作之主要目的係提出一種具輸出緩衝電路之電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 In view of this, the main purpose of this creation is to propose a potential converter with an output buffer circuit, which can not only accurately and quickly convert the first signal to a second signal, but also effectively reduce the pull-up path and the pull-down path Compete with each other, thereby reducing power loss.

本創作提出一種具輸出緩衝電路之電位轉換器，其係由一輸入電路(1)、一栓鎖電路(2)以及一輸出緩衝電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號；而該輸出緩衝電路(3)係用以抑制輸出電位的競爭並輸出該第二信號(V(OUT))。 This creation proposes a potential converter with an output buffer circuit, which is composed of an input circuit (1), a latch circuit (2), and an output buffer circuit (3), wherein the input circuit (1) is Used to provide a differential input signal; the latch circuit (2) is used to save the differential input signal from the input circuit (1); and the output buffer circuit (3) is used to suppress the output potential competition and output The second signal (V(OUT)).

由模擬結果證實，本創作所提出之具輸出緩衝電路之電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results confirm that the potential converter with output buffer circuit proposed in this creation not only can accurately and quickly convert the first signal to a second signal, but also has a simple circuit structure and is beneficial to the miniaturization of the device. Multiple functions can effectively reduce power loss at the same time.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latching circuit

3:輸出緩衝電路 3: Output buffer circuit

GND:地 GND: ground

I1:第一反相器 I1: First inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: third node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: second PMOS transistor

MP3:第三PMOS電晶體 MP3: third PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: Fourth NMOS transistor

OUT:輸出端 OUT: output terminal

IN:第一輸入端 IN: the first input

V(OUT):第二信號 V(OUT): second signal

INB:第二輸入端 INB: second input

V(IN):第一信號 V(IN): first signal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

第1圖係顯示第一先前技藝中電位轉換器之電路圖； Figure 1 is a circuit diagram showing the potential converter in the first prior art;

第2圖係顯示第二先前技藝中電位轉換器之電路圖； Figure 2 is a circuit diagram showing the potential converter in the second prior art;

第3圖係顯示本創作較佳實施例之具輸出緩衝電路之電位轉換器之電路圖； Figure 3 is a circuit diagram showing a potential converter with an output buffer circuit in a preferred embodiment of the invention;

第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； Figure 4 is a timing diagram showing the transient analysis of the first signal and the second signal of the preferred embodiment of this creation;

根據上述之目的，本創作提出一種具輸出緩衝電路之電位轉換器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)以及一輸出緩衝電路(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用以保存來自該輸入電路(1)的差動輸入信號；而該輸出緩衝電路(3)係用以抑制輸出電位的競爭並輸出該第二信號(V(OUT))；該輸入電路(1)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係由一第一PMOS電晶體(MP1)以及一第二PMOS電晶體(MP2)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接；該輸出緩衝電路(3)係由一第三PMOS電晶體(MP3)、一第三NMOS電晶體(MN3)以及一第四NMOS 電晶體(MN4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第三NMOS電晶體(MN3)的汲極相連接；該第三NMOS電晶體(MN3)的源極連接至該第三節點(N3)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三PMOS電晶體(MP3)的汲極相連接；該第四NMOS電晶體(MN4)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第三節點(N3)相連接；該第一高電源供應電壓(VDDH)係用以提供該具輸出緩衝電路之電位轉換器所需之第一高電源電壓；該第二高電源供應電壓(VDDL)係用以提供該具輸出緩衝電路之電位轉換器所需之第二高電源電壓；該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準；該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above-mentioned purpose, this creation proposes a potential converter with an output buffer circuit, as shown in Figure 3, which consists of an input circuit (1), a latch circuit (2) and an output buffer circuit (3) The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to store the differential input signal from the input circuit (1); and the output buffer circuit ( 3) It is used to suppress the competition of the output potential and output the second signal (V(OUT)); the input circuit (1) consists of a first NMOS transistor (MN1) and a second NMOS transistor (MN2) And a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input (IN), and its The drain is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate is connected to the second input (INB), and the drain is The pole is connected to the second node (N2); the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V(IN)), and Provide a signal that is inverse to the first signal (V(IN)); the latch circuit (2) is composed of a first PMOS transistor (MP1) and a second PMOS transistor (MP2), wherein , The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node ( N1) is connected; the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the The second node (N2) is connected; the output buffer circuit (3) is composed of a third PMOS transistor (MP3), a third NMOS transistor (MN3) and a fourth NMOS The source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), the gate of the third PMOS transistor (MP3) is connected to the first node (N1), and the The drain is connected to the drain of the third NMOS transistor (MN3); the source of the third NMOS transistor (MN3) is connected to the third node (N3), and its gate is connected to the first input Terminal (IN), and its drain is connected to the drain of the third PMOS transistor (MP3); the source of the fourth NMOS transistor (MN4) is connected to ground (GND), and its gate is connected to The second input terminal (INB), and its drain is connected to the third node (N3); the first high power supply voltage (VDDH) is used to provide the potential converter with an output buffer circuit The first high power supply voltage; the second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the level converter with an output buffer circuit; the second high power supply voltage (VDDL) The level is less than the level of the first high power supply voltage (VDDH); the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is between 0 volts and 1.8 volts The corresponding waveform of the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, and the first signal (V(IN)) is between 0 volts and 1.2 For a rectangular wave between volts, the second signal (V(OUT)) has a corresponding waveform between 0 volt and 1.8 volt.

請再參閱第3圖，現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，具輸出緩衝電路之電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第三NMOS電晶體(MN3)的閘極，使得該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都截止(OFF)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第二NMOS電晶體(MN2)以及該第四NMOS電晶體 (MN4)的閘極，使得該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通(ON)，此時，由於該第一NMOS電晶體(MN1)截止(OFF)，而該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都導通(ON)，該第二節點(N2)和該第三節點(N3)的電位會被拉降至一邏輯低位準(0伏特)，而該第二節點(N2)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通(ON)，此時由於該第一PMOS電晶體(MP1)導通(ON)，而該第一NMOS電晶體(MN1)截止(OFF)，因此，該第一節點(N1)的電位會被拉升至一邏輯高位準，該第一節點(N1)的邏輯高位準使得該第二PMOS電晶體(MP2)和該第三PMOS電晶體(MP3)都截止(OFF)，此時由於該第三PMOS電晶體(MP3)和該第三NMOS電晶體(MN3)都截止(OFF)，而該第四NMOS電晶體(MN4)導通(ON)，因此，該輸出端(OUT)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過具輸出緩衝電路之電位轉換器轉換成具邏輯低位準(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to Figure 3 again. Now consider the steady-state operation of a potential converter with an output buffer circuit when the first signal (V(IN)) is at a logic low level (0 volts): on the first input (IN) The logic low level of is simultaneously transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the third NMOS transistor (MN3), so that the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both turned off (OFF), and the first inverter (I1) transmits a logic high level (VDDL) to the second NMOS transistor (MN2) and the fourth NMOS transistor The gate of (MN4) makes both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) turn on (ON). At this time, the first NMOS transistor (MN1) is turned off (OFF). , And the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on (ON), the potential of the second node (N2) and the third node (N3) will be pulled down to one The logic low level (0V), and the logic low level on the second node (N2) is transferred to the gate of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) is turned on (ON) At this time, since the first PMOS transistor (MP1) is turned on (ON) and the first NMOS transistor (MN1) is turned off (OFF), the potential of the first node (N1) will be pulled up to a The logic high level of the first node (N1) makes the second PMOS transistor (MP2) and the third PMOS transistor (MP3) both turn off (OFF). At this time, the third PMOS transistor (MP3) and the third NMOS transistor (MN3) are both turned off (OFF), and the fourth NMOS transistor (MN4) is turned on (ON), therefore, the potential of the output terminal (OUT) will be maintained at a logic low level Quasi (0 volt) steady state value. In a nutshell, when the first signal (V(IN)) is at a logic low level (0 volts), it is converted into a second signal with a logic low level (0 volts) through the potential converter with an output buffer circuit. (OUT) output.

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，具輸出緩衝電路之電位轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準同時傳送到該第一反相器(I1)的輸入端、該第一NMOS電晶體(MN1)以及該第三NMOS電晶體(MN3)的閘極，使得該第一NMOS電晶體(MN1)和該第三NMOS電晶體(MN3)都導通(ON)，而該第一反相器(I1)傳送邏輯低位準到該第二NMOS電晶體(MN2)以及該第四NMOS電晶體(MN4)的閘極，使得該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都截止(OFF)，此時，由於該第一NMOS電晶體(MN1)導通(ON)，而該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都截止(OFF)，該第一節點(N1)的電位會被拉降至一邏輯低位準(0伏特)，該第一節點(N1)的邏輯低位準使得該第二PMOS電晶體(MP2)和該第三PMOS電晶體(MP3)都導通(ON)，此時由於該第二NMOS電晶體(MN2)和該第四NMOS電晶體(MN4)都截止(OFF)，該第二節點(N2)的電位會被拉升至一邏輯高位準，而該第二節點(N2)上的邏輯高位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)截止(OFF)，此時由於該第一PMOS電晶體(MP1)截止(OFF)，而該第一NMOS電晶體(MN1)導通(ON)，因此，該第一節點(N1)的電位會維持在一邏輯低位準，再者，由於該第三PMOS電晶體(MP3)和該第三NMOS電晶體(MN3)都導通(ON)，而該第四NMOS電晶體(MN4)截止(OFF)，因此，輸出端(OUT)的電位會維持在一邏輯高位準的穩態值。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過具輸出緩衝電路之電位轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 When the first signal (V(IN)) is at the logic high level (VDDL), the steady-state operation of the potential converter with the output buffer circuit: the logic high level on the first input (IN) is simultaneously transmitted to the The input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1) and the third NMOS transistor (MN3) make the first NMOS transistor (MN1) and the third NMOS transistor The transistors (MN3) are all turned on (ON), and the first inverter (I1) transmits a logic low level to the gates of the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4), so that The second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off (OFF). At this time, since the first NMOS transistor (MN1) is turned on (ON), the second NMOS transistor (MN2) and the The fourth NMOS transistor (MN4) is turned off (OFF), the potential of the first node (N1) will be pulled down to a logic low level (0 volts), and the logic low level of the first node (N1) makes the The second PMOS transistor (MP2) and the third PMOS transistor (MP3) are both turned on (ON). At this time, the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned off (OFF). ), the potential of the second node (N2) will be pulled up to a logic high level, and the logic high level on the second node (N2) is transferred to the gate of the first PMOS transistor (MP1), so that The first PMOS transistor (MP1) is turned off (OFF). At this time, because the first PMOS transistor (MP1) is turned off (OFF) and the first NMOS transistor (MN1) is turned on (ON), the first PMOS transistor (MP1) is turned on (ON). The potential of a node (N1) will be maintained at a logic low level. Furthermore, since the third PMOS transistor (MP3) and the third NMOS transistor (MN3) are both turned on (ON), and the fourth NMOS transistor The crystal (MN4) is turned off (OFF), so the potential of the output terminal (OUT) will maintain a steady-state value at a logic high level. In a nutshell, when the first signal (V(IN)) is at a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by the level converter with the output buffer circuit. Output terminal (OUT) output.

綜上所述，該第一信號(V(IN))為邏輯低位準(0伏特)時，該第二信號(V(OUT))亦為邏輯低位準(0伏特)；而該第一信號(V(IN))為邏輯高位準(VDDL)時，該第二信號(V(OUT))為第一高電源供應電壓(VDDH)。如此，電壓位準轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a logic low level (0 volt), the second signal (V(OUT)) is also at a logic low level (0 volt); and the first signal When (V(IN)) is the logic high level (VDDL), the second signal (V(OUT)) is the first high power supply voltage (VDDH). In this way, the purpose of voltage level conversion is achieved.

本創作所提出之具輸出緩衝電路之電位轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之具輸出緩衝電路之電位轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且可有效地減少輸出端(OUT)的上拉路徑與下拉路徑之間的互相競爭，進而降低功率損耗。 The Spice transient analysis simulation results of the potential converter with output buffer circuit proposed in this creation are shown in Figure 4. The simulation results can confirm that the potential converter with output buffer circuit proposed in this creation has Not only can the first signal be converted into a second signal quickly and accurately, but also the competition between the pull-up path and the pull-down path of the output terminal (OUT) can be effectively reduced, thereby reducing power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although this creation specifically discloses and describes the selected best embodiment, anyone familiar with the technology can understand that any possible changes in form or details do not depart from the spirit and scope of this creation. Therefore, all changes within the scope of related technologies are included in the scope of patent application for this creation.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latching circuit

3:輸出緩衝電路 3: Output buffer circuit

GND:地 GND: ground

I1:第一反相器 I1: First inverter

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: third node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: second PMOS transistor

MP3:第三PMOS電晶體 MP3: third PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

MN3:第三NMOS電晶體 MN3: The third NMOS transistor

MN4:第四NMOS電晶體 MN4: Fourth NMOS transistor

OUT:輸出端 OUT: output terminal

IN:第一輸入端 IN: the first input

V(OUT):第二信號 V(OUT): second signal

INB:第二輸入端 INB: second input

V(IN):第一信號 V(IN): first signal

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

Claims

一種具輸出緩衝電路之電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括： A potential converter with an output buffer circuit for converting a first signal (V(IN)) into a second signal (V(OUT)), which includes:

一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第二PMOS電晶體(MP2)的閘極以及一第一NMOS電晶體(MN1)的汲極連接在一起； A first node (N1) for connecting the drain of a first PMOS transistor (MP1), the gate of a second PMOS transistor (MP2) and the drain of a first NMOS transistor (MN1) Together

一第二節點(N2)，用以將該第一PMOS電晶體(MP1)的閘極、該第二PMOS電晶體(MP2)的汲極以及一第二NMOS電晶體(MN2)的汲極連接在一起； A second node (N2) for connecting the gate of the first PMOS transistor (MP1), the drain of the second PMOS transistor (MP2) and the drain of a second NMOS transistor (MN2) Together

一第三節點(N3)，用以將一第三NMOS電晶體(MN3)的源極以及一第四NMOS電晶體(MN4)的汲極連接在一起； A third node (N3) for connecting the source of a third NMOS transistor (MN3) and the drain of a fourth NMOS transistor (MN4) together;

一第一輸入端(IN)，耦接於該第一NMOS電晶體(MN1)以及該第三NMOS電晶體(MN3)的閘極，用以提供該第一信號(V(IN))； A first input terminal (IN), coupled to the gates of the first NMOS transistor (MN1) and the third NMOS transistor (MN3), for providing the first signal (V(IN));

一第二輸入端(INB)，耦接於該第二NMOS電晶體(MN2)以及該第四NMOS電晶體(MN4)的閘極，用以提供該第一信號(V(IN))的反相信號； A second input terminal (INB) is coupled to the gate of the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) to provide the inverse of the first signal (V(IN)) Phase signal

一輸出端(OUT)，耦接於該第三節點(N3)，用以輸出該第二信號(V(OUT))； An output terminal (OUT), coupled to the third node (N3), for outputting the second signal (V(OUT));

一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)以及該第三PMOS電晶體(MP3)的源極，用以提供該電位轉換器所需之第一高電源電壓； A first high power supply voltage (VDDH), coupled to the source of the first PMOS transistor (MP1), the second PMOS transistor (MP2), and the third PMOS transistor (MP3) to provide The first high power supply voltage required by the level converter;

一第二高電源供應電壓(VDDL)，用以提供該電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位； A second high power supply voltage (VDDL) is used to provide the second high power supply voltage required by the level converter. The second high power supply voltage (VDDL) has a lower potential than the first high power supply voltage (VDDH). ) Of potential;

一輸入電路(1)，耦接於該第一輸入端(IN)，用來提供差動輸入信號； An input circuit (1), coupled to the first input terminal (IN), for providing a differential input signal;

一栓鎖電路(2)，耦接於該第一高電源供應電壓(VDDH)以及該輸入電路(1)，用來保存來自該輸入電路(1)的差動輸入信號；以及 A latch circuit (2), coupled to the first high power supply voltage (VDDH) and the input circuit (1), for storing the differential input signal from the input circuit (1); and

一輸出緩衝電路(3)，用以抑制輸出電位的競爭並輸出該第二信號(V(OUT))。 An output buffer circuit (3) is used to suppress the competition of the output potential and output the second signal (V(OUT)).

如申請專利範圍第1項所述的具輸出緩衝電路之電位轉換器，其中該輸入電路(1)包括： The potential converter with output buffer circuit as described in item 1 of the scope of patent application, wherein the input circuit (1) includes:

一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；以及 A first NMOS transistor (MN1), its source is connected to ground (GND), its gate is connected to the first input (IN), and its drain is connected to the first node (N1); A second NMOS transistor (MN2) whose source is connected to ground (GND), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2); as well as

一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 A first inverter (I1), coupled to the first input terminal (IN), for receiving the first signal (V(IN)), and providing a signal with the first signal (V(IN)) Inverted signal.

如申請專利範圍第2項所述的具輸出緩衝電路之電位轉換器，其中該栓鎖電路(2)包括： The potential converter with output buffer circuit as described in item 2 of the scope of patent application, wherein the latch circuit (2) includes:

一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；以及 A first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node ( N1) are connected; and

一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接。 A second PMOS transistor (MP2), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node ( N2) Connected.

如申請專利範圍第3項所述的具輸出緩衝電路之電位轉換器，其中該輸出緩衝電路(3)包括： The potential converter with output buffer circuit as described in item 3 of the scope of patent application, wherein the output buffer circuit (3) includes:

一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第三NMOS電晶體(MN3)的汲極相連接； A third PMOS transistor (MP3) whose source is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the third NMOS transistor The drain of the crystal (MN3) is connected;

一第三NMOS電晶體(MN3)，其源極連接至該第三節點(N3)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三PMOS電晶體(MP3)的汲極相連接；以及 A third NMOS transistor (MN3) whose source is connected to the third node (N3), its gate is connected to the first input terminal (IN), and its drain is connected to the third PMOS transistor ( MP3) is connected to the drain; and

一第四NMOS電晶體(MN4)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第三節點(N3)相連接。 A fourth NMOS transistor (MN4) has its source connected to ground (GND), its gate connected to the second input terminal (INB), and its drain connected to the third node (N3).

如申請專利範圍第1項所述的具輸出緩衝電路之電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The potential converter with an output buffer circuit as described in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volt and the second high power supply voltage (VDDL).

如申請專利範圍第5項所述的具輸出緩衝電路之電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The potential converter with output buffer circuit as described in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volt and the first high power supply voltage (VDDH).

如申請專利範圍第6項所述的具輸出緩衝電路之電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The potential converter with an output buffer circuit as described in item 6 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).