TWM629687U - High performance voltage level shifter - Google Patents

High performance voltage level shifter Download PDF

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TWM629687U
TWM629687U TW110213181U TW110213181U TWM629687U TW M629687 U TWM629687 U TW M629687U TW 110213181 U TW110213181 U TW 110213181U TW 110213181 U TW110213181 U TW 110213181U TW M629687 U TWM629687 U TW M629687U
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pmos transistor
node
gate
signal
drain
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TW110213181U
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Chinese (zh)
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余建政
賴永瑄
邱崑霖
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修平學校財團法人修平科技大學
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Abstract

本創作提出一種高效能電壓位準移位器，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)用來提供差動輸入信號；該栓鎖電路(2)用來保存並且抑制輸出電位的競爭現象；該模式控制開關(3)用以控制該電壓位準移位器之不同操作模式。 The present invention proposes a high-performance voltage level shifter, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit (1) uses to provide a differential input signal; the latch circuit (2) is used to preserve and suppress the competition phenomenon of the output potential; the mode control switch (3) is used to control different operation modes of the voltage level shifter.

本創作所提出之高效能電壓位準移位器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效。 The high-performance voltage level shifter proposed in the present invention not only can accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and miniaturization of the device.

Description

高效能電壓位準移位器 High Performance Voltage Level Shifter

本創作提出一種高效能電壓位準移位器，尤指一由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，以求獲得精確電壓位準轉換之電子電路。 The present invention proposes a high-performance voltage level shifter, especially one composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), in order to obtain precise voltage level conversion of electronic circuits.

電壓位準移位器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準移位器就負責將低電壓工作信號轉換成高電壓工作信號。 A voltage level shifter is an electronic circuit used to communicate signals between different integrated circuits (Integrated Circuits, IC for short). In many applications, when the application system needs to transmit signals from core logic with a lower voltage level to peripheral devices with a higher voltage level, the voltage level shifter is responsible for converting the low-voltage operating signal to high-voltage operation. Signal.

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準移位器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電壓位準移位器電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因 此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準移位器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電壓位準移位器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 FIG. 1 shows a prior art latch-type voltage level shifter circuit using a first PMOS (P-channel metal oxide semiconductor) transistor ( MP1), a second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2) and an inverse an inverter (INV) to form a voltage level shifter circuit, wherein the bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and the ground (GND), and the first signal (V( The potential of IN)) is also between the ground (GND) and the second high potential voltage (VDDL). The first signal (V(IN)) and the inverted input voltage signal output by the inverter (INV) are respectively connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) . because Therefore, at the same time, only one of the first NMOS transistor ( MN1 ) and the second NMOS transistor ( MN2 ) is turned on (ON). In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level shifter is in a stable state, There is no static current generated in the latch-type voltage level shifter. Especially, when the first NMOS transistor (MN1) is turned off (OFF) and the second NMOS transistor (MN2) is turned on (ON), the gate potential of the first PMOS transistor (MP1) is pulled down and The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, thereby pulling up the first PMOS transistor (MP2). The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there is no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準移位器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1) 及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the above-mentioned conventional voltage level shifter, when the second PMOS transistor (MP2) is approaching to be turned on (or turned off) and the second NMOS transistor (MN2) is approached to be turned off (or turned on), There is a phenomenon of contention for the pull-up and pull-down of the potential on the output terminal (OUT), so the speed of the second signal (V(OUT)) is slower when it transitions to a low potential. Furthermore, consider that when the first signal (V(IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes a low potential, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high potential voltage (VDDH). However, since 0 volts cannot be converted to 1.8 volts instantaneously, the lower first signal (V(IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) And the second NMOS transistor (MN2) is fully turned on or completely off, which will cause a static current (static current) between the first high potential voltage (VDDH) and the ground (GND), which will increase the power loss.

再者，閂鎖型的電壓位準移位器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準移位器正常運作的第一高電位電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type voltage level shifter is affected by the first high potential voltage (VDDH), due to the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The electrode voltage is the first high potential voltage (VDDH), and the gate-source voltages of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are the second high potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch-type voltage level shifter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準移位器電路，該電壓位準移位器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電壓位準移位器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準移位器的性能也不會有太大的改變。因此，鏡像型的電壓位準移位器可以適用在各種輸出電壓電路。 FIG. 2 shows another prior art mirror-type voltage level shifter circuit. The voltage level shifter is realized by switching the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The poles are connected together and to the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in the saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal . Since the performance of the mirror-type voltage level shifter is determined by the currents of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high potential voltage (VDDH) changes , the performance of the voltage level shifter will not change much. Therefore, the mirror-type voltage level shifter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電 位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate voltages of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are The bit is pulled down so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are on. In this way, a static current path is created between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種高效能電壓位準移位器，其不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效。 In view of this, the main purpose of this creation is to provide a high-performance voltage level shifter, which can not only accurately and quickly convert a first signal into a second signal, but also has a simple circuit structure and is beneficial to the device. Multiple functions such as miniaturization.

本創作提出一種高效能電壓位準移位器，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用來保存並且抑制輸出電位的競爭現象；該模式控制開關(3)係用以控制該低功率電壓位準移位器之不同操作模式。 The present invention proposes a high-performance voltage level shifter, which is composed of an input circuit (1), a latch circuit (2) and a mode control switch (3), wherein the input circuit (1) is a used to provide differential input signal; the latch circuit (2) is used to preserve and suppress the competition phenomenon of output potential; the mode control switch (3) is used to control different operations of the low power voltage level shifter model.

由模擬結果證實，本創作所提出之高效能電壓位準移位器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效。 The simulation results confirm that the high-performance voltage level shifter proposed in this work can not only accurately and quickly convert the first signal into a second signal, but also has a simple circuit structure and is conducive to the miniaturization of the device, etc. Multiple effects.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:模式控制開關 3: Mode control switch

EN:致能控制端 EN: Enable control terminal

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MP7:第七PMOS電晶體 MP7: seventh PMOS transistor

MP8:第八PMOS電晶體 MP8: Eighth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

OUT:輸出端 OUT: output terminal

I1:第一反相器 I1: first inverter

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

V(OUT):第二信號 V(OUT): Second signal

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

第1圖 係顯示第一先前技藝中高效能電壓位準移位器之電路圖；第2圖 係顯示第二先前技藝中高效能電壓位準移位器之電路圖；第3圖 係顯示本創作較佳實施例之高效能電壓位準移位器之電路圖；第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； Fig. 1 shows the circuit diagram of the high-performance voltage level shifter in the first prior art; Fig. 2 shows the circuit diagram of the high-performance voltage level shifter in the second prior art; Fig. 3 shows the comparative example of the present invention The circuit diagram of the high-performance voltage level shifter of the preferred embodiment; FIG. 4 is a timing chart of transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種高效能電壓位準移位器，如第3圖所示，其係由一輸入電路(1)、一栓鎖電路(2)以及一模式控制開關(3)所組成，其中，該輸入電路(1)係用來提供差動輸入信號；該栓鎖電路(2)係用來保存並且抑制輸出電位的競爭現象；該模式控制開關(3)係用以控制該低功率電壓位準移位器之不同操作模式；該輸入電路(1)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則連接至該第三節點(N3)；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則連接至該第四節點(N4)；該第一反相器(I1)耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該栓鎖電路(2)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三PMOS電晶體(MP3)、一第四PMOS電晶體(MP4)、一第七PMOS電晶體(MP7)以及一第八PMOS電晶體(MP8)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第三PMOS電晶體(MP3)的源極連接至該 第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該第七PMOS電晶體(MP7)的源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第八PMOS電晶體(MP8)的源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該模式控制開關(3)係由一第五PMOS電晶體(MP5)、一第六PMOS電晶體(MP6)以及一致能控制端(EN)所組成，其中，該第五PMOS電晶體(MP5)的源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第三節點(N3)相連接；該第六PMOS電晶體(MP6)的源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第四節點(N4)相連接；該致能控制端(EN)係耦接於該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號；該第一高電源供應電壓(VDDH)係用以提供該低功率電壓位準移位器所需之第一高電位電壓；而該第二高電源供應電壓(VDDL)係用以提供該低功率電壓位準移位器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位，該第一高電 源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特；該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes a high-performance voltage level shifter, as shown in FIG. 3, which consists of an input circuit (1), a latch circuit (2) and a mode control switch (3) The input circuit (1) is used to provide a differential input signal; the latch circuit (2) is used to save and suppress the competition phenomenon of the output potential; the mode control switch (3) is used to control Different operating modes of the low power voltage level shifter; the input circuit (1) consists of a first NMOS transistor (MN1), a second NMOS transistor (MN2) and a first inverter (I1) ), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), the gate is connected to the first input terminal (IN), and the drain is connected to the third node (N3); the source of the second NMOS transistor (MN2) is connected to the ground (GND), the gate is connected to the second input terminal (INB), and the drain is connected to the fourth node (N4) ); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V(IN)) and provide a connection with the first signal (V(IN) ) inverted signal; the latch circuit (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor Crystal (MP4), a seventh PMOS transistor (MP7) and an eighth PMOS transistor (MP8), wherein the source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the source of the second PMOS transistor (MP2) is connected to the first High power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); the source of the third PMOS transistor (MP3) is connected to the A first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); the fourth PMOS transistor (MP4) The source is connected to the first high power supply voltage (VDDH), the gate is connected to the second input terminal (INB), and the drain is connected to the second node (N2); the seventh PMOS power The source of the crystal (MP7) is connected to the first node (N1), its gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); the eighth The source of the PMOS transistor (MP8) is connected to the second node (N2), its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); the The mode control switch (3) is composed of a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6) and an enable control terminal (EN), wherein the fifth PMOS transistor (MP5) is The source is connected to the first high power supply voltage (VDDH), the gate is connected to the gate of the sixth PMOS transistor (MP6) and is connected to the enable control terminal (EN), and the drain is connected to the third node (N3); the source of the sixth PMOS transistor (MP6) is connected to the first high power supply voltage (VDDH), and the gate of the sixth PMOS transistor (MP5) is connected to the gate of the fifth PMOS transistor (MP5). The gate is connected to the enabling control terminal (EN), and the drain is connected to the fourth node (N4); the enabling control terminal (EN) is coupled to the fifth PMOS transistor (MP5) and the gate of the sixth PMOS transistor (MP6) are used to provide an enable signal; the first high power supply voltage (VDDH) is used to provide the required low power voltage level shifter a first high potential voltage; and the second high power supply voltage (VDDL) is used to provide a second high potential voltage required by the low power voltage level shifter, and the second high power supply voltage (VDDL) is The potential is lower than the potential of the first high power supply voltage (VDDH), the first high power The source supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts; the first signal (V(IN)) is a rectangular wave between 0 volts and 1.2 volts. The two signals (V(OUT)) have corresponding waveforms between 0 volts and 1.8 volts.

請再參閱第3圖，茲依高效能電壓位準移位器之工作模式說明圖3之工作原理如下： Please refer to Figure 3 again to illustrate the working mode of the high-efficiency voltage level shifter. The working principle of Figure 3 is as follows:

(I)主動模式(Active mode) (I) Active mode

在主動模式下，亦即，當該致能控制端(EN)是在高電位狀態時，該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)均呈關閉(OFF)狀態。 In the active mode, that is, when the enable control terminal (EN) is in a high potential state, both the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are in an OFF state .

現在考慮第一信號(V(IN))為低電位(0伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的低電位同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)、第三PMOS電晶體(MP3)以及第七PMOS電晶體(MP7)的閘極，使得該第一NMOS電晶體(MN1)關閉、第三PMOS電晶體(MP3)和第七PMOS電晶體(MP7)都導通，而該第一反相器(I1)傳送第二高電位電壓(1.2伏特)到第二NMOS電晶體(MN2)、第四PMOS電晶體(MP4)以及第八PMOS電晶體(MP8)的閘極，使得第二NMOS電晶體(MN2)導通、第四PMOS電晶體(MP4)和第八PMOS電晶體(MP8)都關閉，此時，由於第二NMOS電晶體(MN2)導通，使得該第四節點(N4)的電位會被拉降至一低電位(0伏特)的值，該第四節點(N4)的低電位使得第一PMOS電晶體(MP1)導通，此時由於第一PMOS電晶體(MP1)、第三PMOS電晶體(MP3)和第七PMOS電晶體(MP7)都導通，而該第一NMOS電晶體(MN1)關閉，使得該第三節點(N3)的電位被拉升至一高電位，該第三節點(N3)的高電位使得第二PMOS電晶體 (MP2)關閉，此時，由於第一PMOS電晶體(MP1)、第三PMOS電晶體(MP3)和第七PMOS電晶體(MP7)都導通，第二PMOS電晶體(MP2)、第四PMOS電晶體(MP4)和第八PMOS電晶體(MP8)都關閉，而第一NMOS電晶體(MN1)關閉、第二NMOS電晶體(MN2)導通，因此，該第三節點(N3)的電位會被拉升至一第一高電位電壓(1.8伏特)，而該第四節點(N4)的電位將維持在低電位(0伏特)，因此，輸出端(OUT)的電位會被拉降至一低電位(0伏特)的穩態值。質言之，第一信號(V(IN))為低電位(0伏特)時，經過電位轉換器轉換成具低電位(0伏特)的第二信號，由輸出端(OUT)輸出。 Now consider the steady state operation of the potential converter when the first signal (V(IN)) is low (0 volts): the low potential on the first input (IN) is simultaneously transmitted to the first inverter (I1) ), the gates of the first NMOS transistor (MN1), the third PMOS transistor (MP3), and the seventh PMOS transistor (MP7), so that the first NMOS transistor (MN1) is turned off and the third PMOS transistor (MP7) is turned off. The transistor (MP3) and the seventh PMOS transistor (MP7) are both on, and the first inverter (I1) transmits the second high potential voltage (1.2 volts) to the second NMOS transistor (MN2), the fourth PMOS The gates of the transistor (MP4) and the eighth PMOS transistor (MP8), so that the second NMOS transistor (MN2) is turned on, and the fourth PMOS transistor (MP4) and the eighth PMOS transistor (MP8) are both turned off. When the second NMOS transistor (MN2) is turned on, the potential of the fourth node (N4) will be pulled down to a low potential (0 volts), and the low potential of the fourth node (N4) makes the fourth node (N4) low potential. A PMOS transistor (MP1) is turned on. At this time, since the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the seventh PMOS transistor (MP7) are all turned on, the first NMOS transistor (MN1) ) is turned off, so that the potential of the third node (N3) is pulled to a high potential, and the high potential of the third node (N3) causes the second PMOS transistor (MP2) is turned off, at this time, since the first PMOS transistor (MP1), the third PMOS transistor (MP3) and the seventh PMOS transistor (MP7) are all turned on, the second PMOS transistor (MP2), the fourth PMOS transistor (MP2), the fourth PMOS transistor The transistor (MP4) and the eighth PMOS transistor (MP8) are both turned off, while the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on. Therefore, the potential of the third node (N3) will be is pulled up to a first high potential voltage (1.8 volts), and the potential of the fourth node (N4) will remain at a low potential (0 volts), therefore, the potential of the output terminal (OUT) will be pulled down to a Steady state value at low potential (0 volts). In other words, when the first signal (V(IN)) is at a low potential (0 volt), it is converted into a second signal with a low potential (0 volt) through a potential converter, and is output from the output terminal (OUT).

再考慮第一信號(V(IN))為第二高電位電壓(1.2伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的第二高電位電壓(1.2伏特)同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)、第三PMOS電晶體(MP3)以及第七PMOS電晶體(MP7)的閘極，使得該第一NMOS電晶體(MN1)導通、第三PMOS電晶體(MP3)和第七PMOS電晶體(MP7)都關閉，使得該第三節點(N3)的電位會被拉降至一低電位(0伏特)的值，而該第一反相器(I1)傳送低電位到第二NMOS電晶體(MN2)、第四PMOS電晶體(MP4)以及第八PMOS電晶體(MP8)的閘極，使得第二NMOS電晶體(MN2)關閉、第四PMOS電晶體(MP4)和第八PMOS電晶體(MP8)都導通，該第三節點(N3)的低電位使得第二PMOS電晶體(MP2)導通，此時由於第二PMOS電晶體(MP2)、第四PMOS電晶體(MP4)和第八PMOS電晶體(MP8)都導通，而第二NMOS電晶體(MN2)關閉，使得該第四節點(N4)的電位被拉升至一高電位，該第四節點(N4)的高電位使得第一PMOS電晶體(MP1)關閉，此時，由於第一PMOS電晶體(MP1)、第三PMOS電晶體(MP3)和第七PMOS電晶體(MP7)都關閉， 第二PMOS電晶體(MP2)、第四PMOS電晶體(MP4)和第八PMOS電晶體(MP8)都導通，而第一NMOS電晶體(MN1)導通、第二NMOS電晶體(MN2)關閉，因此，該第四節點(N4)的電位會被拉升至一第一高電位電壓(1.8伏特)，而該第三節點(N3)的電位將維持在低電位(0伏特)，因此，輸出端(OUT)的電位會被拉升至一第一高電位電壓(1.8伏特)的穩態值。質言之，第一信號(V(IN))為第二高電位電壓(1.2伏特)時，經過電位轉換器轉換成具第一高電位電壓(1.8伏特)的第二信號，由輸出端(OUT)輸出。 Then consider the steady state operation of the potential converter when the first signal (V(IN)) is the second high potential voltage (1.2 volts): the second high potential voltage (1.2 volts) on the first input terminal (IN) At the same time, it is transmitted to the input terminal of the first inverter (I1), the gate of the first NMOS transistor (MN1), the third PMOS transistor (MP3) and the seventh PMOS transistor (MP7), so that the first NMOS transistor (MP7) The transistor (MN1) is turned on, the third PMOS transistor (MP3) and the seventh PMOS transistor (MP7) are both turned off, so that the potential of the third node (N3) will be pulled down to a low potential (0 volts). value, and the first inverter (I1) transmits a low potential to the gates of the second NMOS transistor (MN2), the fourth PMOS transistor (MP4) and the eighth PMOS transistor (MP8), so that the second NMOS transistor (MP4) The transistor (MN2) is turned off, the fourth PMOS transistor (MP4) and the eighth PMOS transistor (MP8) are both turned on, the low potential of the third node (N3) makes the second PMOS transistor (MP2) turn on, at this time Since the second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the eighth PMOS transistor (MP8) are all turned on, and the second NMOS transistor (MN2) is turned off, the fourth node (N4) is turned off. The potential is pulled up to a high potential, and the high potential of the fourth node (N4) turns off the first PMOS transistor (MP1). ) and the seventh PMOS transistor (MP7) are both off, The second PMOS transistor (MP2), the fourth PMOS transistor (MP4) and the eighth PMOS transistor (MP8) are all turned on, while the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, Therefore, the potential of the fourth node (N4) will be pulled up to a first high potential voltage (1.8 volts), and the potential of the third node (N3) will be maintained at a low potential (0 volts), therefore, the output The potential of the terminal (OUT) is pulled up to a steady state value of a first high potential voltage (1.8 volts). In other words, when the first signal (V(IN)) is the second high-potential voltage (1.2V), it is converted into a second signal with the first high-potential voltage (1.8V) through the potential converter, and the output terminal ( OUT) output.

綜上所述，第一信號(V(IN))為低電位(0伏特)時，第二信號(V(OUT))亦為低電位(0伏特)；而第一信號(V(IN))為第二高電位電壓(1.2伏特)時，第二信號(V(OUT))為第一高電位電壓(1.8伏特)。如此，電壓位準轉換的目的便實現。 To sum up, when the first signal (V(IN)) is at a low level (0 volts), the second signal (V(OUT)) is also at a low level (0 volts); and the first signal (V(IN) ) is the second high potential voltage (1.2V), the second signal (V(OUT)) is the first high potential voltage (1.8V). In this way, the purpose of voltage level conversion is achieved.

(II)待機模式(Standby mode) (II) Standby mode (Standby mode)

請再參考圖3。在待機狀態下，亦即，當該致能控制端(EN)是在低電位狀態時，該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)均呈導通(ON)狀態，此時，由於該第三節點(N3)和該第四節點(N4)皆處於接近第一高電位電壓(VDDH)之電位，使得該第一PMOS電晶體(MP1)和該第二PMOS電晶體(MP2)都關閉，因此，該栓鎖電路(2)被除能。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low potential state, both the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) are in a conducting (ON) state , at this time, since the third node (N3) and the fourth node (N4) are both at potentials close to the first high potential voltage (VDDH), the first PMOS transistor (MP1) and the second PMOS transistor are The crystals (MP2) are all off, so the latch circuit (2) is disabled. Its working principle is not repeated here.

本創作所提出之高效能電壓位準移位器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之高效能電壓位準移位器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The simulation results of Spice transient analysis of the high-performance voltage level shifter proposed in this work are shown in Figure 4. The simulation results can confirm that the high-efficiency voltage level shifter proposed in this work has Not only can the first signal be converted into a second signal quickly and accurately, but also the power consumption can be effectively reduced.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected best embodiment, those skilled in the art will understand that any possible changes in form or detail do not depart from the spirit and scope of the present invention. Therefore, all changes within the relevant technical scope are included within the scope of the patent application of this creation.

1:輸入電路 1: Input circuit

2:栓鎖電路 2: Latch circuit

3:模式控制開關 3: Mode control switch

EN:致能控制端 EN: Enable control terminal

N1:第一節點 N1: the first node

N2:第二節點 N2: second node

N3:第三節點 N3: The third node

N4:第四節點 N4: Fourth Node

MP1:第一PMOS電晶體 MP1: The first PMOS transistor

MP2:第二PMOS電晶體 MP2: Second PMOS transistor

MP3:第三PMOS電晶體 MP3: Third PMOS transistor

MP4:第四PMOS電晶體 MP4: Fourth PMOS transistor

MP5:第五PMOS電晶體 MP5: Fifth PMOS transistor

MP6:第六PMOS電晶體 MP6: sixth PMOS transistor

MP7:第七PMOS電晶體 MP7: seventh PMOS transistor

MP8:第八PMOS電晶體 MP8: Eighth PMOS transistor

MN1:第一NMOS電晶體 MN1: The first NMOS transistor

MN2:第二NMOS電晶體 MN2: Second NMOS transistor

OUT:輸出端 OUT: output terminal

I1:第一反相器 I1: first inverter

IN:第一輸入端 IN: the first input terminal

V(IN):第一信號 V(IN): The first signal

INB:第二輸入端 INB: the second input terminal

V(OUT):第二信號 V(OUT): Second signal

GND:地 GND: ground

VDDH:第一高電源供應電壓 VDDH: The first high power supply voltage

VDDL:第二高電源供應電壓 VDDL: The second highest power supply voltage

Claims (7)

一種高效能電壓位準移位器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極以及一第七PMOS電晶體(MP7)的源極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極以及一第八PMOS電晶體(MP8)的源極連接在一起；一第三節點(N3)，用以將一第二PMOS電晶體(MP2)的閘極、一第七PMOS電晶體(MP7)的汲極、一第五PMOS電晶體(MP5)的汲極以及一第一NMOS電晶體(MN1)的汲極連接在一起；一第四節點(N4)，用以將一第一PMOS電晶體(MP1)的閘極、一第八PMOS電晶體(MP8)的汲極、一第六PMOS電晶體(MP6)的汲極以及一第二NMOS電晶體(MN2)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)的閘極、該第七PMOS電晶體(MP7)的閘極、該第一NMOS電晶體(MN1)的閘極以及該第一反相器(I1)的輸入端，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)的閘極、該第八PMOS電晶體(MP8)的閘極、該第二NMOS電晶體(MN2)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號； 一致能控制端(EN)，用以提供一致能信號；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一第一高電源供應電壓(VDDH)，用以提供該高效能電壓位準移位器所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，用以提供該高效能電壓位準移位器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一輸入電路(1)，耦接於該第一輸入端(IN)，用來提供差動輸入信號；一栓鎖電路(2)，耦接於該第一高電源供應電壓(VDDH)以及該輸入電路(1)，用來保存並且抑制輸出電位的競爭現象；以及一模式控制開關(3)，耦接於該輸入電路(1)以及該栓鎖電路(2)，用以控制該高效能電壓位準移位器之不同操作模式。 A high-performance voltage level shifter for converting a first signal (V(IN)) into a second signal (V(OUT)), comprising: a first node (N1) for converting a first signal (V(IN)) into a second signal (V(OUT)) The drain of a first PMOS transistor (MP1), the drain of a third PMOS transistor (MP3) and the source of a seventh PMOS transistor (MP7) are connected together; a second node (N2), For connecting the drain of a second PMOS transistor (MP2), the drain of a fourth PMOS transistor (MP4) and the source of an eighth PMOS transistor (MP8) together; a third node ( N3), for connecting the gate of a second PMOS transistor (MP2), the drain of a seventh PMOS transistor (MP7), the drain of a fifth PMOS transistor (MP5) and a first NMOS transistor The drains of the crystals (MN1) are connected together; a fourth node (N4) is used to connect the gate of a first PMOS transistor (MP1), the drain of an eighth PMOS transistor (MP8), and a first PMOS transistor (MP8). The drains of the six PMOS transistors (MP6) and the drains of a second NMOS transistor (MN2) are connected together; a first input terminal (IN) is coupled to the gate of the third PMOS transistor (MP3) pole, the gate of the seventh PMOS transistor (MP7), the gate of the first NMOS transistor (MN1) and the input terminal of the first inverter (I1) for providing a first signal (V (IN)); a second input terminal (INB), coupled to the gate of the fourth PMOS transistor (MP4), the gate of the eighth PMOS transistor (MP8), and the second NMOS transistor ( the gate of MN2) and the output terminal of the first inverter (I1), for providing the inverted signal of the first signal (V(IN)); an enable control terminal (EN) for providing an enable signal; an output terminal (OUT), coupled to the fourth node (N4) for outputting the second signal (V(OUT)); a first a high power supply voltage (VDDH) for providing the first high potential voltage required by the high performance voltage level shifter; a second high power supply voltage (VDDL) for providing the high performance voltage level shifter a second high potential voltage required by the bit device, the potential of the second high power supply voltage (VDDL) is lower than the potential of the first high power supply voltage (VDDH); an input circuit (1), coupled to the first high power supply voltage (VDDH) an input terminal (IN) for providing a differential input signal; a latch circuit (2) coupled to the first high power supply voltage (VDDH) and the input circuit (1) for saving and inhibiting the output The potential competition phenomenon; and a mode control switch (3), coupled to the input circuit (1) and the latch circuit (2), for controlling different operation modes of the high-performance voltage level shifter. 如申請專利範圍第1項所述的高效能電壓位準移位器，其中該輸入電路(1)包括：一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則連接至該第三節點(N3)；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則連接至該第四節點(N4)；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一 信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。 The high-efficiency voltage level shifter according to the claim 1, wherein the input circuit (1) comprises: a first NMOS transistor (MN1), the source of which is connected to the ground (GND), and the gate of which is connected to the ground (GND). The electrode is connected to the first input terminal (IN), and the drain electrode is connected to the third node (N3); a second NMOS transistor (MN2), whose source electrode is connected to the ground (GND), and its gate electrode connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1), coupled to the first input terminal (IN), with to accept the first signal (V(IN)), and provide a signal inverted to the first signal (V(IN)). 如申請專利範圍第2項所述的高效能電壓位準移位器，其中該栓鎖電路(2)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；一第七PMOS電晶體(MP7)，其源極連接至該第一節點(N1)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；以及一第八PMOS電晶體(MP8)，其源極連接至該第二節點(N2)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接。 The high-performance voltage level shifter as claimed in claim 2, wherein the latch circuit (2) comprises: a first PMOS transistor (MP1), the source of which is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the a first high power supply voltage (VDDH), the gate of which is connected to the third node (N3), and the drain of which is connected to the second node (N2); a third PMOS transistor (MP3), which is The source is connected to the first high power supply voltage (VDDH), the gate is connected to the first input terminal (IN), and the drain is connected to the first node (N1); a fourth PMOS power A crystal (MP4), its source is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to the second node (N2) ; a seventh PMOS transistor (MP7), its source is connected to the first node (N1), its gate is connected to the first input (IN), and its drain is connected to the third node (N3) ) is connected; and an eighth PMOS transistor (MP8), the source of which is connected to the second node (N2), the gate of which is connected to the second input terminal (INB), and the drain of which is connected to the second node (N2). Four nodes (N4) are connected. 如申請專利範圍第3項所述的高效能電壓位準移位器，其中該模式控制 開關(3)包括：一第五PMOS電晶體(MP5)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第六PMOS電晶體(MP6)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第三節點(N3)相連接；一第六PMOS電晶體(MP6)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極與該第五PMOS電晶體(MP5)的閘極相連接並連接至該致能控制端(EN)，而其汲極則與該第四節點(N4)相連接；以及一致能控制端(EN)，耦接於該第五PMOS電晶體(MP5)和該第六PMOS電晶體(MP6)的閘極，用以提供一致能信號。 The high-performance voltage level shifter of claim 3, wherein the mode controls The switch (3) includes: a fifth PMOS transistor (MP5), the source of which is connected to the first high power supply voltage (VDDH), and the gate of which is connected to the gate of the sixth PMOS transistor (MP6) and connected to the enable control terminal (EN), and its drain is connected to the third node (N3); a sixth PMOS transistor (MP6), its source is connected to the first high power supply voltage (VDDH), the gate of which is connected to the gate of the fifth PMOS transistor (MP5) and to the enable control terminal (EN), and the drain of which is connected to the fourth node (N4); and an enable control terminal (EN) coupled to the gates of the fifth PMOS transistor (MP5) and the sixth PMOS transistor (MP6) for providing an enable signal. 如申請專利範圍第1項所述的高效能電壓位準移位器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。 The high-performance voltage level shifter as claimed in claim 1, wherein the amplitude of the first signal (V(IN)) is between 0 volts and the second high power supply voltage (VDDL). 如申請專利範圍第5項所述的高效能電壓位準移位器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。 The high-performance voltage level shifter as claimed in claim 5, wherein the amplitude of the second signal (V(OUT)) is between 0 volts and the first high power supply voltage (VDDH). 如申請專利範圍第2項所述的高效能電壓位準移位器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。 The high-performance voltage level shifter as claimed in claim 2, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).
TW110213181U 2021-11-09 2021-11-09 High performance voltage level shifter TWM629687U (en)

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