TWM578459U - Power-saving level shifting circuit - Google Patents

Abstract

本創作提出一種節能電壓位準轉換器，其係由一栓鎖電路(1)、一輸出控制電路(2)、一輸入電路(3)以及一模式控制開關(4)所組成，其中，該栓鎖電路(1)用以保存來自該輸入電路(3)的差動輸入信號；該輸出控制電路(2)用來控制該節能電壓位準轉換器的輸出信號；該輸入電路(3)用來提供差動輸入信號；該模式控制開關(4)用以控制該節能電壓位準轉換器之不同操作模式。 This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to store the differential input signal from the input circuit (3); the output control circuit (2) is used to control the output signal of the energy-saving voltage level converter; the input circuit (3) is used To provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter.

由模擬結果證實，本創作所提出之節能電壓位準轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭。因此，可以大幅減少延遲時間，並且可以消除短路功率損耗。 The simulation results confirm that the energy-saving voltage level converter proposed by this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. At the same time, it can effectively suppress the competition between the pull-up path and the pull-down path. Therefore, the delay time can be greatly reduced, and short-circuit power loss can be eliminated.

Description

節能電壓位準轉換器 Energy-saving voltage level converter

本創作提出一種節能電壓位準轉換器，其係由一栓鎖電路(1)、一輸出控制電路(2)、一輸入電路(3)以及一模式控制開關(4)所組成，以求獲得精確電壓位準轉換且有效地避免上拉路徑和下拉路徑之間的競爭，進而降低功率損耗之電子電路。 This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). An electronic circuit that accurately converts voltage levels and effectively avoids competition between pull-up and pull-down paths, thereby reducing power loss.

電壓位準轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電壓位準轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 The voltage level converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transmit signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the voltage level converter is responsible for converting low-voltage working signals into high-voltage working signals. .

第1圖係顯示一先前技藝(prior art)之一閂鎖型電壓位準轉換器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一節能電壓位準轉換器電路，其中，該反相器(INV)的偏壓是第二高電位電壓(VDDL)及地(GND)，而輸入電壓(V(IN))的電位亦在地(GND)與第二高電位電壓(VDDL)之間。輸入電壓(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連 接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極(gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電壓位準轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電壓位準轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)截止(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而截止第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)截止時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而截止第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 FIG. 1 shows a latch-type voltage level converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1 ), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter The inverter (INV) constitutes an energy-saving voltage level converter circuit. The bias voltage of the inverter (INV) is the second high potential voltage (VDDL) and ground (GND), and the input voltage (V (IN) ) Is also between ground (GND) and the second high potential voltage (VDDL). The input voltage (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected separately. Connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, due to the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the voltage level converter is in a stable state, the latch No static current is generated in the lock-type voltage level converter. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電壓位準轉換器在第二PMOS電晶體(MP2)趨近於導通(或截止)與在第二NMOS電晶體(MN2)趨近於截止(或導通)的過程中，對於輸出節點(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此輸出電壓信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當輸入電壓(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電位電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低輸入電壓(V(IN))可能無 法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)達到完全導通或完全截止，如此會造成在第一高電位電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the process of the conventional voltage level converter described above, when the second PMOS transistor (MP2) is approaching on (or off) and when the second NMOS transistor (MN2) is approaching off (or on), There is a phenomenon of contention between the pull-up and pull-down of the potential at the output node (OUT), so the output voltage signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the input voltage (V (IN)) is changed from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that the first Two PMOS transistors (MP2) are turned on. Therefore, the output is a first high potential voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower input voltage (V (IN)) during the transition may not be Method to make the first PMOS transistor (MP1), the second PMOS transistor (MP2), the first NMOS transistor (MN1), and the second NMOS transistor (MN2) to be completely turned on or completely turned off. There is a static current between the high potential voltage (VDDH) and the ground (GND). This static current will increase the power loss.

再者，閂鎖型的電壓位準轉換器的性能是受到第一高電位電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電位電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電位電壓(VDDL)。因此，限制了可以使閂鎖型電壓位準轉換器正常運作的第一高電位電壓(VDDH)的範圍。 In addition, the performance of the latch-type voltage level converter is affected by the first high potential voltage (VDDH), because the gate-source of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) The voltage is the first high-potential voltage (VDDH), and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high-potential voltage (VDDL). Therefore, the range of the first high potential voltage (VDDH) that can make the latch-type voltage level converter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電壓位準轉換器電路，該電壓位準轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型電壓位準轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電位電壓(VDDH)改變，電壓位準轉換器的性能也不會有太大的改變。因此，鏡像型的電壓位準轉換器可以適用在各種輸出電壓電路。 Figure 2 shows a mirrored voltage level converter circuit, which is one of the other prior art. The voltage level converter is connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). Together and connected to the drain of the first PMOS transistor (MP1), the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit. The first PMOS transistor (MP1) is in The saturation region, and its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are also equal. Since the performance of the mirror-type voltage level converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output first high-potential voltage (VDDH) changes, the voltage The performance of the level converter will not change much. Therefore, the mirror-type voltage level converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體 (MN2)截止時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor is turned on When (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned off. Continuity. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種節能電壓位準轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地抑制上拉路徑和下拉路徑之間的競爭，進而降低功率損耗。 In view of this, the main purpose of this creation is to propose an energy-saving voltage level converter, which can not only accurately and quickly convert a first signal to a second signal, but also effectively suppress the difference between the pull-up path and the pull-down path Competition, which in turn reduces power loss.

本創作提出一種節能電壓位準轉換器，其係由一栓鎖電路(1)、一輸出控制電路(2)、一輸入電路(3)以及一模式控制開關(4)所組成，其中，該栓鎖電路(1)用以保存來自該輸入電路(3)的差動輸入信號；該輸出控制電路(2)用來控制該節能電壓位準轉換器的輸出信號；該輸入電路(3)用來提供差動輸入信號；該模式控制開關(4)用以控制該節能電壓位準轉換器之不同操作模式。 This creation proposes an energy-saving voltage level converter, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3), and a mode control switch (4). The latch circuit (1) is used to store the differential input signal from the input circuit (3); the output control circuit (2) is used to control the output signal of the energy-saving voltage level converter; the input circuit (3) is used To provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter.

由模擬結果證實，本創作所提出之節能電壓位準轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地抑制上拉路徑與下拉路徑的互相競爭，進而降低功率損耗。 The simulation results confirm that the energy-saving voltage level converter proposed by this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device. At the same time, it can also effectively suppress the competition between the pull-up path and the pull-down path, thereby reducing power loss.

1‧‧‧栓鎖電路 1‧‧‧ latch circuit

2‧‧‧輸出控制電路 2‧‧‧Output control circuit

3‧‧‧輸入電路 3‧‧‧input circuit

4‧‧‧模式控制開關 4‧‧‧Mode control switch

EN‧‧‧致能控制端 EN‧‧‧Enable control terminal

N1‧‧‧第一節點 N1‧‧‧First Node

N2‧‧‧第二節點 N2‧‧‧Second Node

N3‧‧‧第三節點 N3‧‧‧ third node

N4‧‧‧第四節點 N4‧‧‧ fourth node

N5‧‧‧第五節點 N5‧‧‧ fifth node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧The first PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧Second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧Third PMOS Transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧The first NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

MN3‧‧‧第三NMOS電晶體 MN3‧‧‧The third NMOS transistor

MN4‧‧‧第四NMOS電晶體 MN4‧‧‧Fourth NMOS transistor

MN5‧‧‧第五NMOS電晶體 MN5‧‧‧Fifth NMOS transistor

GND‧‧‧地 GND‧‧‧ Ground

IN‧‧‧第一輸入端 IN‧‧‧first input

V(IN)‧‧‧第一信號 V (IN) ‧‧‧First Signal

INB‧‧‧第二輸入端 INB‧‧‧Second Input

I1‧‧‧第一反相器 I1‧‧‧first inverter

OUT‧‧‧輸出端 OUT‧‧‧output

V(OUT)‧‧‧第二信號 V (OUT) ‧‧‧Second signal

VDDH‧‧‧第一高電源供應電壓 VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧第二高電源供應電壓 VDDL‧‧‧The second highest power supply voltage

第1圖 係顯示第一先前技藝中電壓位準轉換器之電路圖；第2圖 係顯示第二先前技藝中電壓位準轉換器之電路圖； 第3圖 係顯示本創作較佳實施例之節能電壓位準轉換器之電路圖；第4圖 係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖； Fig. 1 is a circuit diagram showing a voltage level converter in the first prior art; Fig. 2 is a circuit diagram showing a voltage level converter in the second prior art; FIG. 3 is a circuit diagram showing the energy-saving voltage level converter of the preferred embodiment of the present invention; FIG. 4 is a timing diagram of the transient analysis of the first signal and the second signal of the preferred embodiment of the present invention;

根據上述之目的，本創作提出一種節能電壓位準轉換器，如第3圖所示，其係由一栓鎖電路(1)、一輸出控制電路(2)、一輸入電路(3)以及一模式控制開關(4)所組成，其中，該栓鎖電路(1)用以保存來自該輸入電路(3)的差動輸入信號；該輸出控制電路(2)用來控制該節能電壓位準轉換器的輸出信號；該輸入電路(3)用來提供差動輸入信號；該模式控制開關(4)用以控制該節能電壓位準轉換器之不同操作模式；該栓鎖電路(1)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS電晶體(MN1)以及一第二NMOS電晶體(MN2)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；該第一NMOS電晶體(MN1)的源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；該第二NMOS電晶體(MN2)的源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接；該輸出控制電路(2)係由一第三PMOS電晶體(MP3)和一第四PMOS電晶體(MP4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲 極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該輸入電路(3)係由一第三NMOS電晶體(MN3)、一第四NMOS電晶體(MN4)以及一第一反相器(I1)所組成，其中，該第三NMOS電晶體(MN3)的源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；該第四NMOS電晶體(MN4)的源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；該第一反相器(I1)耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；該模式控制開關(4)係由一第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連接至該致能控制端(EN)，而其汲極則與該第五節點(N5)相連接；該第一高電源供應電壓(VDDH)係用以提供該節能電壓位準轉換器所需之第一高電源電壓，該第二高電源供應電壓(VDDL)係用以提供該節能電壓位準轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, the present invention proposes an energy-saving voltage level converter, as shown in FIG. 3, which is composed of a latch circuit (1), an output control circuit (2), an input circuit (3) and a A mode control switch (4), wherein the latch circuit (1) is used to store a differential input signal from the input circuit (3); the output control circuit (2) is used to control the energy-saving voltage level conversion Output signal of the converter; the input circuit (3) is used to provide a differential input signal; the mode control switch (4) is used to control different operation modes of the energy-saving voltage level converter; the latch circuit (1) is provided by A first PMOS transistor (MP1), a second PMOS transistor (MP2), a first NMOS transistor (MN1) and a second NMOS transistor (MN2), wherein the first PMOS transistor The source of (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the fourth node (N4), and its drain is connected to the first node (N1); the first The source of two PMOS transistors (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is Connected to the second node (N2); the source of the first NMOS transistor (MN1) is connected to the third node (N3), its gate is connected to the second input terminal (INB), and its sink The pole is connected to the first node (N1); the source of the second NMOS transistor (MN2) is connected to the fourth node (N4), and the gate is connected to the first input terminal (IN), and Its drain is connected to the second node (N2); the output control circuit (2) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), where the first The source of the three PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain The source is connected to the first node (N1); the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), and the gate is connected to the second input terminal (INB) ), And its drain is connected to the second node (N2); the input circuit (3) is composed of a third NMOS transistor (MN3), a fourth NMOS transistor (MN4) and a first inverter A phaser (I1), wherein the source of the third NMOS transistor (MN3) is connected to the fifth node (N5), its gate is connected to the first input terminal (IN), and its drain is Is connected to the third node (N3); the source of the fourth NMOS transistor (MN4) is connected to the fifth node (N5), its gate is connected to the second input terminal (INB), and its The drain is connected to the fourth node (N4); the first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN)), and Provide a signal that is opposite to the first signal (V (IN)); the mode control switch (4) is composed of a fifth NMOS transistor (MN5), the source of which is connected to the ground (GND), and The gate is connected to the enable control terminal (EN), and its drain is connected to the fifth node (N5). Connected; the first high power supply voltage (VDDH) is used to provide the first high power supply voltage required by the energy-saving voltage level converter, and the second high power supply voltage (VDDL) is used to provide the power-saving voltage level The second high power supply voltage required by the quasi-converter. The level of the second high power supply voltage (VDDL) is lower than the level of the first high power supply voltage (VDDH). The first signal is between 0 volts. And a rectangular wave between 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts, the first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage ( VDDL) is 1.2 volts, the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT)) is between 0 volts and 1.8 volts Corresponding waveform.

請再參閱第3圖，茲依電壓位準轉換器之工作模式說明圖3 之工作原理如下： Please refer to Fig. 3 again for the description of the working mode of the voltage level converter. Fig. 3 The working principle is as follows:

(I)主動模式(Active mode) (I) Active mode

在主動模式下，亦即，當該致能控制端(EN)是在高電位狀態時，該第五NMOS電晶體(MN5)呈導通(ON)狀態。 In the active mode, that is, when the enable control terminal (EN) is in a high potential state, the fifth NMOS transistor (MN5) is in an ON state.

現在考慮第一信號(V(IN))為邏輯低位準(0伏特)時，節能電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的邏輯低位準同時傳送到該第一反相器(I1)的輸入端、該第二NMOS電晶體(MN2)以及該第三NMOS電晶體(MN3)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都截止(OFF)，而該第一反相器(I1)傳送邏輯高位準(VDDL)到該第一NMOS電晶體(MN1)以及該第四NMOS電晶體(MN4)的閘極，使得該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都導通(ON)，此時，由於該第二NMOS電晶體(MN2)截止(OFF)，而該第四NMOS電晶體(MN4)導通，該第四節點(N4)的電位會被拉降至一邏輯低位準(0伏特)，而該第四節點(N4)上的邏輯低位準傳送到該第一PMOS電晶體(MP1)的閘極，使得該第一PMOS電晶體(MP1)導通，此時由於該第一PMOS電晶體(MP1)和該第一NMOS電晶體(MN1)都導通，而該第三NMOS電晶體(MN3)截止，因此，該第三節點(N3)的電位會被拉升至一邏輯高位準，該第三節點(N3)的邏輯高位準使得該第二PMOS電晶體(MP2)截止，由於該第二NMOS電晶體(MN2)和該第二PMOS電晶體(MP2)都截止，而該第四NMOS電晶體(MN4)導通，因此，該第四節點(N4)的電位將維持在邏輯低位準(0伏特)，輸出端(OUT)的電位會維持在一邏輯低位準(0伏特)的穩態值。質言之，第一信號(V(IN))為邏輯低位準(0伏特)時，經過節能電壓位準轉換器轉換成具邏輯低位準(0伏特) 的第二信號，由輸出端(OUT)輸出。 Now consider the steady-state operation of the energy-saving voltage level converter when the first signal (V (IN)) is a logic low level (0 volts): the logic low level on the first input (IN) is simultaneously transmitted to the first An input terminal of an inverter (I1), a gate of the second NMOS transistor (MN2) and a third NMOS transistor (MN3), so that the second NMOS transistor (MN2) and the third NMOS transistor The crystal (MN3) is turned off, and the first inverter (I1) transmits a logic high level (VDDL) to the gate of the first NMOS transistor (MN1) and the gate of the fourth NMOS transistor (MN4). , So that the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both turned on (ON), at this time, because the second NMOS transistor (MN2) is turned off (OFF), the fourth NMOS transistor The transistor (MN4) is turned on, the potential of the fourth node (N4) is pulled down to a logic low level (0 volts), and the logic low level on the fourth node (N4) is transmitted to the first PMOS circuit. The gate of the crystal (MP1) causes the first PMOS transistor (MP1) to be turned on. At this time, since the first PMOS transistor (MP1) and the first NMOS transistor (MN1) are both turned on, the third NMOS Transistor (MN3) is off, so this The potential of the three node (N3) will be pulled up to a logic high level. The logic high level of the third node (N3) causes the second PMOS transistor (MP2) to be turned off. And the second PMOS transistor (MP2) are both turned off, and the fourth NMOS transistor (MN4) is turned on, so the potential of the fourth node (N4) will be maintained at a logic low level (0 volts), and the output terminal ( The potential of OUT) is maintained at a steady state value at a logic low level (0 volts). In other words, when the first signal (V (IN)) is at a logic low level (0 volts), it is converted into a logic low level (0 volts) by an energy-saving voltage level converter. The second signal is output from the output terminal (OUT).

再考慮第一信號(V(IN))為邏輯高位準(VDDL)時，節能電壓位準轉換器的穩態操作情形：第一輸入端(IN)上的邏輯高位準(VDDL)同時傳送到該第一反相器(I1)的輸入端、該第二NMOS電晶體(MN2)以及該第三NMOS電晶體(MN3)的閘極，使得該第二NMOS電晶體(MN2)和該第三NMOS電晶體(MN3)都導通(ON)，而該第一反相器(I1)傳送邏輯低位準到該第一NMOS電晶體(MN1)以及該第四NMOS電晶體(MN4)的閘極，使得該第一NMOS電晶體(MN1)和該第四NMOS電晶體(MN4)都截止(OFF)，此時，由於該第三NMOS電晶體(MN3)導通，而該第一NMOS電晶體(MN1)截止(OFF)，該第三節點(N3)的電位會被拉降至一邏輯低位準，該第三節點(N3)上的邏輯低位準傳送到該第二PMOS電晶體(MP2)的閘極，使得該第二PMOS電晶體(MP2)導通，此時由於該第二PMOS電晶體(MP2)和該第二NMOS電晶體(MN2)都導通，而該第四NMOS電晶體(MN4)截止，因此，該第四節點(N4)的電位會被拉升至一邏輯高位準，該第四節點(N4)的邏輯高位準使得該第一PMOS電晶體(MP1)截止，此時由於該第一PMOS電晶體(MP1)和該第一NMOS電晶體(MN1)都截止，而該第三NMOS電晶體(MN3)導通，因此，該第三節點(N3)的電位將維持在一邏輯低位準，而該第四節點(N4)的電位亦將維持在一邏輯高位準，因此，輸出端(OUT)的電位會維持在一邏輯高位準的穩態值。質言之，第一信號(V(IN))為一邏輯高位準(VDDL)時，經過節能電壓位準轉換器轉換成具第一高電源供應電壓(VDDH)的第二信號，由輸出端(OUT)輸出。 Consider again the steady-state operation of the energy-saving voltage level converter when the first signal (V (IN)) is the logic high level (VDDL): the logic high level (VDDL) on the first input (IN) is simultaneously transmitted to An input terminal of the first inverter (I1), a gate of the second NMOS transistor (MN2), and a gate of the third NMOS transistor (MN3) make the second NMOS transistor (MN2) and the third The NMOS transistor (MN3) is all turned on, and the first inverter (I1) transmits a logic low level to the gates of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4), The first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are both turned OFF. At this time, because the third NMOS transistor (MN3) is turned on, the first NMOS transistor (MN1) is turned on. ) OFF, the potential of the third node (N3) is pulled down to a logic low level, and the logic low level on the third node (N3) is transmitted to the gate of the second PMOS transistor (MP2). Electrode, so that the second PMOS transistor (MP2) is turned on. At this time, because the second PMOS transistor (MP2) and the second NMOS transistor (MN2) are both turned on, and the fourth NMOS transistor (MN4) is turned off. And therefore, the fourth node (N4) The bit will be pulled up to a logic high level. The logic high level of the fourth node (N4) causes the first PMOS transistor (MP1) to turn off. At this time, the first PMOS transistor (MP1) and the first The NMOS transistor (MN1) is turned off and the third NMOS transistor (MN3) is turned on. Therefore, the potential of the third node (N3) will be maintained at a logic low level and the potential of the fourth node (N4) It will also be maintained at a logic high level. Therefore, the potential of the output terminal (OUT) will be maintained at a steady state value of a logic high level. In other words, when the first signal (V (IN)) is a logic high level (VDDL), it is converted into a second signal with the first high power supply voltage (VDDH) by the energy-saving voltage level converter, and is output by the output terminal. (OUT) output.

綜上所述，由於該第二PMOS電晶體(MP2)和該第四NMOS 電晶體(MN4)可以在短時間內同時導通。本創作透過將該第二NMOS電晶體(MN2)對應的上拉路徑切斷來減少競爭。當該第四NMOS電晶體(MN4)導通(亦即，下拉路徑被致能)時，該第二NMOS電晶體(MN2)將上拉路徑切斷，以避免上拉路徑和下拉路徑之間的競爭，因此，可以大幅減少延遲時間，並且可以消除短路功率損耗。 In summary, since the second PMOS transistor (MP2) and the fourth NMOS The transistor (MN4) can be turned on simultaneously in a short time. This work reduces the competition by cutting off the pull-up path corresponding to the second NMOS transistor (MN2). When the fourth NMOS transistor (MN4) is turned on (that is, the pull-down path is enabled), the second NMOS transistor (MN2) cuts off the pull-up path to avoid the difference between the pull-up path and the pull-down path. Competition, therefore, can significantly reduce the delay time and can eliminate short circuit power loss.

(II)待機模式(Standby mode) (II) Standby mode

請再參考圖3。在待機狀態下，亦即，當該致能控制端(EN)是在低電位狀態時，該第五NMOS電晶體(MN5)呈截止(OFF)狀態，此時，該電壓位準轉換器停止動作。此時，任何第一信號(V(IN))的輸入均不會影響到已被栓鎖住的第二信號(V(OUT))值。其工作原理於此不再累述。 Please refer to Figure 3 again. In the standby state, that is, when the enable control terminal (EN) is in a low-potential state, the fifth NMOS transistor (MN5) is in an OFF state. At this time, the voltage level converter stops action. At this time, the input of any first signal (V (IN)) will not affect the value of the second signal (V (OUT)) that has been locked. Its working principle is not repeated here.

本創作所提出之節能電壓位準轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之節能電壓位準轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 The Spice transient analysis simulation results of the energy-saving voltage level converter proposed by this creation are shown in Figure 4. From the simulation results, it can be confirmed that the energy-saving voltage level converter proposed by this creation can not only quickly The first signal is accurately converted into a second signal, and the power loss can be effectively reduced.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims (8)

一種節能電壓位準轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第一PMOS電晶體(MP1)的汲極、一第一NMOS電晶體(MN1)的汲極以及一第三PMOS電晶體(MP3)的汲極連接在一起；一第二節點(N2)，用以將一第二PMOS電晶體(MP2)的汲極、一第二NMOS電晶體(MN2)的汲極以及一第四PMOS電晶體(MP4)的汲極連接在一起；一第三節點(N3)，用以將該第一NMOS電晶體(MN1)的源極、一第三NMOS電晶體(MN3)的汲極以及該第二PMOS電晶體(MP2)的閘極連接在一起；一第四節點(N4)，用以將該第二NMOS電晶體(MN2)的源極、一第四NMOS電晶體(MN4)的汲極以及該第一PMOS電晶體(MP1)的閘極連接在一起；一第五節點(N5)，用以將該第三NMOS電晶體(MN3)的源極、該第四NMOS電晶體(MN4)的源極以及一第五NMOS電晶體(MN5)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)以及該第三NMOS電晶體(MN3)的閘極，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)以及該第四NMOS電晶體(MN4)的閘極，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第四節點(N4)，用以輸出該第二信號(V(OUT))；一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號；一致能控制端(EN)，耦接於該第五NMOS電晶體(MN5)的閘極，用以提供一致能信號；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)、該第二PMOS電晶體(MP2)、該第三PMOS電晶體(MP3)以及該第四PMOS電晶體(MP4)的源極，用以提供該節能電壓位準轉換器所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，用以提供該節能電壓位準轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一栓鎖電路(1)，用以保存來自一輸入電路(3)的差動輸入信號；一輸出控制電路(2)，用來控制該節能電壓位準轉換器的輸出信號；一輸入電路(3)，耦接於該第一輸入端(IN)，用來提供差動輸入信號；以及一模式控制開關(4)，用以控制該節能電壓位準轉換器之不同操作模式。An energy-saving voltage level converter is used for converting a first signal (V (IN)) into a second signal (V (OUT)), which includes: a first node (N1) for converting a first signal (N1) A drain of a PMOS transistor (MP1), a drain of a first NMOS transistor (MN1), and a drain of a third PMOS transistor (MP3) are connected together; a second node (N2) is used for Connect the drain of a second PMOS transistor (MP2), the drain of a second NMOS transistor (MN2), and the drain of a fourth PMOS transistor (MP4); a third node (N3) To connect the source of the first NMOS transistor (MN1), the drain of a third NMOS transistor (MN3), and the gate of the second PMOS transistor (MP2); a fourth node (N4), used to connect the source of the second NMOS transistor (MN2), the drain of a fourth NMOS transistor (MN4), and the gate of the first PMOS transistor (MP1); The fifth node (N5) is used to connect the source of the third NMOS transistor (MN3), the source of the fourth NMOS transistor (MN4), and the drain of a fifth NMOS transistor (MN5) to Together; a first input terminal (IN) is coupled to the third PMOS transistor (MP3) and the gate of the third NMOS transistor (MN3) are used to provide a first signal (V (IN)); a second input terminal (INB) is coupled to the fourth PMOS transistor ( MP4) and the gate of the fourth NMOS transistor (MN4) to provide an inverted signal of the first signal (V (IN)); an output terminal (OUT) is coupled to the fourth node (N4) ) To output the second signal (V (OUT)); a first inverter (I1) is coupled to the first input terminal (IN) to receive the first signal (V (IN) ), And provide a signal opposite to the first signal (V (IN)); the uniform energy control terminal (EN) is coupled to the gate of the fifth NMOS transistor (MN5) to provide uniform energy Signal; a first high power supply voltage (VDDH), coupled to the first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), and the fourth PMOS The source of the transistor (MP4) is used to provide the first high potential voltage required by the energy-saving voltage level converter; a second high power supply voltage (VDDL) is used to provide the energy-saving voltage level converter. The second highest potential voltage required, the second highest power supply voltage (VDDL) The potential is less than the first high power supply voltage (VDDH); a latch circuit (1) is used to save the differential input signal from an input circuit (3); an output control circuit (2) is used to Controlling an output signal of the energy-saving voltage level converter; an input circuit (3) coupled to the first input terminal (IN) for providing a differential input signal; and a mode control switch (4) for Control different operation modes of the energy-saving voltage level converter. 如申請專利範圍第1項所述的節能電壓位準轉換器，其中該栓鎖電路(1)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第四節點(N4)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第三節點(N3)，而其汲極則與該第二節點(N2)相連接；一第一NMOS電晶體(MN1)，其源極連接至該第三節點(N3)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第一節點(N1)相連接；以及一第二NMOS電晶體(MN2)，其源極連接至該第四節點(N4)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第二節點(N2)相連接。The energy-saving voltage level converter according to item 1 of the scope of patent application, wherein the latch circuit (1) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the fourth node (N4), and whose drain is connected to the first node (N1); a second PMOS transistor (MP2), whose source is connected to the first High power supply voltage (VDDH), its gate is connected to the third node (N3), and its drain is connected to the second node (N2); a first NMOS transistor (MN1), its source Connected to the third node (N3), its gate is connected to the second input terminal (INB), and its drain is connected to the first node (N1); and a second NMOS transistor (MN2) Its source is connected to the fourth node (N4), its gate is connected to the first input terminal (IN), and its drain is connected to the second node (N2). 如申請專利範圍第2項所述的節能電壓位準轉換器，其中該輸出控制電路(2)包括：一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。The energy-saving voltage level converter according to item 2 of the scope of patent application, wherein the output control circuit (2) includes: a third PMOS transistor (MP3) whose source is connected to the first high power supply voltage ( VDDH), whose gate is connected to the first input terminal (IN), and whose drain is connected to the first node (N1); and a fourth PMOS transistor (MP4), whose source is connected to the The first high power supply voltage (VDDH) has a gate connected to the second input terminal (INB) and a drain connected to the second node (N2). 如申請專利範圍第3項所述的節能電壓位準轉換器，其中該輸入電路(3)包括：一第三NMOS電晶體(MN3)，其源極連接至該第五節點(N5)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三節點(N3)相連接；一第四NMOS電晶體(MN4)，其源極連接至該第五節點(N5)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四節點(N4)相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。The energy-saving voltage level converter according to item 3 of the scope of patent application, wherein the input circuit (3) includes: a third NMOS transistor (MN3), the source of which is connected to the fifth node (N5), and The gate is connected to the first input terminal (IN), and its drain is connected to the third node (N3); a fourth NMOS transistor (MN4), and its source is connected to the fifth node (N5) ), Its gate is connected to the second input terminal (INB), and its drain is connected to the fourth node (N4); and a first inverter (I1) is coupled to the first input The terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)). 如申請專利範圍第4項所述的節能電壓位準轉換器，其中該模式控制開關(4)係由該第五NMOS電晶體(MN5)所組成，其源極連接至地(GND)，其閘極連接至該致能控制端(EN)，而其汲極則與該第五節點(N5)相連接。The energy-saving voltage level converter according to item 4 of the scope of patent application, wherein the mode control switch (4) is composed of the fifth NMOS transistor (MN5), and its source is connected to the ground (GND). The gate is connected to the enable control terminal (EN), and its drain is connected to the fifth node (N5). 如申請專利範圍第1項所述的節能電壓位準轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。The energy-saving voltage level converter according to item 1 of the scope of patent application, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL). 如申請專利範圍第6項所述的節能電壓位準轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。The energy-saving voltage level converter according to item 6 of the patent application scope, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH). 如申請專利範圍第7項所述的節能電壓位準轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。The energy-saving voltage level converter according to item 7 of the patent application scope, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).