TWM565914U

TWM565914U - Voltage level shifter

Info

Publication number: TWM565914U
Application number: TW106211560U
Authority: TW
Inventors: 余建政; 陳威仁; 黃裕晨
Original assignee: 修平學校財團法人修平科技大學
Priority date: 2017-08-04
Filing date: 2017-08-04
Publication date: 2018-08-21

Abstract

本創作提出一種電位轉換器，其係由一預充電電路(1)、一栓鎖器(2)以及一信號輸入電路(3)所組成，其中，該預充電電路(1)係用來將該第一節點(N1)以及該第二節點(N2)的電位拉升到第二高電源供應電壓(VDDL)；該栓鎖器(2)係用以保存由該第一NMOS電晶體(MN1)以及該第二NMOS電晶體(MN2)接收的差動輸入信號；該信號輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號。 This creation proposes a potential converter, which is composed of a precharge circuit (1), a latch (2), and a signal input circuit (3), where the precharge circuit (1) is used to convert The potentials of the first node (N1) and the second node (N2) are pulled up to a second high power supply voltage (VDDL); the latch (2) is used to hold the first NMOS transistor (MN1) ) And the differential input signal received by the second NMOS transistor (MN2); the signal input circuit (3) is used to provide the first signal (V (IN)) and the first signal (V (IN)) Inverted signal.

本創作所提出之電位轉換器，不但能精確地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少漏電流，進而降低功率消耗。 The potential converter proposed in this creation can not only accurately convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to miniaturization of the device, and can also effectively reduce leakage current. This reduces power consumption.

Description

電位轉換器 Potentiometer

本創作係有關一種電位轉換器，尤指利用一預充電電路(1)、一栓鎖器(2)以及一信號輸入電路(3)所組成，以求獲得精確電壓位準轉換且有效地降低功率消耗之電子電路。 This creation relates to a potential converter, especially using a pre-charging circuit (1), a latch (2) and a signal input circuit (3), in order to obtain accurate voltage level conversion and effectively reduce Electronic circuit for power consumption.

電位轉換器係一種用來溝通不同的積體電路(Integrated Circuit，簡稱IC)之間的信號傳遞之電子電路。在許多應用中，當應用系統需將信號從電壓位準較低的核心邏輯傳送到電壓位準較高的週邊裝置時，電位轉換器就負責將低電壓工作信號轉換成高電壓工作信號。 A potential converter is an electronic circuit used to communicate signal transmission between different integrated circuits (ICs). In many applications, when the application system needs to transfer signals from core logic with lower voltage levels to peripheral devices with higher voltage levels, the potential converter is responsible for converting low-voltage working signals into high-voltage working signals.

第1圖係顯示一先前技藝(prior art)之一閂鎖型電位轉換器電路，其係使用一第一PMOS(P-channel metal oxide semiconductor，P通道金屬氧化物半導體)電晶體(MP1)、一第二PMOS電晶體(MP2)、一第一NMOS(N-channel metal oxide semiconductor，N通道金屬氧化物半導體)電晶體(MN1)、一第二NMOS電晶體(MN2)及一反相器(INV)來構成一電位轉換器電路，其中，該反相器(INV)的偏壓是第二高電源供應電壓(VDDL)及地(GND)，而第一信號(V(IN))的電位亦在地(GND)與第二高電源供應電壓(VDDL)之間。第一信號(V(IN))及經過反相器(INV)輸出的反相輸入電壓信號分別連接至第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)的閘極 (gate)。因此，在同一時間內，第一NMOS電晶體(MN1)及第二NMOS電晶體(MN2)之中只有一個會導通(ON)。此外，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的交叉耦合(cross-coupled)方式，使得當電位轉換器的輸出(OUT)處於一個穩定的狀態時，閂鎖型的電位轉換器中沒有靜態電流(static current)產生。尤其，當第一NMOS電晶體(MN1)關閉(OFF)而第二NMOS電晶體(MN2)導通(ON)時，第一PMOS電晶體(MP1)的閘極電位被拉降(pull down)並使得第一PMOS電晶體(MP1)導通，以致拉升(pull up)第二PMOS電晶體(MP2)的閘極電位而關閉第二PMOS電晶體(MP2)；再者，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第二PMOS電晶體(MP2)的閘極電位被拉降並使得第二PMOS電晶體(MP2)導通，以致拉升第一PMOS電晶體(MP1)的閘極電位而關閉第一PMOS電晶體(MP1)。因此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間或第二PMOS電晶體(MP2)和第二NMOS電晶體(MN2)之間就不會存在一個電流路徑。 Figure 1 shows a latch-type potential converter circuit of a prior art, which uses a first PMOS (P-channel metal oxide semiconductor) transistor (MP1), A second PMOS transistor (MP2), a first NMOS (N-channel metal oxide semiconductor) transistor (MN1), a second NMOS transistor (MN2), and an inverter ( INV) to form a potential converter circuit, where the bias voltage of the inverter (INV) is the second highest power supply voltage (VDDL) and ground (GND), and the potential of the first signal (V (IN)) Also between ground (GND) and the second highest power supply voltage (VDDL). The first signal (V (IN)) and the inverted input voltage signal output through the inverter (INV) are connected to the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2), respectively. (gate). Therefore, at the same time, only one of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) will be turned on. In addition, because of the cross-coupled mode of the first PMOS transistor (MP1) and the second PMOS transistor (MP2), when the output (OUT) of the potential converter is in a stable state, the latch type No static current is generated in the potentiometer. In particular, when the first NMOS transistor (MN1) is turned off and the second NMOS transistor (MN2) is turned on, the gate potential of the first PMOS transistor (MP1) is pulled down and pulled down. The first PMOS transistor (MP1) is turned on, so that the gate potential of the second PMOS transistor (MP2) is pulled up and the second PMOS transistor (MP2) is turned off; further, when the first NMOS transistor is turned on When (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potential of the second PMOS transistor (MP2) is pulled down and the second PMOS transistor (MP2) is turned on, so that the first PMOS transistor is pulled up The gate potential of the crystal (MP1) turns off the first PMOS transistor (MP1). Therefore, there will be no current path between the first PMOS transistor (MP1) and the first NMOS transistor (MN1) or between the second PMOS transistor (MP2) and the second NMOS transistor (MN2).

然而，上述習知電位轉換器在第二PMOS電晶體(MP2)趨近於導通(或關閉)與在第二NMOS電晶體(MN2)趨近於關閉(或導通)的過程中，對於輸出端(OUT)上的電位之拉升及拉降有互相競爭(contention)的現象，因此第二信號(V(OUT))在轉變成低電位時速度較慢。此外，考慮當第一信號(V(IN))由0伏特改變至1.8伏特時，第一NMOS電晶體(MN1)導通，而第二PMOS電晶體(MP2)的閘極變為低電位，使得第二PMOS電晶體(MP2)導通。所以，輸出為一第一高電源供應電壓(VDDH)。但是，由於0伏特無法瞬間轉換至1.8伏特，因此，在轉換期間的較低第一信號(V(IN))可能無法使第一PMOS電晶體(MP1)、第二PMOS電晶體(MP2)、第一NMOS電晶體 (MN1)及第二NMOS電晶體(MN2)達到完全導通或完全關閉，如此會造成在第一高電源供應電壓(VDDH)與地(GND)之間存在一靜態電流(static current)，此靜態電流會增加功率的損耗。 However, in the process of the above-mentioned conventional potential converter, when the second PMOS transistor (MP2) approaches to turn on (or off) and the second NMOS transistor (MN2) approaches to turn off (or on), the output terminal There is a phenomenon of contention between the pull-up and pull-down of the potential at (OUT), so the second signal (V (OUT)) is slower when it is converted to a low potential. In addition, it is considered that when the first signal (V (IN)) changes from 0 volts to 1.8 volts, the first NMOS transistor (MN1) is turned on, and the gate of the second PMOS transistor (MP2) becomes low, so that The second PMOS transistor (MP2) is turned on. Therefore, the output is a first high power supply voltage (VDDH). However, because 0 volts cannot be instantly converted to 1.8 volts, the lower first signal (V (IN)) during the conversion may not enable the first PMOS transistor (MP1), the second PMOS transistor (MP2), First NMOS transistor (MN1) and the second NMOS transistor (MN2) are completely turned on or completely turned off. This will cause a static current between the first high power supply voltage (VDDH) and ground (GND). This static Current increases power loss.

再者，閂鎖型的電位轉換器的性能是受到第一高電源供應電壓(VDDH)的影響，由於第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘-源極電壓為第一高電源供應電壓(VDDH)，而第一NMOS電晶體(MN1)和第二NMOS電晶體(MN2)的閘-源極電壓是第二高電源供應電壓(VDDL)。因此，限制了可以使閂鎖型電位轉換器正常運作的第一高電源供應電壓(VDDH)的範圍。 Furthermore, the performance of the latch-type potential converter is affected by the first high power supply voltage (VDDH), due to the gate-source voltage of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). The first high power supply voltage (VDDH) is supplied, and the gate-source voltage of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) is the second high power supply voltage (VDDL). Therefore, the range of the first high power supply voltage (VDDH) that can make the latch type potential converter operate normally is limited.

第2圖係顯示另一先前技藝之一鏡像型電位轉換器電路，該電位轉換器藉由將第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極連接在一起並連接到第一PMOS電晶體(MP1)的汲極，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)形成電流鏡電路，第一PMOS電晶體(MP1)是處於飽和區，並且其閘極電壓使得飽和電流等於流入第一NMOS電晶體(MN1)之電流，而流經第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)之電流亦相等。由於鏡像型的電位轉換器的性能是由第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)的電流來決定，因此，即使輸出的第一高電源供應電壓(VDDH)改變，電位轉換器的性能也不會有太大的改變。因此，鏡像型的電位轉換器可以適用在各種輸出電壓電路。 Figure 2 shows one of the other prior art mirror-type potential converter circuits. The potential converter is connected and connected by the gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2). To the drain of the first PMOS transistor (MP1), so that the first PMOS transistor (MP1) and the second PMOS transistor (MP2) form a current mirror circuit, the first PMOS transistor (MP1) is in a saturation region, and Its gate voltage makes the saturation current equal to the current flowing into the first NMOS transistor (MN1), and the current flowing through the first PMOS transistor (MP1) and the second PMOS transistor (MP2) is also equal. Since the performance of the mirror-type potential converter is determined by the current of the first PMOS transistor (MP1) and the first NMOS transistor (MN1), even if the output of the first high power supply voltage (VDDH) changes, the potential The performance of the converter will not change much. Therefore, the mirror-type potential converter can be applied to various output voltage circuits.

然而，當第一NMOS電晶體(MN1)導通而第二NMOS電晶體(MN2)關閉時，第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)的閘極電位被拉降，使得第一PMOS電晶體(MP1)和第二PMOS電晶體(MP2)都導通。如此，在第一PMOS電晶體(MP1)和第一NMOS電晶體(MN1)之間會產生一個靜態電流路徑。 However, when the first NMOS transistor (MN1) is turned on and the second NMOS transistor (MN2) is turned off, the gate potentials of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are pulled down, so that Both the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are turned on. In this way, a static current path is generated between the first PMOS transistor (MP1) and the first NMOS transistor (MN1).

有鑑於此，本創作之主要目的係提出一種電位轉換器，其不但能精確且快速地將第一信號轉換為一第二信號，並且可有效地減少漏電流，進而降低功率消耗。 In view of this, the main purpose of this creation is to propose a potential converter, which can not only accurately and quickly convert the first signal into a second signal, but also effectively reduce the leakage current and thus the power consumption.

本創作提出一種電位轉換器，其係由一預充電電路(1)、一栓鎖器(2)以及一信號輸入電路(3)所組成，其中，該預充電電路(1)係用來將該第一節點(N1)以及該第二節點(N2)的電位拉升到第二高電源供應電壓(VDDL)；該栓鎖器(2)係用以保存由輸入電晶體接收的輸入信號；該信號輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號。 This creation proposes a potential converter, which is composed of a precharge circuit (1), a latch (2), and a signal input circuit (3), where the precharge circuit (1) is used to convert The potentials of the first node (N1) and the second node (N2) are pulled up to the second high power supply voltage (VDDL); the latch (2) is used to save the input signal received by the input transistor; The signal input circuit (3) is used to provide the first signal (V (IN)) and an inverted signal of the first signal (V (IN)).

由模擬結果證實，本創作所提出之電位轉換器，不但能精確且快速地將第一信號轉換為一第二信號，並且兼具電路結構簡單以及有利於裝置之小型化等多重功效，同時亦能有效地減少功率損耗。 The simulation results confirm that the potential converter proposed in this creation can not only accurately and quickly convert the first signal into a second signal, but also has multiple functions such as simple circuit structure and conducive to the miniaturization of the device. Can effectively reduce power loss.

1‧‧‧預充電電路 1‧‧‧ pre-charge circuit

2‧‧‧栓鎖器 2‧‧‧ latch

3‧‧‧信號輸入電路 3‧‧‧ signal input circuit

I1‧‧‧第一反相器 I1‧‧‧first inverter

N1‧‧‧第一節點 N1‧‧‧First Node

N2‧‧‧第二節點 N2‧‧‧Second Node

MP1‧‧‧第一PMOS電晶體 MP1‧‧‧The first PMOS transistor

MP2‧‧‧第二PMOS電晶體 MP2‧‧‧Second PMOS transistor

MP3‧‧‧第三PMOS電晶體 MP3‧‧‧Third PMOS Transistor

MP4‧‧‧第四PMOS電晶體 MP4‧‧‧Fourth PMOS transistor

MN1‧‧‧第一NMOS電晶體 MN1‧‧‧The first NMOS transistor

MN2‧‧‧第二NMOS電晶體 MN2‧‧‧Second NMOS transistor

MN3‧‧‧第三NMOS電晶體 MN3‧‧‧The third NMOS transistor

MN4‧‧‧第四NMOS電晶體 MN4‧‧‧Fourth NMOS transistor

IN‧‧‧第一輸入端 IN‧‧‧first input

V(IN)‧‧‧第一信號 V (IN) ‧‧‧First Signal

INB‧‧‧第二輸入端 INB‧‧‧Second Input

OUT‧‧‧輸出端 OUT‧‧‧output

GND‧‧‧地 GND‧‧‧ Ground

V(OUT)‧‧‧第二信號 V (OUT) ‧‧‧Second signal

VDDH‧‧‧第一高電源供應電壓 VDDH‧‧‧The first highest power supply voltage

VDDL‧‧‧第二高電源供應電壓 VDDL‧‧‧The second highest power supply voltage

第1圖係顯示第一先前技藝中電位轉換器之電路圖；第2圖係顯示第二先前技藝中電位轉換器之電路圖；第3圖係顯示本創作較佳實施例之電位轉換器之電路圖；第4圖係顯示本創作較佳實施例之第一信號及第二信號之暫態分析時序圖。 Figure 1 shows the circuit diagram of the potential converter in the first prior art; Figure 2 shows the circuit diagram of the potential converter in the second prior art; Figure 3 shows the circuit diagram of the potential converter in the preferred embodiment of the present invention; FIG. 4 is a timing diagram illustrating the transient analysis of the first signal and the second signal in the preferred embodiment of the present invention.

根據上述之目的，本創作提出一種電位轉換器，如第3圖所示，其係由一預充電電路(1)、一栓鎖器(2)以及一信號輸入電路(3)所組成，其中，該預充電電路(1)係用來將該第一節點(N1)以及該第二節點(N2)的電位拉升到第二高電源供應電壓(VDDL)；該栓鎖器(2)係用以保存由該第一NMOS電晶體(MN1)以及該第二NMOS電晶體(MN2)接收的差動輸入信號；該信號輸入電路(3)係用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號；該預充電電路(1)係由一第三PMOS電晶體(MP3)以及一第四PMOS電晶體(MP4)所組成，其中，該第三PMOS電晶體(MP3)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；該第四PMOS電晶體(MP4)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接；該栓鎖器(2)係由一第一PMOS電晶體(MP1)、一第二PMOS電晶體(MP2)、一第三NMOS電晶體(MN3)以及一第四NMOS電晶體(MN4)所組成，其中，該第一PMOS電晶體(MP1)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；該第二PMOS電晶體(MP2)的源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接；該第三NMOS電晶體(MN3)的源極連接至該第一NMOS電晶體(MN1)的汲極，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；該第四NMOS電晶體(MN4)的源極連接至該第二NMOS電晶體(MN2)的汲極，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接；該信號輸入電路(3)係由一第一NMOS電晶體(MN1)、一第二NMOS電晶體(MN2)以及一第一反相器(I1)所組成，其中，該第一NMOS電晶體(MN1)的源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三NMOS電晶體(MN3)的源極相連接；該第二NMOS電晶體(MN2)的源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四NMOS電晶體(MN4)的源極相連接；而該第一反相器(I1)係耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供該第二輸入端(INB)一個與該第一信號(V(IN))反相的信號；該第一高電源供應電壓(VDDH)係用以提供該電位轉換器所需之第一高電源電壓，該第二高電源供應電壓(VDDL)係用以提供該電位轉換器所需之第二高電源電壓，該第二高電源供應電壓(VDDL)之位準係小於該第一高電源供應電壓(VDDH)之位準，該第一信號為介於0伏特及1.2伏特間的矩形波，而該第二信號則為介於0伏特及1.8伏特間的對應波形，該第一高電源供應電壓(VDDH)為1.8伏特，而該第二高電源供應電壓(VDDL)為1.2伏特，該第一信號(V(IN))為介於0伏特及1.2伏特間的矩形波，該第二信號(V(OUT))則為介於0伏特及1.8伏特間的對應波形。 According to the above purpose, this creation proposes a potential converter, as shown in FIG. 3, which is composed of a precharge circuit (1), a latch (2), and a signal input circuit (3), where The pre-charging circuit (1) is used to pull the potentials of the first node (N1) and the second node (N2) to the second high power supply voltage (VDDL); the latch (2) is It is used to save the differential input signal received by the first NMOS transistor (MN1) and the second NMOS transistor (MN2); the signal input circuit (3) is used to provide the first signal (V (IN) ) And the inverted signal of the first signal (V (IN)); the precharge circuit (1) is composed of a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4), where: The source of the third PMOS transistor (MP3) is connected to the first high power supply voltage (VDDH), its gate is connected to the first input terminal (IN), and its drain is connected to the first node ( N1) phase connection; the source of the fourth PMOS transistor (MP4) is connected to the first high power supply voltage (VDDH), its gate is connected to the second input terminal (INB), and its drain is connected to The second node (N2) is connected ; The latch (2) is composed of a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third NMOS transistor (MN3) and a fourth NMOS transistor (MN4) The source of the first PMOS transistor (MP1) is connected to the first high power supply voltage (VDDH), its gate is connected to the second node (N2), and its drain is connected to the first node A node (N1) is connected; the source of the second PMOS transistor (MP2) is connected to the first high power supply voltage (VDDH), its gate is connected to the first node (N1), and its drain It is connected to the second node (N2); the source of the third NMOS transistor (MN3) is connected to the drain of the first NMOS transistor (MN1), and its gate is connected to The second node (N2), and its drain is connected to the first node (N1); the source of the fourth NMOS transistor (MN4) is connected to the drain of the second NMOS transistor (MN2) , Its gate is connected to the first node (N1), and its drain is connected to the second node (N2); the signal input circuit (3) is composed of a first NMOS transistor (MN1), a A second NMOS transistor (MN2) and a first inverter (I1), wherein the source of the first NMOS transistor (MN1) is connected to the ground (GND), and the gate of the first NMOS transistor (MN1) is connected to the first The input terminal (IN), and its drain is connected to the source of the third NMOS transistor (MN3); the source of the second NMOS transistor (MN2) is connected to the ground (GND), and its gate is connected To the second input terminal (INB), and its drain is connected to the source of the fourth NMOS transistor (MN4); and the first inverter (I1) is coupled to the first input terminal (IN) for receiving the first signal (V (IN)) and providing a signal at the second input terminal (INB) which is opposite to the first signal (V (IN)); the first high power source The supply voltage (VDDH) is used to provide the first high power supply voltage required by the potential converter. The high power supply voltage (VDDL) is used to provide a second high power supply voltage required by the potential converter. The level of the second high power supply voltage (VDDL) is less than that of the first high power supply voltage (VDDH). Level, the first signal is a rectangular wave between 0 volts and 1.2 volts, and the second signal is a corresponding waveform between 0 volts and 1.8 volts. The first high power supply voltage (VDDH) is 1.8 volts, and the second high power supply voltage (VDDL) is 1.2 volts, the first signal (V (IN)) is a rectangular wave between 0 volts and 1.2 volts, and the second signal (V (OUT) ) Is the corresponding waveform between 0 volts and 1.8 volts.

請再參閱第3圖，現在考慮第一信號(V(IN))為低電位(0伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的低電位同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)以及第三PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)關閉、第三PMOS電晶體(MP3)導通，此時該第一節點(N1)的電位被拉升至一高電位；而該第一反相器(I1)傳送第二高電源供應電壓(VDDL)到第二NMOS電晶體(MN2)和第四PMOS電晶體(MP4)的閘極，使得第二NMOS電晶體(MN2)導通、第四PMOS電晶體(MP4)關閉，由於該第一節點(N1)的高電位使得第二PMOS電晶體(MP2)關閉、第四NMOS電晶體(MN4)導通，此時，由於第二NMOS電晶體(MN2)和第四NMOS電晶體(MN4)都導通，因此，該第二節點(N2)的電位會被拉降至一低電位(0伏特)的穩態值，再者，該第二節點(N2)上的低電位傳送到第一PMOS電晶體(MP1)和第三NMOS電晶體(MN3)的閘極，使得第一PMOS電晶體(MP1)導通、第三NMOS電晶體(MN3)關閉，由於第一PMOS電晶體(MP1)和第三PMOS電晶體(MP3)都導通，第一NMOS電晶體(MN1)和第三NMOS電晶體(MN3)都關閉，因此，第一節點(N1)的電位會被拉升至一第一高電源供應電壓(VDDH)，而由於第二NMOS電晶體(MN2)和第四NMOS電晶體(MN4)都導通，第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都關閉，因此，第二節點(N2)的電位將維持在低電位(0伏特)，因此，輸出端(OUT)的電位會被拉降至一低電位(0伏特)的穩態值。質言之，第一信號(V(IN))為低電位(0伏特)時，經過電位轉換器轉換成具低電位(0伏特)的第二信號，由輸出端(OUT)輸出。 Please refer to Figure 3 again. Now consider the steady-state operation of the potential converter when the first signal (V (IN)) is low potential (0 volts): the low potential on the first input (IN) is simultaneously transmitted to First The input terminal of an inverter (I1), the gates of the first NMOS transistor (MN1) and the third PMOS transistor (MP3) make the first NMOS transistor (MN1) turn off and the third PMOS transistor ( MP3) is turned on, at this time the potential of the first node (N1) is pulled up to a high potential; and the first inverter (I1) transmits a second high power supply voltage (VDDL) to the second NMOS transistor ( MN2) and the gate of the fourth PMOS transistor (MP4), so that the second NMOS transistor (MN2) is turned on and the fourth PMOS transistor (MP4) is turned off. The high potential of the first node (N1) makes the second The PMOS transistor (MP2) is turned off and the fourth NMOS transistor (MN4) is turned on. At this time, since the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are both turned on, the second node (N2 ) Is pulled down to a steady state value of a low potential (0 volts), and the low potential at the second node (N2) is transferred to the first PMOS transistor (MP1) and the third NMOS transistor. The gate of (MN3) turns on the first PMOS transistor (MP1) and turns off the third NMOS transistor (MN3). Since both the first PMOS transistor (MP1) and the third PMOS transistor (MP3) are turned on, the first One NMOS transistor (MN1) and a third N The MOS transistor (MN3) is turned off, so the potential of the first node (N1) will be pulled up to a first high power supply voltage (VDDH), and because the second NMOS transistor (MN2) and the fourth NMOS transistor The crystal (MN4) is turned on, the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are both turned off. Therefore, the potential of the second node (N2) will be maintained at a low potential (0 volts). Therefore, the output The potential at the terminal OUT is pulled down to a steady state value of a low potential (0 volts). In other words, when the first signal (V (IN)) is at a low potential (0 volts), it is converted into a second signal with a low potential (0 volts) by a potential converter, and is output by the output terminal (OUT).

再考慮第一信號(V(IN))為第二高電位電壓(1.2伏特)時，電位轉換器的穩態操作情形：第一輸入端(IN)上的第二高電源供應電壓(VDDL)同時傳送到第一反相器(I1)的輸入端、第一NMOS電晶體(MN1)以及第三 PMOS電晶體(MP3)的閘極，使得該第一NMOS電晶體(MN1)導通、第三PMOS電晶體(MP3)關閉，而該第一反相器(I1)傳送一低電位到第二NMOS電晶體(MN2)和第四PMOS電晶體(MP4)的閘極，使得第二NMOS電晶體(MN2)關閉、第四PMOS電晶體(MP4)導通，此時由於第四PMOS電晶體(MP4)導通，該第二節點(N2)的電位會被拉升至一高電位；而該第二節點(N2)的高電位使得第一PMOS電晶體(MP1)關閉、第三NMOS電晶體(MN3)導通，此時由於第一NMOS電晶體(MN1)和第三NMOS電晶體(MN3)都導通，因此，該第一節點(N1)的電位會被拉降至一低電位(0伏特)的穩態值，再者，該第一節點(N1)上的低電位傳送到第二PMOS電晶體(MP2)和第四NMOS電晶體(MN4)的閘極，使得第二PMOS電晶體(MP2)導通、第四NMOS電晶體(MN4)關閉，由於第二PMOS電晶體(MP2)和第四PMOS電晶體(MP4)都導通，第二NMOS電晶體(MN2)和第四NMOS電晶體(MN4)都關閉，因此，第二節點(N2)的電位將維持在第一高電源供應電壓(VDDH)，而第一節點(N1)的電位維持在低電位(0伏特)，因此，輸出端(OUT)的電位會被拉升至一第一高電源供應電壓(VDDH)的穩態值。質言之，第一信號(V(IN))為第二高電位電壓(1.2伏特)時，經過電位轉換器轉換成具第一高電位電壓(1.8伏特)的第二信號，由輸出端(OUT)輸出。 Consider again the steady-state operation of the potential converter when the first signal (V (IN)) is the second high potential voltage (1.2 volts): the second high power supply voltage (VDDL) on the first input (IN) Simultaneously transferred to the input of the first inverter (I1), the first NMOS transistor (MN1), and the third The gate of the PMOS transistor (MP3) causes the first NMOS transistor (MN1) to be turned on, the third PMOS transistor (MP3) to be turned off, and the first inverter (I1) transmits a low potential to the second NMOS The gates of the transistor (MN2) and the fourth PMOS transistor (MP4) cause the second NMOS transistor (MN2) to be turned off and the fourth PMOS transistor (MP4) to be turned on. At this time, due to the fourth PMOS transistor (MP4) Turn on, the potential of the second node (N2) will be pulled up to a high potential; and the high potential of the second node (N2) causes the first PMOS transistor (MP1) to be turned off and the third NMOS transistor (MN3) to be turned off Turn on. At this time, because the first NMOS transistor (MN1) and the third NMOS transistor (MN3) are both on, the potential of the first node (N1) will be pulled down to a low potential (0 volts). State value, and further, the low potential on the first node (N1) is transmitted to the gates of the second PMOS transistor (MP2) and the fourth NMOS transistor (MN4), so that the second PMOS transistor (MP2) is turned on The fourth NMOS transistor (MN4) is turned off. Since both the second PMOS transistor (MP2) and the fourth PMOS transistor (MP4) are turned on, both the second NMOS transistor (MN2) and the fourth NMOS transistor (MN4) are turned on. Off, so the second node (N 2) The potential will be maintained at the first high power supply voltage (VDDH), and the potential at the first node (N1) will be maintained at a low potential (0 volts). Therefore, the potential at the output terminal (OUT) will be pulled up to one Steady-state value of the first high power supply voltage (VDDH). In other words, when the first signal (V (IN)) is the second high-potential voltage (1.2 volts), it is converted into a second signal with the first high-potential voltage (1.8 volts) by a potential converter, and the output terminal ( OUT) output.

綜上所述，第一信號(V(IN))為低電位(0伏特)時，第二信號(V(OUT))亦為低電位(0伏特)；而第一信號(V(IN))為第二高電位電壓(1.2伏特)時，第二信號(V(OUT))為第一高電位電壓(1.8伏特)。如此，電壓位準轉換的目的便實現。 In summary, when the first signal (V (IN)) is low potential (0 volts), the second signal (V (OUT)) is also low potential (0 volts); and the first signal (V (IN) ) Is the second high potential voltage (1.2 volts), the second signal (V (OUT)) is the first high potential voltage (1.8 volts). In this way, the purpose of voltage level conversion is achieved.

本創作所提出之電位轉換器之Spice暫態分析模擬結果，如第4圖所示，由該模擬結果可証實，本創作所提出之電位轉換器，其不但仍能快速且精確地將第一信號轉換為一第二信號，並且能有效地降低功率的損耗。 Spice transient analysis simulation results of the potential converter proposed in this creation, such as As shown in FIG. 4, the simulation results confirm that the potential converter proposed by this creation can not only quickly and accurately convert the first signal into a second signal, but also effectively reduce the power loss.

雖然本創作特別揭露並描述了所選之最佳實施例，但舉凡熟悉本技術之人士可明瞭任何形式或是細節上可能的變化均未脫離本創作的精神與範圍。因此，所有相關技術範疇內之改變都包括在本創作之申請專利範圍內。 Although the present invention specifically discloses and describes the selected preferred embodiment, those skilled in the art can understand that any form or details of possible changes can be made without departing from the spirit and scope of this creation. Therefore, all changes within the relevant technical scope are included in the scope of the patent application for this creation.

Claims

一種電位轉換器，用以將一第一信號(V(IN))轉換為一第二信號(V(OUT))，其包括：一第一節點(N1)，用以將一第二PMOS電晶體(MP2)的閘極、一第一PMOS電晶體(MP1)的汲極、一第三PMOS電晶體(MP3)的汲極、一第三NMOS電晶體(MN3)的汲極以及一第四NMOS電晶體(MN4)的閘極連接在一起；一第二節點(N2)，用以將一第一PMOS電晶體(MP1)的閘極、一第二PMOS電晶體(MP2)的汲極、一第四PMOS電晶體(MP4)的汲極、一第三NMOS電晶體(MN3)的閘極以及一第四NMOS電晶體(MN4)的汲極連接在一起；一第一輸入端(IN)，耦接於該第三PMOS電晶體(MP3)的閘極、一第一NMOS電晶體(MN1)的閘極以及一第一反相器(I1)的輸入端，用以提供一第一信號(V(IN))；一第二輸入端(INB)，耦接於該第四PMOS電晶體(MP4)的閘極、一第二NMOS電晶體(MN2)的閘極以及該第一反相器(I1)的輸出端，用以提供該第一信號(V(IN))的反相信號；一輸出端(OUT)，耦接於該第二節點(N2)，用以輸出該第二信號(V(OUT))；一第一高電源供應電壓(VDDH)，耦接於該第一PMOS電晶體(MP1)以及該第二PMOS電晶體(MP2)的源極，用以提供該電位轉換器所需之第一高電位電壓；一第二高電源供應電壓(VDDL)，耦接於該第三PMOS電晶體(MP3)、該第四PMOS電晶體(MP4)的源極以及該第一反相器(I1)，用以提供該電位轉換器所需之第二高電位電壓，該第二高電源供應電壓(VDDL)之電位係小於該第一高電源供應電壓(VDDH)之電位；一預充電電路(1)，用以將該第一節點(N1)以及該第二節點(N2)的電位拉升到第二高電源供應電壓(VDDL)；一栓鎖器(2)，用以保存由該第一NMOS電晶體(MN1)以及該第二NMOS電晶體(MN2)接收的差動輸入信號；以及一信號輸入電路(3)，用來提供該第一信號(V(IN))以及該第一信號(V(IN))的反相信號。A potential converter for converting a first signal (V (IN)) into a second signal (V (OUT)). The potential converter includes a first node (N1) for converting a second PMOS voltage The gate of the crystal (MP2), a drain of a first PMOS transistor (MP1), a drain of a third PMOS transistor (MP3), a drain of a third NMOS transistor (MN3), and a fourth The gates of the NMOS transistor (MN4) are connected together; a second node (N2) is used to connect the gate of a first PMOS transistor (MP1), the drain of a second PMOS transistor (MP2), A drain of a fourth PMOS transistor (MP4), a gate of a third NMOS transistor (MN3), and a drain of a fourth NMOS transistor (MN4) are connected together; a first input terminal (IN) Is coupled to the gate of the third PMOS transistor (MP3), the gate of a first NMOS transistor (MN1), and the input terminal of a first inverter (I1) to provide a first signal (V (IN)); a second input terminal (INB), coupled to the gate of the fourth PMOS transistor (MP4), a gate of a second NMOS transistor (MN2), and the first inverter The output terminal of the converter (I1) is used to provide an inverted signal of the first signal (V (IN)); an output terminal (OUT ) Is coupled to the second node (N2) to output the second signal (V (OUT)); a first high power supply voltage (VDDH) is coupled to the first PMOS transistor (MP1) And the source of the second PMOS transistor (MP2) is used to provide a first high potential voltage required by the potential converter; a second high power supply voltage (VDDL) is coupled to the third PMOS transistor (MP3), the source of the fourth PMOS transistor (MP4), and the first inverter (I1) are used to provide a second high potential voltage required by the potential converter, and the second high power supply voltage The potential of (VDDL) is less than the potential of the first high power supply voltage (VDDH); a precharge circuit (1) is used to pull up the potential of the first node (N1) and the second node (N2) To the second highest power supply voltage (VDDL); a latch (2) to hold the differential input signal received by the first NMOS transistor (MN1) and the second NMOS transistor (MN2); and A signal input circuit (3) is used to provide the first signal (V (IN)) and an inverted signal of the first signal (V (IN)).

如申請專利範圍第1項所述的電位轉換器，其中該預充電電路(1)包括：一第三PMOS電晶體(MP3)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第一節點(N1)相連接；以及一第四PMOS電晶體(MP4)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第二節點(N2)相連接。The potential converter according to item 1 of the patent application scope, wherein the precharge circuit (1) comprises: a third PMOS transistor (MP3), the source of which is connected to the first high power supply voltage (VDDH), Its gate is connected to the first input terminal (IN), and its drain is connected to the first node (N1); and a fourth PMOS transistor (MP4), its source is connected to the first high The power supply voltage (VDDH) has a gate connected to the second input terminal (INB), and a drain connected to the second node (N2).

如申請專利範圍第2項所述的電位轉換器，其中該栓鎖器(2)包括：一第一PMOS電晶體(MP1)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；一第二PMOS電晶體(MP2)，其源極連接至該第一高電源供應電壓(VDDH)，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接；一第三NMOS電晶體(MN3)，其源極連接至該第一NMOS電晶體(MN1)的汲極，其閘極連接至該第二節點(N2)，而其汲極則與該第一節點(N1)相連接；以及一第四NMOS電晶體(MN4)，其源極連接至該第二NMOS電晶體(MN2)的汲極，其閘極連接至該第一節點(N1)，而其汲極則與該第二節點(N2)相連接。The potential converter according to item 2 of the scope of patent application, wherein the latch (2) includes: a first PMOS transistor (MP1) whose source is connected to the first high power supply voltage (VDDH), Its gate is connected to the second node (N2), and its drain is connected to the first node (N1); a second PMOS transistor (MP2), its source is connected to the first high power supply Voltage (VDDH), its gate is connected to the first node (N1), and its drain is connected to the second node (N2); a third NMOS transistor (MN3), its source is connected to the The drain of the first NMOS transistor (MN1) has its gate connected to the second node (N2), and its drain is connected to the first node (N1); and a fourth NMOS transistor (MN4) ), Its source is connected to the drain of the second NMOS transistor (MN2), its gate is connected to the first node (N1), and its drain is connected to the second node (N2).

如申請專利範圍第3項所述的電位轉換器，其中信號輸入電路(3)包括：一第一NMOS電晶體(MN1)，其源極連接至地(GND)，其閘極連接至該第一輸入端(IN)，而其汲極則與該第三NMOS電晶體(MN3)的源極相連接；一第二NMOS電晶體(MN2)，其源極連接至地(GND)，其閘極連接至該第二輸入端(INB)，而其汲極則與該第四NMOS電晶體(MN4)的源極相連接；以及一第一反相器(I1)，耦接於該第一輸入端(IN)，用以接受該第一信號(V(IN))，並提供一個與該第一信號(V(IN))反相的信號。The potential converter according to item 3 of the patent application scope, wherein the signal input circuit (3) includes: a first NMOS transistor (MN1), a source of which is connected to ground (GND), and a gate of which is connected to the first An input terminal (IN), and its drain is connected to the source of the third NMOS transistor (MN3); a second NMOS transistor (MN2), whose source is connected to the ground (GND), and its gate And the drain is connected to the source of the fourth NMOS transistor (MN4); and a first inverter (I1) is coupled to the first input terminal (INB). The input terminal (IN) is used to receive the first signal (V (IN)) and provide a signal that is opposite to the first signal (V (IN)).

如申請專利範圍第4項所述的電位轉換器，其中該第一反相器(I1)的電壓源為該第二高電源供應電壓(VDDL)。The potential converter according to item 4 of the scope of patent application, wherein the voltage source of the first inverter (I1) is the second high power supply voltage (VDDL).

如申請專利範圍第1項所述的電位轉換器，其中該第一信號(V(IN))的振幅為0伏特至該第二高電源供應電壓(VDDL)之間。The potential converter according to item 1 of the patent application range, wherein the amplitude of the first signal (V (IN)) is between 0 volts and the second high power supply voltage (VDDL).

如申請專利範圍第6項所述的電位轉換器，其中該第二信號(V(OUT))的振幅為0伏特至該第一高電源供應電壓(VDDH)之間。The potential converter according to item 6 of the application, wherein the amplitude of the second signal (V (OUT)) is between 0 volts and the first high power supply voltage (VDDH).