TWI566328B - 具有用於產生附加構件之多晶矽層的氮化鎵電晶體 - Google Patents

具有用於產生附加構件之多晶矽層的氮化鎵電晶體 Download PDF

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TWI566328B
TWI566328B TW103125695A TW103125695A TWI566328B TW I566328 B TWI566328 B TW I566328B TW 103125695 A TW103125695 A TW 103125695A TW 103125695 A TW103125695 A TW 103125695A TW I566328 B TWI566328 B TW I566328B
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metal
gate
polysilicon
region
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TW103125695A
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TW201519363A (zh
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建軍 曹
羅伯特 畢曲
亞力山大 里道
亞雷納 納卡塔
趙廣元
馬豔萍
羅伯特 史瑞特瑪特
麥可Ａ 迪魯吉
周春華
謝斯海德里 庫魯里
劉芳昌
江銘崑
曹佳麗
阿古斯 猶哈爾
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高效電源轉換公司
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Description

具有用於產生附加構件之多晶矽層的氮化鎵電晶體
本發明係有關氮化鎵(GaN)裝置之領域，且更特定的是，有關使用一或多個多晶矽層來製造主動及被動矽裝置之GaN積體電路的製造。
氮化鎵(GaN)半導體裝置由於其能以高頻切換、承載大電流、且支援高電壓的能力而與日俱增地合乎吾人所欲。這些裝置的發展普遍針對高功率/高頻率應用。針對這些類型應用製作之裝置係基於顯現高電子遷移率的一般裝置結構，且不同地被稱作異質接面場效電晶體(HFET)、高電子遷移率電晶體(HEMT)、或調變摻雜場效電晶體(MODFET)。這些類型的裝置典型地可忍受例如30V至2000V的高電壓，同時在例如100kHz-100GHz的高頻下運作。
一GaN HEMT裝置包括具有至少二氮化層之一氮化物半導體。在半導體或在一緩衝層上形成不同材料會使層體具有不同能隙。相鄰的氮化層中的不同材料亦會造成極化，其造成靠近兩層之接面處，特別是在具有較窄能隙之層體中的一傳導二維電子氣(2DEG)區域。
造成極化之氮化層典型包括鄰近一GaN層的一 AlGaN障蔽層以含括2DEG，而允許電荷流過裝置。此障蔽層可為摻雜或未摻雜。由於2DEG區域在零閘極偏壓下存在於閘極下方，大部分的氮化鎵裝置係為通常導通或空乏模式裝置。若2DEG區域在零施加閘極偏壓下於閘極之上被空乏，即移除時，則此裝置可為一增強模式裝置。增強模式裝置為通常截止，且由於所提供之附加安全性且它們較易以簡單、低成本之驅動電路來控制，故其合於吾人之意。一增強模式裝置需要在閘極處施加一正偏壓以傳導電流。
圖1A~1H繪示用於製造一增強模式(通常截止)GaN電晶體之一傳統製造程序。如圖1A所示，例示性裝置藉在由矽(Si)、碳化矽(SiC)或類似物形成的一基體10上先沉積數個層體而形成。特別是，一氮化鋁(AlN)種層11沉積在基體10上，一氮化鎵鋁(AlGaN)層12形成在種層11上，且一氮化鎵(GaN)層13形成在AlGaN層12上。此外，一氮化鎵鋁(AlGaN)障蔽層14形成在GaN層13上，一pGaN層15形成在障蔽層14上，且一閘極金屬16形成在pGaN層15上。如圖1A進一步所示，光阻17在閘極金屬16上沉積做為保護層，以使用光阻界定閘極圖案。
接著，如圖1B所示，閘極金屬16及pGaN材料15(即晶體)利用作為保護層之光阻17來蝕刻。接下來如圖1C及1D中所示，絕緣層或膜18被沉積，且接觸開口19A及19B係形成用於源極與汲極接點。再者，沉積一第一鋁金屬以界定金屬圖案。如圖1E所示，金屬層可形成源極金屬20A、汲極金屬20B、及隨意而定的場板20C。如圖1F中所示，一 中間層介電質接著沉積。在此範例中，絕緣層18與在圖1C中所沉積者為相同材料。
一旦中間層介電質18沉積，如圖1G所示，可在金屬層間切出通孔22A及22B。此等通孔可填充鎢來形成一插塞，且可沉積一第二鋁金屬層以形成金屬21A及21B。此步驟可如圖1H中所示再次實行而形成額外通孔切口24A及24B與額外金屬23A及23B。接著可在第三鋁金屬23A及23B上方沉積一鈍化層25。圖2顯示由圖1A~1H之程序所形成之GaN結構的掃描式電子顯微鏡圖。
以上圖1A~1H中所述之程序的一限制在於所製造的裝置為在晶片上的一單一增強模式裝置。第二限制在於上文提及的GaN HEMT裝置使用一高度傳導電子氣(2DEG)，而因此為一n通道電晶體。然而，由於氮化鎵中極不良的電洞遷移率，故難以製造一p通道電晶體。此外，亦難以在氮化鎵中製造其他類型的矽裝置。
據此，吾人會希望有用以形成包括以其他方式難以在氮化鎵中製造之矽主動及被動構件之GaN積體電路的方法。
本文係揭露包括用以製造用於一積體電路之附加構件的GaN電晶體裝置及其製造方法。此GaN裝置包括一EPI結構及置設在EPI結構上方的一絕緣材料。此外，一或多個多晶矽層置設在絕緣材料中，而該等多晶矽層具有一或多個n型區域及p型區域。此裝置更包括置設在絕緣材料 上的金屬互連部，及置設在絕緣材料中將源極與汲極金屬連接至多晶矽層之n型及p型區域的通孔。
一種用以製造GaN電晶體裝置的方法包括形成一EPI結構，其具有一基體、在該基體上方的一AlGaN層、在該AlGaN層上方的一GaN層、在該AlGaN層上方的一障蔽層、在該障蔽層上方的一p型GaN層；在該p型GaN層上沉積一閘極金屬；及在該閘極金屬上方形成一光阻，且蝕刻該閘極金屬及該p型GaN層。此方法更包括沉積一第一絕緣層；蝕刻該第一絕緣層以在絕緣材料中形成一對接觸窗；及在該對接觸窗中形成一源極金屬與一汲極金屬。接著，沉積一第二絕緣層且在該第二絕緣層上沉積一多晶矽層。在沉積該多晶矽層後，此製造方法更包括下列步驟：摻雜該多晶矽層以在該多晶矽層中形成至少一n型區域及至少一p型區域；沉積一第三絕緣層且在該第三絕緣層中形成第一多數通孔，該等通孔分別耦合至該源極金屬、該汲極金屬、該多晶矽層之該至少一n型區域、及該多晶矽層之該至少一p型區域；及在該第三絕緣層上形成一金屬層。
10、110、211、311、411‧‧‧基體
11、111‧‧‧種層
12、112‧‧‧AlGaN層
13‧‧‧GaN層
14‧‧‧障蔽層
15‧‧‧pGaN層/pGaN材料
16、116、217、417‧‧‧閘極金屬
17‧‧‧光阻
18‧‧‧絕緣層/中間層介電質
19A、19B‧‧‧接觸開口
20A、120A、220、325、422‧‧‧源極金屬
20B、120B、221、326、423‧‧‧汲極金屬
20C、120C‧‧‧場板
22A、22B、123A~123E、125A、125B、226~229、327、328、429、430‧‧‧通孔
21A、21B、23A、23B‧‧‧金屬
24A、24B‧‧‧通孔切口
25‧‧‧鈍化層
113、214、314、414‧‧‧通道層
114‧‧‧AlGaN障蔽層
115‧‧‧pGaN層
118‧‧‧絕緣體/絕緣層
121、128、240、340、442‧‧‧多晶矽層
121A‧‧‧n型區域
121B、224、322、425‧‧‧p型區域
121C‧‧‧未摻雜區域
122‧‧‧絕緣層
124A、126、126A、126B、420‧‧‧金屬層
124B‧‧‧第二金屬層
212、312、412‧‧‧電晶體層/過渡層
213、313、413‧‧‧緩衝層/緩衝材料
215‧‧‧(AlGaN)障蔽層/層體
216‧‧‧p(型)GaN層
218、324、418‧‧‧隔離區域
219‧‧‧絕緣材料/介電材料
222‧‧‧底閘極(金屬)/背閘極/多晶矽FET/閘極金屬
223、225、321、323、424、426‧‧‧n型區域/摻雜區域
230~233、331、333、334、431、432‧‧‧金屬接點
315‧‧‧(AlGaN)障蔽層/障蔽材料
316、318‧‧‧p型GaN材料
317‧‧‧閘極金屬/p型GaN材料
319‧‧‧閘極金屬/底閘極
320‧‧‧絕緣層/絕緣材料/介電材料
415‧‧‧(AlGaN)障蔽層/障蔽材料/層體
416‧‧‧pGaN層/p型GaN材料
419‧‧‧絕緣材料/介電材料
421‧‧‧底閘極/障蔽金屬層/閘極金屬
440‧‧‧障蔽金屬
本揭露內容之特徵、目的及優點將在結合圖式審視以下詳細敘述時更為明顯看出，圖中相同參考符號於全文中係做對應標示，且其中：
圖1A~1H繪示用以製造一增強模式(常閉)GaN電晶體的一傳統製造程序。
圖2顯示由圖1A~1H之程序所形成之GaN結構的 一掃描式電子顯微鏡圖。
圖3A~3H繪示根據本發明之一第一實施例在一GaN積體電路中使用一多晶矽層以製造主動及被動矽裝置。
圖4A及4B繪示根據本發明之一例示性實施例的一GaN積體電路之額外實施例。
圖5A~5J繪示使用一多晶矽層以製造如圖4A及/或4B中所示在一GaN積體電路中之裝置的一例示性製造程序。
圖6繪示根據本發明之GaN積體電路的又另一實施例。
圖7A~7H繪示使用一多晶矽層來製造如圖6中所示在一GaN積體電路中之裝置的一例示性製造程序。
圖8繪示根據本發明之一例示性實施例的GaN積體電路的又另一變化。
圖9A~9I繪示使用一多晶矽層來製造如圖8中所示在一GaN積體電路中之裝置的一例示性製造程序。
在以下詳細敘述中，某些實施例係為參考。這些實施例採足夠詳細敘述以使熟悉此技者能夠實施它們。將了解的是在本文中所揭露者可採用其他實施例並可做成多種結構的、邏輯的、及電子氣的改變，且使用材料的變化來形成積體電路之多種層體。在後附詳細敘述中所揭示之特徵的多種組合，對於欲以最寬廣意義範圍來實施本案教 示內容，可能非屬必要，而反倒僅是用來描述本發明之特定代表範例。
圖3A~3H繪示根據本發明之一第一實施例使用一多晶矽層以在一GaN積體電路中製造主動及被動矽裝置。
本發明所述之製造方法的第一例示性實施例之初始步驟使用如同以上那些針對圖1A~1F所述之一GaN電晶體之傳統製造技術的相同與相似步驟。特別是，一EPI結構包括一沉積在一基體上的種層(例如氮化鋁(AlN))，其由矽(Si)、碳化矽(SiC)或類似物所形成。並且，一或多個過渡層(例如氮化鎵鋁(AlGaN))形成在該種層上，且一通道層(例如一氮化鎵(GaN)層)形成在該AlGaN層上。由氮化鎵鋁(AlGaN)所組成的障蔽層，例如，接著形成在該通道層上，使得一二維電子氣(2DEG)形成在該通道層與該障蔽層間之接面處。
在例示性實施例中，為形成閘極，將一pGaN層形成在障蔽層上，且將一閘極金屬形成在該pGaN層上。接著，在該閘極金屬上沉積一光阻作為保護層以使用該光阻界定閘極圖案，且蝕刻該閘極金屬及該pGaN材料。而後沉積一絕緣層且在該絕緣層中形成接觸開口用於源極與汲極接點。再者，沉積一鋁金屬以界定源極金屬、汲極金屬、及隨意而定的一場板。其次，中間層介電質沉積在金屬接點上。
圖3A繪示從這些初步製造步驟所得之結構。如 同所示，基體110從底層至頂層設置有一AlN種層111、一AlGaN層112、由GaN或類似物組成之一通道層113、及形成於其上之一AlGaN障蔽層114。此外，由pGaN層115及閘極金屬116組成的一閘極接點形成在AlGaN障蔽層114上，以及形成源極金屬120A、汲極金屬120B與場板120C。並且，絕緣體118置設在金屬接點及障蔽層上方。注意到的是雖然在例示性實施例中(如以上所述)，閘極接點/結構係使用經圖案化光阻形成在pGaN層115及閘極金屬116上方，但閘極接點/結構也可使用熟於此技者可了解的替代方法來形成。例如，閘極結構可為形成在障蔽層114中的凹入閘極，及F-植入(氟植入)閘極、或任何用以形成一增強模式裝置的其他方法形成者。
接著，如圖3B所示，一多晶矽層121沉積在絕緣層118上，且雜質被植入以界定具有p型摻雜、n型摻雜及/或沒有摻雜的區域。這些區域將形成用於p-n二極體、npn及pnp電晶體、電阻器、電容器、與其他主動及被動元件之基礎。于圖3B所示之範例中，多晶矽層121包括一n型區域121A、一p型區域121B、及一未摻雜區域121C。其次，使用一接觸光罩來圖案化多晶矽層121並對其蝕刻，如圖3C所示。
再者，如圖3D所示，絕緣層122接著沉積在多晶矽層121上方。通孔123A~123E而後形成於絕緣層122及絕緣層118(在圖3E中合併顯示為絕緣層118)中。特別是，通孔123A連接源極金屬120A，通孔123B連接汲極金屬120B，通 孔123C連接n型區域121A，通孔123D連接p型區域121B，且通孔123E連接未摻雜區域121C。在例示性實施例中，可施用鎢(W)或銅(Cu)插塞技術來填充較小、較高長寬比的通孔123A~123E，同時利用0.01至0.1μm範圍厚的TiN薄層用以使多晶矽層121的區域接觸。應知，雖然在例示性實施例中使用通孔，但在業界中可採許多共通方式連接金屬及多晶矽。
來到圖3F，接著沉積一金屬層以建立互連體，藉此將矽主動及被動構件附加在GaN電晶體上。尤其是，如例示性實施例中所示，一金屬層124A與通孔123A及123C電氣耦合，而一第二金屬層124B與通孔123B、123D及123E電氣耦合。
於一改良型態中，如圖3G所繪示，額外通孔125A及125B與額外金屬層126A及126B亦形成至裝置。替代地或附加地，如圖3H所示可形成一第二多晶矽層。特別是，第二多晶矽層128藉由通孔127耦合至另一金屬層126。在例示性實施例中，第二多晶矽層128可被附加以形成n通道及p通道MOSFET。圖3H顯示二多晶矽層121及128的互連。一MOSFET的汲極與源極電極界定於多晶矽層121中，而閘極電極界定於多晶矽層128中。
應了解的是，對於圖3A~3H中所繪示的例示性製造方法可做出許多變化及修改。例如，如圖3H所示，可由氧化多晶矽及附加一金屬或多晶矽閘極電極而附加一n通道及/或p通道MOS裝置。並且，多重多晶矽層可被附加以 對多晶矽MOSFET產生諸如多晶矽對多晶矽(poly-poly)電容器的附加構件以及閘極。此外，矽構件可被用來針對GaN電晶體產生閘極過電壓保護。最後，多晶矽可被用來針對GaN電晶體產生汲極-源極的過電壓保護，及/或產生可在相同晶片上與GaN電晶體配合使用的CMOS構件。
圖4A及4B繪示根據本發明之一例示性實施例的一GaN積體電路之額外實施例。尤其是，圖4A繪示具有一底閘極多晶矽裝置結構的一GaN積體電路。如同所示，GaN裝置形成在一基體211、一或多個電晶體層212(例如一AlN種層)、一緩衝層213(例如一AlGaN層)、一通道層214(例如GaN)及一AlGaN障蔽層215上。這些層體與針對第一實施例所述之結構類似。如以上所提，一2DEG區域形成在通道層214及緩衝層215之間的介面處。
如進一步所示，一pGaN層216及閘極金屬217形成在障蔽層215上且形成閘極結構。源極與汲極金屬220及221形成在障蔽層215上，而通孔228及229將源極與汲極金屬220及221分別電氣連接至金屬接點232及233。並且，一隔離區域218透過離子植入或蝕刻於障蔽層215、通道層214中形成，且延伸至緩衝層213中。隔離區域形成在障蔽層中，且通道層將2DEG區域之第一部分與2DEG區域之第二部分電氣隔離。此裝置更包括電氣絕緣且保護裝置金屬的一絕緣材料219。如同所示，多晶矽FET的一底閘極222形成在絕緣材料中。注意到的是，底閘極222可為一金屬、多晶矽或其他傳導材料。應了解的是，閘極結構形成在2DEG區 域之一部分上方，同時底或背閘極222形成在與第一區域隔離的2DEG區域之一第二部分上方。
此外，一多晶矽層形成在底閘極上方。特別是，該多晶矽層可包含一n型區域223、一p型區域224及一n型區域225(即用於裝置源極、閘極與汲極之一NPN層)，但是應了解的是，此等區域可被反過來形成一PNP層。通孔226及227分別將摻雜區域223及225耦合至金屬接點230及231。據此，圖4A中所示之裝置包括供一多晶矽FET用之一底閘極結構，其置設在電路內與GaN FET之主動胞元隔離的一區域中。
圖4B繪示圖4A中所示裝置的一替代性實施例。圖4B中之裝置的層體及構件與圖4A相同，且將不會在此重述。圖4B中所示之裝置不同在於多晶矽FET 222形成於電路之作用區域中，而不是如圖4A中所示裝置設置在隔離區域中。
圖5A~5J繪示使用一多晶矽層以在如圖4A及/或4B中所示之GaN積體電路中製造裝置的例示性製造方法。所有的程序流程可用來在作用裝置區域(圖4B)或在隔離區域(圖4A)兩者中形成底閘極多晶矽FET。由多晶矽/閘極金屬所形成之背閘極防止2DEG電位在多晶矽FET上的效應。
圖5A繪示一EPI結構，從底部至頂部包括：矽基體211、過渡層212、一緩衝材料213(例如AlGaN)、一通道層214(例如GaN)、及一障蔽材料215(例如AlGaN)。再者，一p型GaN材料216形成在障蔽層215上，且一閘極金屬217 形成在p型GaN材料216上(即沉積或生長)。在沉積光阻並以任何已知技術，例如電漿蝕刻，蝕刻閘極金屬217及p型GaN材料216後，一隔離區域218接著形成，一絕緣材料219沉積在EPI結構上方。隔離區域218可藉覆蓋裝置層體215之部分，並接著對暴露的層體向下蝕刻，至少到通道層214的下方而形成。蝕刻區域而後可填充氧化物或其他合適隔離材料。
其次，如圖5B所示，使用一接觸光罩蝕刻絕緣材料以形成接觸開口，且沉積接觸金屬以形成源極金屬120、汲極金屬121、及隨意而定的一場板。如同先前所述，接著在結構上沉積一絕緣材料，其於圖5C中再次顯示為絕緣材料219。而後如圖5D所示，一底閘極金屬222沉積於絕緣材料219上，且如圖5E中所示再進行蝕刻。經蝕刻的閘極金屬形成如上述之供多晶矽FET用的底閘極。
製造程序接續來到圖5F，其中閘極絕緣體係為供多晶矽FET用而被沉積。此閘極絕緣體以絕緣材料219表示。其次，一多晶矽層240如圖5G中所示接著被沉積，且接下來如圖5H中所示被蝕刻。在例示性實施例中，多晶矽層240被蝕刻，使層體的剩餘部分形成在閘極金屬222上方。其次，如圖5I所繪示，對多晶矽層實行遮罩及離子佈植步驟，以形成NPN或PNP層。如以上所提，多晶矽層的離子佈植可產生一n型區域223、一p型區域224及一n型區域225(即供裝置之源極、閘極與汲極用的一NPN層)、或可替代地產生一PNP層。
最後，如圖5J所示，一額外介電材料(同樣以介電材料219表示)被沉積，多個通孔於介電材料219中形成，並以諸如鎢(W)、銅(Cu)或類似者的傳導材料填充，且在介電材料219之頂部上形成金屬接點。如同所示，通孔226及227將摻雜區域223及225分別電氣耦合至金屬接點230及231，通孔228將源極金屬220電氣耦合至金屬接點232，而通孔229將汲極金屬221電氣耦合至金屬接點233。圖中雖未顯示，但應了解的是額外金屬層可採如第一實施例且特別是圖3G中所揭示者的類似方式形成。
圖6繪示根據本發明之例示實施例的GaN積體電路之又另一實施例。圖6中所繪示之電路與圖4A中所繪示之具有一底閘極多晶矽裝置結構的GaN積體電路為類似設計。圖6不同在於底閘極使用pGaN層及閘極金屬作為供多晶矽FET用的閘極層來形成，其有效減少製造期間的光罩數量，從以下針對圖7A~7H所描述的例示性方法中將可明顯看出。
如圖6所示，GaN形成在一基體311、一或多個電晶體層312(例如一AlN種層)、一緩衝層313(例如一AlGaN層)、一通道層314及一AlGaN障蔽層315上。此外，一pGaN層316及閘極金屬317在障蔽層315上形成。一額外區域之pGaN層318及閘極金屬319形成在障蔽層上由隔離區域324隔開的區域中。pGaN層318及閘極金屬319形成供多晶矽FET用之閘極層。
而且，源極與汲極金屬325及326在障蔽層315上 形成，而通孔328及327將源極與汲極金屬325及326分別電氣連接至金屬接點333及334。如以上所提，一隔離區域324藉離子佈植或蝕刻在緩衝障蔽層315、通道層314中形成、延伸進入緩衝層313。此裝置更包括電氣絕緣於且保護裝置金屬的一絕緣材料320。此外，多晶矽層在底閘極318、319上方形成。特別是，多晶矽層可包含一n型區域321、一p型區域322及一n型區域323(即用於裝置之源極、閘極與汲極的一NPN層)，但應了解的是此等區域可反過來形成一PNP層。通孔330及329將摻雜區域321及323分別耦合至金屬接點331及332。據此，類似圖4A之例示性裝置，圖6中所示之裝置包括供一多晶矽FET用之一底閘極結構，其置設在電路內與GaN FET之主動胞元隔離的一區域中。雖然圖中未顯示，但應了解的是可形成具有在電路之作用區域中供多晶矽FET用之閘極結構(類似圖4B之實施例)的相同結構，而不是讓閘極結構如圖6所示裝置設置在隔離區域中。
圖7A~7H繪示使用一多晶矽層以如圖6中所示在GaN積體電路中製造裝置的一例示性製造方法。所有程序流程可用以在隔離區域(圖6)或作用區域(圖中未顯示)二者中形成底閘極多晶矽FET。由多晶矽/閘極金屬所形成之背閘極防止2DEG電位在多晶矽FET上的效應。
圖7A繪示一EPI結構，從底部至頂部包括：矽基體311、過渡層312、GaN緩衝材料313、通道層314、及AlGaN障蔽層315。此外，一p型GaN材料316、318形成在障蔽材料315上，且一閘極金屬317、319形成(即沉積或生長)在p 型GaN材料316上。雖圖中未顯示，但這些結構藉沉積一光阻且使用任何習知技術，例如電漿蝕刻，來蝕刻閘極金屬317、319及p型GaN材料316、318而形成。在形成這些結構後，沉積一絕緣層320。
接下來如圖7B中所示，一多晶矽層340被沉積在絕緣層320上，該多晶矽層340而後如圖7C中所示被蝕刻。再者，如圖7D所繪示，對剩下的多晶矽層340實行遮罩及離子佈植的步驟以形成NPN或PNP層。如以上所提，多晶矽層的離子佈植可產生一n型區域321、一p型區域322、及一n型區域323(即用於裝置之源極、閘極與汲極的一NPN層)、或替代性地產生一PNP層。
如圖7E所示，接著有一隔離區域324藉覆蓋裝置層之部分且而後對暴露的層體向下蝕刻，至少到通道層314下方來形成。其次，經蝕刻區域以氧化物或其他合適隔離材料填充。應了解的是，隔離區域324可使用為熟於此技者可了解的任何其他技術來形成，且進一步的是隔離區域324可在程序中的不同階段形成，例如，在步驟7A中絕緣層320被沉積之前。
再者，如圖7F所示，絕緣材料320使用一接觸光罩蝕刻來形成接觸開口，且接觸金屬被沉積以形成源極金屬325、汲極金屬326、及隨意而定的一場板。於沉積一額外絕緣層320(圖7G)後，多個通孔形成於介電材料320中且填充諸如鎢(W)、銅(Cu)或類似者的一傳導材料，且金屬接點在介電材料320頂部上形成。如圖7H所示，通孔330及329 將摻雜區域321及323分別電氣耦合至金屬接點331及332，通孔328將源極金屬325電氣耦合至金屬接點333，且通孔327將汲極金屬326電氣耦合至金屬接點334。圖中雖未顯示，但應了解的是，額外金屬層可採如第一實施例且特別是圖3G中所揭示者的類似方式形成。
圖8繪示根據本發明之GaN積體電路的更另一變化。繪示於圖8中的電路與圖4A中所繪示之具有底閘極多晶矽裝置結構的GaN積體電路為類似設計。圖8不同在於通常用作供金屬1用之障蔽層的金屬層使用作為供多晶矽FET用的底閘極，其有效減少製造期間光罩的數量，從以下關於針對圖9A~9I所描述的例示性方法中將可明顯看出。
如圖8所示，包括一底閘極多晶矽裝置結構的GaN積體電路被提供，且其形成於基體411、一或多個電晶體層412(例如AlN種層)、一緩衝層413(例如AlGaN層)、一通道層414及一AlGaN障蔽層415上。這些層體與參照上述實施例所描述之EPI結構的那些層體類似。
如進一步所示，pGaN層416及閘極金屬417形成在障蔽層415上。源極與汲極金屬422及423形成在障蔽層415上，而通孔428及427將源極與汲極金屬422及423分別電氣耦合至金屬接點433及434。此外，一隔離區域418藉離子佈植或蝕刻在緩衝障蔽層415、通道層414中形成、延伸進入緩衝層413。此裝置更包括電氣絕緣於且保護裝置金屬的絕緣材料419。如同所示，多晶矽FET的一底閘極421形成在絕緣材料中。應了解的是，底閘極421可為一金屬、多晶矽 或其他傳導材料。並且，在此實施例中，金屬層在源極與汲極金屬422及423下方延伸且標示為金屬層420。圖8中之裝置更包括形成在底閘極421上方的一多晶矽層。此多晶矽層可包含一n型區域424、一p型區域425及一n型區域426(即用於裝置之源極、閘極與汲極的一NPN層)，但是應了解的是，這些區域可反過來形成一PNP層。通孔430及429將摻雜區域424及426分別電氣耦合至金屬接點431及432。據此，圖8中所示之裝置包括供一多晶矽FET用之一底閘極結構，其置設在電路內與GaN FET裝置之主動胞元隔離的一區域中。可替代地，多晶矽FET之底閘極421可形成在電路之作用區域中，而不是如圖8中所示裝置設置在隔離區域中。
圖9A~9I繪示使用多晶矽層以製造如圖8中所示之GaN積體電路中的裝置之一例示性製造程序。所有程序流程可用來在作用區域(圖中未顯示)或隔離區域(圖8)兩者中形成底閘極多晶矽FET。由多晶矽/閘極金屬形成的一背閘極防止2DEG電位在多晶矽FET上的效應。
起初，如圖9A所示，一EPI結構被形成，其從底部至頂部包括：矽基體411、過渡層412、GaN緩衝材料413、通道層414及AlGaN障蔽材料415。並且，一p型GaN材料416形成在障蔽材料415上，且一閘極金屬417形成(即沉積或生長)在p型GaN材料416上。在沉積光阻且蝕刻閘極金屬417及p型GaN材料416後，接著形成一隔離區域418，且在EPI結構上方沉積一絕緣材料419。隔離區域418可藉覆蓋裝置 層體415之部分且而後對暴露的層體向下蝕刻，至少到通道層414下方來形成。其次，經蝕刻區域可填充氧化物或其他合適隔離材料。
再者，要位於金屬1下方之一障蔽金屬440被沉積，如圖9B中所示。圖9C繪示下一個步驟，其中障蔽金屬440及絕緣材料419被蝕刻以形成接觸開口，且一接觸金屬441(即金屬1)被沉積以形成源極金屬、汲極金屬、及隨意而定的一場板。如圖9D進一步所示，金屬層441及障蔽金屬440被蝕刻，以形成用於多晶矽FET的源極金屬422、汲極金屬423及障蔽金屬層421。應了解的是，在例示性實施例中，在障蔽金屬層421上方的金屬層被蝕刻掉，但在待形成源極金屬422與汲極金屬423之處沒有被蝕刻。換言之，製造程序必須選擇性地決定那些金屬層欲被蝕刻。
如先前所述，一絕緣材料接著沉積在結構上，其同樣以絕緣材料419顯示於圖9E中，而一多晶矽層442沉積在絕緣材料419上，如圖9F所示。多晶矽層442使用一接觸光罩來蝕刻，使得層體的剩餘部分形成在閘極金屬421上方，如圖9G所示。接著，在圖9H的步驟中，對多晶矽層442實行遮罩及離子佈植步驟以形成NPN或PNP層。如以上所提，多晶矽層的離子佈植可產生一n型區域424、一p型區域425及一n型區域426(即用於裝置之源極、閘極與汲極的一NPN層)，或可替代地產生一PNP層。
最後，如圖9I所示，一額外介電材料被沉積(同樣以介電材料419表示)，多個通孔形成在介電材料419中， 且以諸如鎢(W)、銅(Cu)或類似者的一傳導材料填充，而金屬接點形成在介電材料419頂部。如同所示，通孔430及429分別將摻雜區域424及426電氣耦合至金屬接點431及432，通孔428將源極金屬422電氣耦合至金屬接點433，且通孔427將汲極金屬423電氣耦合至金屬接點434。圖中雖未顯示，但應了解的是，額外金屬層可採如第一實施例且特別是圖3G中所揭示者的類似方式形成。
上述敘述及圖式僅視為達到本文所述之特徵及優點的特定實施例之例示。針對特定程序可做出修改及替換。據此，本發明之實施例並不視為受以上描述及圖式所限制。
110‧‧‧基體
111‧‧‧種層
112‧‧‧AlGaN層
113‧‧‧通道層
114‧‧‧AlGaN障蔽層
115‧‧‧pGaN層
116‧‧‧閘極金屬
118‧‧‧絕緣體/絕緣層
120A‧‧‧源極金屬
120B‧‧‧汲極金屬
120C‧‧‧場板

Claims (17)

  1. 一種製造積體電路之方法，該方法包含：形成用於一增強模式裝置的一閘極結構；在該閘極結構上方沉積一第一絕緣層；在該第一絕緣層上方沉積一多晶矽層；摻雜該多晶矽層，以在該多晶矽層中形成至少一p型區域及至少一n型區域；在該多晶矽層上沉積一第二絕緣層；在該第二絕緣層上形成一金屬層，其透過形成於該第二絕緣層中的至少一通孔而耦合至該多晶矽層的該至少一p型區域。
  2. 如請求項1之方法，其更包含：在至少一緩衝層上方沉積一通道層；及在該通道層上方沉積一障蔽層，其中形成該閘極結構之步驟包含：在該障蔽層上方沉積一p型GaN層；在該p型GaN層上沉積一閘極金屬；在該閘極金屬上方形成一光阻；及蝕刻該閘極金屬及該p型GaN層。
  3. 如請求項1之方法，其中在該第二絕緣層上形成一金屬層之步驟包含形成透過該第二絕緣層中的個別通孔電氣耦合至該多晶矽層之該至少一n型區域的第一金屬互連體、及電氣耦合至該多晶矽層之該至少一p型區域的 一第二金屬互連體。
  4. 如請求項3之方法，其更包含：形成一額外多晶矽層；及在該額外多晶矽層上形成一第三絕緣層。
  5. 如請求項4之方法，其更包含：形成在該第三絕緣層中且電氣耦合至該額外多晶矽層之至少一額外通孔；及形成在該第三絕緣層上且透過該至少一額外通孔電氣耦合至該額外多晶矽層之一金屬接點。
  6. 一種積體電路，其包含：一通道層；置設在該通道層上方的一障蔽層；置設在該障蔽層上的一源極金屬與一汲極金屬；置設在該源極與汲極金屬間的一閘極結構；置設在該源極金屬、該汲極金屬與該閘極結構上方的一絕緣材料；置設在該絕緣材料中的一多晶矽層，該多晶矽層具有至少一p型區域及至少一n型區域；置設在該絕緣材料上的多個金屬互連體；及置設在該絕緣材料之層體中的多個通孔，其分別將該源極金屬、該汲極金屬、及該多晶矽層之該至少一p型區域耦合至該等多個金屬互連體。
  7. 如請求項6之積體電路，其中該等多個通孔中之一第一通孔將該源極金屬 耦合至該等多個金屬互連體中的一第一互連體，而該等多個通孔中之一第二通孔將該多晶矽層之該至少一n型區域電氣耦合至該第一互連體，及其中該等多個通孔中之一第三通孔將該汲極金屬耦合至該等多個金屬互連體中之一第二互連體，而該等多個通孔中之一第四通孔將該多晶矽層之該至少一p型區域電氣耦合至該第二互連體。
  8. 如請求項6之積體電路，其更包含置設在該絕緣材料中的一額外多晶矽層，其中該等多個通孔中之一第一通孔將該源極金屬耦合至該等多個金屬互連體中的一第一互連體，而該等多個通孔中之一第二通孔將該多晶矽層之該至少一n型區域電氣耦合至該第一互連體，及其中該等多個通孔中之一第三通孔將該汲極金屬耦合至該等多個金屬互連體中之一第二互連體，而該等多個通孔中之一第四通孔將該多晶矽層之該至少一p型區域電氣耦合至該第二互連體。
  9. 如請求項6之積體電路，其更包含：一基體；及置設在該基體上方的至少一過渡層，其中該通道層置設在該至少一過渡層上方，且該閘極結構置設在該障蔽層上，及其中該至少一過渡層包含AlGaN，且該通道層包含GaN。
  10. 一種製造積體電路之方法，該方法包含：在至少一緩衝層上方沉積一通道層；在該通道層上方沉積一障蔽層，使得一二維電子氣(2DEG)區域形成在該通道層與該障蔽層間的一介面處；在該障蔽層和該通道層中形成一隔離區域，以將該2DEG區域之一第一部分與該2DEG區域之一第二部分電氣隔離；在該2DEG區域之該第一部分上方形成用於一增強模式裝置的一閘極結構；在該閘極結構上方沉積一第一絕緣層；在該2DEG區域之該第二部分上方形成一背閘極；在該背閘極上方沉積一第二絕緣層；在該第二絕緣層上沉積一多晶矽層，且對該多晶矽層蝕刻，使得經蝕刻的多晶矽層的至少一部分置設在該背閘極上方；摻雜該經蝕刻的多晶矽層，以在該多晶矽層中形成至少一p型區域；在該經蝕刻的多晶矽層上沉積一第三絕緣層；及在該第三絕緣層上形成至少一金屬互連層，其透過形成在該第三絕緣層中的至少一通孔來電氣耦合至該多晶矽層之該至少一p型區域。
  11. 如請求項10之方法，其中在該2DEG區域之該第二部分上方形成背閘極之步驟包含在該第一絕緣層上沉積一閘極金屬並蝕刻該閘極金屬，使得經蝕刻的閘極金屬置 設在該2DEG區域之該第二部分上方。
  12. 如請求項10之方法，其中在該2DEG區域之該第一部分上方形成該閘極結構以及在該2DEG區域之該第二部分上方形成背閘極的步驟包含：在該障蔽層上方沉積一p型GaN層；在該p型GaN層上沉積一閘極金屬；在置設在該2DEG區域之該第一部分上方的該閘極金屬之一第一部分、及在置設在該2DEG區域之該第二部分上方的該閘極金屬之一第二部分上形成一圖案化光阻；及蝕刻該閘極金屬與該p型GaN層。
  13. 如請求項10之方法，其中摻雜該多晶矽層之步驟更包含摻雜該多晶矽層以在該多晶矽層中形成至少一n型區域；及其中摻雜該多晶矽層之步驟更包含形成一第二n型區域或一第二p型區域，使得經摻雜的多晶矽層包含作為一FET裝置之一源極、一閘極與一汲極的一PNP層或一NPN層。
  14. 一種積體電路，其包含：置設在至少一緩衝層上方的一通道層；置設在該通道層上方的一障蔽層，而一二維電子氣(2DEG)區域形成在該通道層與該障蔽層間的一介面處；置設在該障蔽層及該通道層中的一隔離區域，其將該2DEG區域之一第一部分與該2DEG區域之一第二部分電氣隔離； 置設在該2DEG區域之該第一部分上方用於一增強模式裝置的一閘極結構；置設在該閘極結構上方的一第一絕緣層；置設在該2DEG區域之該第二部分上方的一背閘極；置設在該背閘極上方的一第二絕緣層；置設在該第二絕緣層上且在該背閘極上方的一多晶矽層，該多晶矽層包括至少一p型區域；置設在經蝕刻的該多晶矽層上之一第三絕緣層；及置設在該第三絕緣層上的至少一金屬互連層，其透過形成在該第三絕緣層中的至少一通孔電氣耦合至該多晶矽層之該至少一p型區域。
  15. 如請求項14之積體電路，其中該2DEG區域之該第二部分上方的該背閘極置設在該第一絕緣層上。
  16. 如請求項14之積體電路，其中該閘極結構及該背閘極各包含置設在該障蔽層上方的一p型GaN層、及置設在該p型GaN層上的一閘極金屬。
  17. 如請求項14之積體電路，其中該多晶矽層更包含至少一n型區域，及一第二n型區域或一第二p型區域，使得經摻雜之多晶矽層包含作為一FET裝置之一源極、一閘極與一汲極的一PNP層或一NPN層。
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