CN105684134B - 具有用于产生附加构件的多晶硅层的氮化镓晶体管 - Google Patents

具有用于产生附加构件的多晶硅层的氮化镓晶体管 Download PDF

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CN105684134B
CN105684134B CN201480042752.2A CN201480042752A CN105684134B CN 105684134 B CN105684134 B CN 105684134B CN 201480042752 A CN201480042752 A CN 201480042752A CN 105684134 B CN105684134 B CN 105684134B
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layer
metal
region
polysilicon
polysilicon layer
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CN105684134A (zh
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曹建军
罗伯特·比奇
亚历山大·利道
阿兰娜·纳卡塔
赵广元
马艳萍
罗伯特·斯特里特马特
迈克尔·A·德·罗吉
周春华
塞沙德里·科卢里
刘芳昌
蒋明坤
曹佳丽
阿古斯·裘哈尔
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Efficient Power Conversion Corp
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Abstract

本发明系有关具有用以产生用于集成电路的附加构件的多晶硅层的GaN晶体管以及其制造方法。GaN装置包括EPI结构及设置在EPI结构上方的绝缘材料。并且，一个或多个多晶硅层设置在该绝缘材料中，而所述多晶硅层具有一个或多个n型区域及p型区域。此装置还包括设置在该绝缘材料上的金属互连体，及设置在该绝缘材料中的通孔，其将源极与漏极金属连接至该多晶硅层的n型及p型区域。

Description

具有用于产生附加构件的多晶硅层的氮化镓晶体管
技术领域
本发明涉及氮化镓(GaN)装置的领域，并且更具体地，涉及使用一个或多个多晶硅层来制造主动及被动硅装置的GaN集成电路的制造。
背景技术
氮化镓(GaN)半导体装置由于其能以高频切换、承载大电流、且支持高电压的能力而与日俱增地合乎吾人所欲。这些装置的发展普遍针对高功率/高频率应用。针对这些类型应用制作的装置系基于显现高电子迁移率的一般装置结构，且不同地被称作异质接面场效晶体管(HFET)、高电子迁移率晶体管(HEMT)、或调变掺杂场效晶体管(MODFET)。这些类型的装置典型地可忍受例如30V至2000V的高电压，同时在例如100kHz-100GHz的高频下运作。
GaN HEMT装置包括具有至少二氮化层的氮化物半导体。在半导体或在缓冲层上形成不同材料会使层体具有不同带隙(band gaps)。相邻的氮化层中的不同材料亦会造成极化，其造成靠近两层的接面处，特别是在具有较窄带隙的层体中的传导二维电子气(2DEG)区域。
造成极化的氮化层典型包括邻近GaN层的AlGaN阻挡层以包括2DEG，而允许电荷流过装置。此阻挡层可为掺杂或未掺杂的。由于2DEG区域在零栅极偏压下存在于栅极下方，大部分的氮化镓装置系为通常导通或空乏模式装置。若2DEG区域在零施加栅极偏压下于栅极的上被空乏，即移除时，则此装置可为增强模式装置。增强模式装置为通常截止，且由于所提供的附加安全性且它们较易以简单、低成本的驱动电路来控制，故其合于吾人之意。增强模式装置需要在栅极处施加正偏压以传导电流。
图1A至图1H示出了用于制造增强模式(通常截止)GaN晶体管的传统制造程序。如图1A所示，例示性装置藉在由硅(Si)、碳化硅(SiC)或类似物形成的衬底10上先沉积数个层体而形成。特别是，氮化铝(AlN)种层11沉积在衬底10上，氮化镓铝(AlGaN)层12形成在种层11上，且氮化镓(GaN)层13形成在AlGaN层12上。此外，氮化镓铝(AlGaN)阻挡层14形成在GaN层13上，pGaN层15形成在阻挡层14上，且栅极金属16形成在pGaN层15上。如图1A进一步所示，光阻17在栅极金属16上沉积做为保护层，以使用光阻界定栅极图案。
接着，如图1B所示，栅极金属16及pGaN材料15(即晶体)利用作为保护层的光阻17来蚀刻。接下来如图1C及1D中所示，绝缘层或膜18被沉积，且接触开口19A及19B系形成用于源极与漏极接点。再者，沉积第一铝金属以界定金属图案。如图1E所示，金属层可形成源极金属20A、漏极金属20B、及随意而定的场板20C。如图1F中所示，中间层介电质接着沉积。在此范例中，绝缘层18与在图1C中所沉积者为相同材料。
一旦中间层介电质18沉积，如图1G所示，可在金属层间切出通孔22A及22B。此等通孔可填充钨来形成插塞，且可沉积第二铝金属层以形成金属21A及21B。此步骤可如图1H中所示再次实行而形成额外通孔切口24A及24B与额外金属23A及23B。接着可在第三铝金属23A及23B上方沉积钝化层25。图2显示由图1A-1H的程序所形成的GaN结构的扫描式电子显微镜图。
以上图1A-1H中所述的程序的限制在于所制造的装置为在芯片上的单一增强模式装置。第二限制在于上文提及的GaN HEMT装置使用高度传导电子气(2DEG)，而因此为n通道晶体管。然而，由于氮化镓中极不良的电洞迁移率，故难以制造p信道晶体管。此外，亦难以在氮化镓中制造其他类型的硅装置。
据此，吾人会希望有用以形成包括以其他方式难以在氮化镓中制造的硅主动及被动构件的GaN集成电路的方法。
发明内容
本文系揭露包括用以制造用于集成电路的附加构件的GaN晶体管装置及其制造方法。此GaN装置包括EPI结构及设置在EPI结构上方的绝缘材料。此外，一个或多个多晶硅层设置在绝缘材料中，而所述多晶硅层具有一个或多个n型区域及p型区域。此装置还包括设置在绝缘材料上的金属互连部，及设置在绝缘材料中将源极与漏极金属连接至多晶硅层的n型及p型区域的通孔。
一种用以制造GaN晶体管装置的方法包括形成EPI结构，其具有衬底、在该衬底上方的AlGaN层、在该AlGaN层上方的GaN层、在该AlGaN层上方的阻挡层、在该阻挡层上方的p型GaN层；在该p型GaN层上沉积栅极金属；及在该栅极金属上方形成光阻，且蚀刻该栅极金属及该p型GaN层。此方法还包括沉积第一绝缘层；蚀刻该第一绝缘层以在绝缘材料中形成对接触窗；及在该对接触窗中形成源极金属与漏极金属。接着，沉积第二绝缘层且在该第二绝缘层上沉积多晶硅层。在沉积该多晶硅层后，此制造方法还包括下列步骤：掺杂该多晶硅层以在该多晶硅层中形成至少一个n型区域及至少一个p型区域；沉积第三绝缘层且在该第三绝缘层中形成第一多数通孔，所述通孔分别耦合至该源极金属、该漏极金属、该多晶硅层的该至少n型区域、及该多晶硅层的该至少一个p型区域；及在该第三绝缘层上形成金属层。
附图说明
本揭露内容的特征、目的及优点将在结合图式审视以下详细叙述时更为明显看出，图中相同参考符号于全文中系做对应标示，且其中：
图1A-1H绘示用以制造增强模式(常闭)GaN晶体管的传统制造程序。
图2显示由图1A-1H的程序所形成的GaN结构的扫描式电子显微镜图。
图3A-3H绘示根据本发明的第一实施例在GaN集成电路中使用多晶硅层以制造主动及被动硅装置。
图4A及4B绘示根据本发明的例示性实施例的GaN集成电路的额外实施例。
图5A-5J绘示使用多晶硅层以制造如图4A及/或4B中所示在GaN集成电路中的装置的例示性制造程序。
图6绘示根据本发明的GaN集成电路的又另一实施例。
图7A-7H绘示使用多晶硅层来制造如图6中所示在GaN集成电路中的装置的例示性制造程序。
图8绘示根据本发明的例示性实施例的GaN集成电路的又另一变化。
图9A-9I绘示使用多晶硅层来制造如图8中所示在GaN集成电路中的装置的例示性制造程序。
具体实施方式
在以下详细叙述中，某些实施例系为参考。这些实施例采足够详细叙述以使熟悉此技者能够实施它们。将了解的是在本文中所揭露者可采用其他实施例并可做成多种结构的、逻辑的、及电子气的改变，且使用材料的变化来形成集成电路的多种层体。在后附详细叙述中所揭示的特征的多种组合，对于欲以最宽广意义范围来实施本案教示内容，可能非属必要，而反倒仅是用来描述本发明的特定代表范例。
图3A-3H绘示根据本发明的第一实施例使用多晶硅层以在GaN集成电路中制造主动及被动硅装置。
本发明所述的制造方法的第一例示性实施例的初始步骤使用如同以上那些针对图1A-1F所述的GaN晶体管的传统制造技术的相同与相似步骤。特别是，EPI结构包括沉积在衬底上的种层(例如氮化铝(AlN))，其由硅(Si)、碳化硅(SiC)或类似物所形成。并且，一个或多个过渡层(例如氮化镓铝(AlGaN))形成在该种层上，且通道层(例如氮化镓(GaN)层)形成在该AlGaN层上。由氮化镓铝(AlGaN)所组成的阻挡层，例如，接着形成在该通道层上，使得二维电子气(2DEG)形成在该通道层与该阻挡层间的接面处。
在例示性实施例中，为形成栅极，将pGaN层形成在阻挡层上，且将栅极金属形成在该pGaN层上。接着，在该栅极金属上沉积光阻作为保护层以使用该光阻界定栅极图案，且蚀刻该栅极金属及该pGaN材料。而后沉积绝缘层且在该绝缘层中形成接触开口用于源极与漏极接点。再者，沉积铝金属以界定源极金属、漏极金属、及随意而定的场板。其次，中间层介电质沉积在金属接点上。
图3A绘示从这些初步制造步骤所得的结构。如同所示，衬底110从底层至顶层设置有AlN种层111、AlGaN层112、由GaN或类似物组成的通道层113、及形成于其上的AlGaN阻挡层114。此外，由pGaN层115与门极金属116组成的栅极接点形成在AlGaN阻挡层114上，以及形成源极金属120A、漏极金属120B与场板120C。并且，绝缘体118设置在金属接点及阻挡层上方。注意到的是虽然在例示性实施例中(如以上所述)，栅极接点/结构系使用经图案化光阻形成在pGaN层115与门极金属116上方，但栅极接点/结构也可使用熟于此技者可了解的替代方法来形成。例如，栅极结构可为形成在阻挡层114中的凹入栅极，及F-植入(氟植入)栅极、或任何用以形成增强模式装置的其他方法形成者。
接着，如图3B所示，多晶硅层121沉积在绝缘层118上，且杂质被植入以界定具有p型掺杂、n型掺杂及/或没有掺杂的区域。这些区域将形成用于p-n二极管、npn及pnp晶体管、电阻器、电容器、与其他主动及被动组件的基础。于图3B所示的范例中，多晶硅层121包括n型区域121A、p型区域121B、及未掺杂区域121C。其次，使用接触光罩来图案化多晶硅层121并对其蚀刻，如图3C所示。
再者，如图3D所示，绝缘层122接着沉积在多晶硅层121上方。通孔123A-123E而后形成于绝缘层122及绝缘层118(在图3E中合并显示为绝缘层118)中。特别是，通孔123A连接源极金属120A，通孔123B连接漏极金属120B，通孔123C连接n型区域121A，通孔123D连接p型区域121B，且通孔123E连接未掺杂区域121C。在例示性实施例中，可施用钨(W)或铜(Cu)插塞技术来填充较小、较高长宽比的通孔123A-123E，同时利用0.01至0.1m范围厚的TiN薄层用以使多晶硅层121的区域接触。应知，虽然在例示性实施例中使用通孔，但在业界中可采许多共通方式连接金属及多晶硅。
来到图3F，接着沉积金属层以建立互连体，藉此将硅主动及被动构件附加在GaN晶体管上。尤其是，如例示性实施例中所示，金属层124A与通孔123A及123C电气耦合，而第二金属层124B与通孔123B、123D及123E电气耦合。
于改良型态中，如图3G所绘示，额外通孔125A及125B与额外金属层126A及126B亦形成至装置。替代地或附加地，如图3H所示可形成第二多晶硅层。特别是，第二多晶硅层128藉由通孔127耦合至另一金属层126。在例示性实施例中，第二多晶硅层128可被附加以形成n信道及p信道MOSFET。图3H显示二多晶硅层121及128的互连。MOSFET的漏极与源极电极界定于多晶硅层121中，而栅极电极界定于多晶硅层128中。
应了解的是，对于图3A-3H中所绘示的例示性制造方法可做出许多变化及修改。例如，如图3H所示，可由氧化多晶硅及附加金属或多晶硅栅极电极而附加n信道及/或p信道MOS装置。并且，多重多晶硅层可被附加以对多晶硅MOSFET产生诸如多晶硅对多晶硅(poly-poly)电容器的附加构件以与门极。此外，硅构件可被用来针对GaN晶体管产生栅极过电压保护。最后，多晶硅可被用来针对GaN晶体管产生漏极-源极的过电压保护，及/或产生可在相同芯片上与GaN晶体管配合使用的CMOS构件。
图4A及4B绘示根据本发明的例示性实施例的GaN集成电路的额外实施例。尤其是，图4A绘示具有底栅极多晶硅装置结构的GaN集成电路。如同所示，GaN装置形成在衬底211、一个或多个晶体管层212(例如AlN种层)、缓冲层213(例如AlGaN层)、通道层214(例如GaN)及AlGaN阻挡层215上。这些层体与针对第一实施例所述的结构类似。如以上所提，2DEG区域形成在信道层214及缓冲层215的间的接口处。
如进一步所示，pGaN层216与门极金属217形成在阻挡层215上且形成栅极结构。源极与漏极金属220及221形成在阻挡层215上，而通孔228及229将源极与漏极金属220及221分别电气连接至金属接点232及233。并且，隔离区域218通过离子植入或蚀刻于阻挡层215、通道层214中形成，且延伸至缓冲层213中。隔离区域形成在阻挡层中，且信道层将2DEG区域的第一部分与2DEG区域的第二部分电气隔离。此装置还包括电气绝缘且保护装置金属的绝缘材料219。如同所示，多晶硅FET的底栅极222形成在绝缘材料中。注意到的是，底栅极222可为金属、多晶硅或其他传导材料。应了解的是，栅极结构形成在2DEG区域的一部分上方，同时底或背栅极222形成在与第一区域隔离的2DEG区域的第二部分上方。
此外，多晶硅层形成在底栅极上方。特别是，该多晶硅层可包括n型区域223、p型区域224及n型区域225(即用于装置源极、栅极与漏极的NPN层)，但是应了解的是，此等区域可被反过来形成PNP层。通孔226及227分别将掺杂区域223及225耦合至金属接点230及231。据此，图4A中所示的装置包括供多晶硅FET用的底栅极结构，其设置在电路内与GaN FET的主动胞元隔离的区域中。
图4B绘示图4A中所示装置的替代性实施例。图4B中的装置的层体及构件与图4A相同，且将不会在此重述。图4B中所示的装置不同在于多晶硅FET 222形成于电路的作用区域中，而不是如图4A中所示装设置置在隔离区域中。
图5A-5J绘示使用多晶硅层以在如图4A及/或4B中所示的GaN集成电路中制造装置的例示性制造方法。所有的程序流程可用来在作用装置区域(图4B)或在隔离区域(图4A)两者中形成底栅极多晶硅FET。由多晶硅/栅极金属所形成的背栅极防止2DEG电位在多晶硅FET上的效应。
图5A绘示EPI结构，从底部至顶部包括：硅衬底211、过渡层212、缓冲材料213(例如AlGaN)、通道层214(例如GaN)、及障蔽材料215(例如AlGaN)。再者，p型GaN材料216形成在阻挡层215上，且栅极金属217形成在p型GaN材料216上(即沉积或生长)。在沉积光阻并以任何已知技术，例如电浆蚀刻，蚀刻栅极金属217及p型GaN材料216后，隔离区域218接着形成，绝缘材料219沉积在EPI结构上方。隔离区域218可藉覆盖装置层体215的部分，并接着对暴露的层体向下蚀刻，至少到通道层214的下方而形成。蚀刻区域而后可填充氧化物或其他合适隔离材料。
其次，如图5B所示，使用接触光罩蚀刻绝缘材料以形成接触开口，且沉积接触金属以形成源极金属120、漏极金属121、及随意而定的场板。如同先前所述，接着在结构上沉积绝缘材料，其于图5C中再次显示为绝缘材料219。而后如图5D所示，底栅极金属222沉积于绝缘材料219上，且如图5E中所示再进行蚀刻。经蚀刻的栅极金属形成如上述的供多晶硅FET用的底栅极。
制造程序接续来到图5F，其中栅极绝缘体系为供多晶硅FET用而被沉积。此栅极绝缘体以绝缘材料219表示。其次，多晶硅层240如图5G中所示接着被沉积，且接下来如图5H中所示被蚀刻。在例示性实施例中，多晶硅层240被蚀刻，使层体的剩余部分形成在栅极金属222上方。其次，如图5I所绘示，对多晶硅层实行屏蔽及离子布植步骤，以形成NPN或PNP层。如以上所提，多晶硅层的离子布植可产生n型区域223、p型区域224及n型区域225(即供装置的源极、栅极与漏极用的NPN层)、或可替代地产生PNP层。
最后，如图5J所示，额外介电材料(同样以介电材料219表示)被沉积，多个通孔于介电材料219中形成，并以诸如钨(W)、铜(Cu)或类似者的传导材料填充，且在介电材料219的顶部上形成金属接点。如同所示，通孔226及227将掺杂区域223及225分别电气耦合至金属接点230及231，通孔228将源极金属220电气耦合至金属接点232，而通孔229将漏极金属221电气耦合至金属接点233。图中虽未显示，但应了解的是额外金属层可采如第一实施例且特别是图3G中所揭示者的类似方式形成。
图6绘示根据本发明的例示实施例的GaN集成电路的又另一实施例。图6中所绘示的电路与图4A中所绘示的具有底栅极多晶硅装置结构的GaN集成电路为类似设计。图6不同在于底栅极使用pGaN层与门极金属作为供多晶硅FET用的栅极层来形成，其有效减少制造期间的光罩数量，从以下针对图7A-7H所描述的例示性方法中将可明显看出。
如图6所示，GaN形成在衬底311、一个或多个晶体管层312(例如AlN种层)、缓冲层313(例如AlGaN层)、通道层314及AlGaN阻挡层315上。此外，pGaN层316与门极金属317在阻挡层315上形成。额外区域的pGaN层318与门极金属319形成在阻挡层上由隔离区域324隔开的区域中。pGaN层318与门极金属319形成供多晶硅FET用的栅极层。
而且，源极与漏极金属325及326在阻挡层315上形成，而通孔328及327将源极与漏极金属325及326分别电气连接至金属接点333及334。如以上所提，隔离区域324藉离子布植或蚀刻在缓冲阻挡层315、通道层314中形成、延伸进入缓冲层313。此装置还包括电气绝缘于且保护装置金属的绝缘材料320。此外，多晶硅层在底栅极318、319上方形成。特别是，多晶硅层可包括n型区域321、p型区域322及n型区域323(即用于装置的源极、栅极与漏极的NPN层)，但应了解的是此等区域可反过来形成PNP层。通孔330及329将掺杂区域321及323分别耦合至金属接点331及332。据此，类似图4A的例示性装置，图6中所示的装置包括供多晶硅FET用的底栅极结构，其设置在电路内与GaN FET的主动胞元隔离的区域中。虽然图中未显示，但应了解的是可形成具有在电路的作用区域中供多晶硅FET用的栅极结构(类似图4B的实施例)的相同结构，而不是让栅极结构如图6所示装设置置在隔离区域中。
图7A-7H绘示使用多晶硅层以如图6中所示在GaN集成电路中制造装置的例示性制造方法。所有程序流程可用以在隔离区域(图6)或作用区域(图中未显示)二者中形成底栅极多晶硅FET。由多晶硅/栅极金属所形成的背栅极防止2DEG电位在多晶硅FET上的效应。
图7A绘示EPI结构，从底部至顶部包括：硅衬底311、过渡层312、GaN缓冲材料313、通道层314、及AlGaN阻挡层315。此外，p型GaN材料316、318形成在障蔽材料315上，且栅极金属317、319形成(即沉积或生长)在p型GaN材料316上。虽图中未显示，但这些结构藉沉积光阻且使用任何习知技术，例如电浆蚀刻，来蚀刻栅极金属317、319及p型GaN材料316、318而形成。在形成这些结构后，沉积绝缘层320。
接下来如图7B中所示，多晶硅层340被沉积在绝缘层320上，该多晶硅层340而后如图7C中所示被蚀刻。再者，如图7D所绘示，对剩下的多晶硅层340实行屏蔽及离子布植的步骤以形成NPN或PNP层。如以上所提，多晶硅层的离子布植可产生n型区域321、p型区域322、及n型区域323(即用于装置的源极、栅极与漏极的NPN层)、或替代性地产生PNP层。
如图7E所示，接着有隔离区域324藉覆盖装置层的部分且而后对暴露的层体向下蚀刻，至少到通道层314下方来形成。其次，经蚀刻区域以氧化物或其他合适隔离材料填充。应了解的是，隔离区域324可使用为熟于此技者可了解的任何其他技术来形成，且进一步的是隔离区域324可在程序中的不同阶段形成，例如，在步骤7A中绝缘层320被沉积的前。
再者，如图7F所示，绝缘材料320使用接触光罩蚀刻来形成接触开口，且接触金属被沉积以形成源极金属325、漏极金属326、及随意而定的场板。于沉积额外绝缘层320(图7G)后，多个通孔形成于介电材料320中且填充诸如钨(W)、铜(Cu)或类似者的传导材料，且金属接点在介电材料320顶部上形成。如图7H所示，通孔330及329将掺杂区域321及323分别电气耦合至金属接点331及332，通孔328将源极金属325电气耦合至金属接点333，且通孔327将漏极金属326电气耦合至金属接点334。图中虽未显示，但应了解的是，额外金属层可采如第一实施例且特别是图3G中所揭示者的类似方式形成。
图8绘示根据本发明的GaN集成电路的又一变化。绘示于图8中的电路与图4A中所绘示的具有底栅极多晶硅装置结构的GaN集成电路为类似设计。图8不同在于通常用作供金属1用的阻挡层的金属层使用作为供多晶硅FET用的底栅极，其有效减少制造期间光罩的数量，从以下关于针对图9A-9I所描述的例示性方法中将可明显看出。
如图8所示，包括底栅极多晶硅装置结构的GaN集成电路被提供，且其形成于衬底411、一个或多个晶体管层412(例如AlN种层)、缓冲层413(例如AlGaN层)、通道层414及AlGaN阻挡层415上。这些层体与参照上述实施例所描述的EPI结构的那些层体类似。
如进一步所示，pGaN层416与门极金属417形成在阻挡层415上。源极与漏极金属422及423形成在阻挡层415上，而通孔428及427将源极与漏极金属422及423分别电气耦合至金属接点433及434。此外，隔离区域418藉离子布植或蚀刻在缓冲阻挡层415、通道层414中形成、延伸进入缓冲层413。此装置还包括电气绝缘于且保护装置金属的绝缘材料419。如同所示，多晶硅FET的底栅极421形成在绝缘材料中。应了解的是，底栅极421可为金属、多晶硅或其他传导材料。并且，在此实施例中，金属层在源极与漏极金属422及423下方延伸且标示为金属层420。图8中的装置还包括形成在底栅极421上方的多晶硅层。此多晶硅层可包括n型区域424、p型区域425及n型区域426(即用于装置的源极、栅极与漏极的NPN层)，但是应了解的是，这些区域可反过来形成PNP层。通孔430及429将掺杂区域424及426分别电气耦合至金属接点431及432。据此，图8中所示的装置包括供多晶硅FET用的底栅极结构，其设置在电路内与GaN FET装置的主动胞元隔离的区域中。可替代地，多晶硅FET的底栅极421可形成在电路的作用区域中，而不是如图8中所示装设置置在隔离区域中。
图9A-9I绘示使用多晶硅层以制造如图8中所示的GaN集成电路中的装置的例示性制造程序。所有程序流程可用来在作用区域(图中未显示)或隔离区域(图8)两者中形成底栅极多晶硅FET。由多晶硅/栅极金属形成的背栅极防止2DEG电位在多晶硅FET上的效应。
起初，如图9A所示，EPI结构被形成，其从底部至顶部包括：硅衬底411、过渡层412、GaN缓冲材料413、通道层414及AlGaN障蔽材料415。并且，p型GaN材料416形成在障蔽材料415上，且栅极金属417形成(即沉积或生长)在p型GaN材料416上。在沉积光阻且蚀刻栅极金属417及p型GaN材料416后，接着形成隔离区域418，且在EPI结构上方沉积绝缘材料419。隔离区域418可藉覆盖装置层体415的部分且而后对暴露的层体向下蚀刻，至少到通道层414下方来形成。其次，经蚀刻区域可填充氧化物或其他合适隔离材料。
再者，要位于金属1下方的障蔽金属440被沉积，如图9B中所示。图9C绘示下一个步骤，其中障蔽金属440及绝缘材料419被蚀刻以形成接触开口，且接触金属441(即金属1)被沉积以形成源极金属、漏极金属、及随意而定的场板。如图9D进一步所示，金属层441及障蔽金属440被蚀刻，以形成用于多晶硅FET的源极金属422、漏极金属423及障蔽金属层421。应了解的是，在例示性实施例中，在障蔽金属层421上方的金属层被蚀刻掉，但在待形成源极金属422与漏极金属423的处没有被蚀刻。换言的，制造程序必须选择性地决定那些金属层欲被蚀刻。
如先前所述，绝缘材料接着沉积在结构上，其同样以绝缘材料419显示于图9E中，而多晶硅层442沉积在绝缘材料419上，如图9F所示。多晶硅层442使用接触光罩来蚀刻，使得层体的剩余部分形成在栅极金属421上方，如图9G所示。接着，在图9H的步骤中，对多晶硅层442实行屏蔽及离子布植步骤以形成NPN或PNP层。如以上所提，多晶硅层的离子布植可产生n型区域424、p型区域425及n型区域426(即用于装置的源极、栅极与漏极的NPN层)，或可替代地产生PNP层。
最后，如图9I所示，额外介电材料被沉积(同样以介电材料419表示)，多个通孔形成在介电材料419中，且以诸如钨(W)、铜(Cu)或类似者的传导材料填充，而金属接点形成在介电材料419顶部。如同所示，通孔430及429分别将掺杂区域424及426电气耦合至金属接点431及432，通孔428将源极金属422电气耦合至金属接点433，且通孔427将漏极金属423电气耦合至金属接点434。图中虽未显示，但应了解的是，额外金属层可采如第一实施例且特别是图3G中所揭示者的类似方式形成。
上述叙述及图式仅视为达到本文所述的特征及优点的特定实施例的例示。针对特定程序可做出修改及替换。据此，本发明的实施例并不视为受以上描述及图式所限制。

Claims (15)

1.一种制造集成电路的方法，该方法包括：
形成用于增强模式装置的栅极结构；
在该栅极结构上方沉积第一绝缘层；
在该第一绝缘层上方沉积多晶硅层；
掺杂该多晶硅层，以在该多晶硅层中形成至少p型区域；
在该多晶硅层上沉积第二绝缘层；
在该第二绝缘层上形成金属层，其通过形成于该第二绝缘层中的至少一个通孔而耦合至该多晶硅层的该至少一个p型区域；
其中掺杂多晶硅层的步骤还包括掺杂该多晶硅层以在该多晶硅层中形成至少一个n型区域；并且
其中在该第二绝缘层上形成金属层的步骤包括形成通过该第二绝缘层中的个别通孔电气耦合至该多晶硅层的该至少一个n型区域的第一金属互连体、及电气耦合至该多晶硅层的该至少一个p型区域的第二金属互连体。
2.如权利要求1所述的方法，还包括：
在至少一个缓冲层上方沉积通道层；及
在该通道层上方沉积阻挡层，其中形成该栅极结构的步骤包括：
在该阻挡层上方沉积p型GaN层；
在该p型GaN层上沉积栅极金属；
在该栅极金属上方形成光阻；以及
蚀刻该栅极金属及该p型GaN层。
3.如权利要求1所述的方法，还包括：
形成额外多晶硅层；及
在该额外多晶硅层上形成第三绝缘层。
4.如权利要求3所述的方法，还包括：
形成在该第三绝缘层中且电气耦合至该额外多晶硅层的至少一个额外通孔；及
形成在该第三绝缘层上且通过该至少一个额外通孔电气耦合至该额外多晶硅层的金属接点。
5.一种集成电路，其包括：
通道层；
设置在该通道层上方的阻挡层；
设置在该阻挡层上的源极金属与漏极金属；
设置在该源极与漏极金属间的栅极结构；
设置在该源极金属、该漏极金属与该栅极结构上方的绝缘材料；
设置在该绝缘材料中的多晶硅层，该多晶硅层具有至少一个p型区域；
设置在该绝缘材料上的多个金属互连体；及
设置在该绝缘材料的层体中的多个通孔，其分别将该源极金属、该漏极金属、及该多晶硅层的该至少一个p型区域耦合至所述多个金属互连体；
其中该多晶硅层还具有至少一个n型区域，且其中所述多个通孔中的第一通孔将该源极金属耦合至所述多个金属互连体中的第一互连体，而所述多个通孔中的第二通孔将该多晶硅层的该至少一个n型区域电气耦合至该第一互连体，及
其中所述多个通孔中的第三通孔将该漏极金属耦合至所述多个金属互连体中的第二互连体，而所述多个通孔中的第四通孔将该多晶硅层的该至少一个p型区域电气耦合至该第二互连体。
6.如权利要求5所述的集成电路，还包括设置在该绝缘材料中的额外多晶硅层，
其中所述多个通孔中的第一通孔将该源极金属耦合至所述多个金属互连体中的第一互连体，而所述多个通孔中的第二通孔将该多晶硅层的该至少一个n型区域电气耦合至该第一互连体，及
其中所述多个通孔中的第三通孔将该漏极金属耦合至所述多个金属互连体中的第二互连体，而所述多个通孔中的第四通孔将该多晶硅层的该至少一个p型区域电气耦合至该第二互连体。
7.如权利要求5所述的集成电路，还包括：
衬底；及
设置在该衬底上方的至少一个过渡层，
其中该通道层设置在该至少一个过渡层上方，且该栅极结构设置在该阻挡层上，及
其中该至少一个过渡层包括AlGaN，且该通道层包括GaN。
8.一种制造集成电路的方法，该方法包括：
在至少一个缓冲层上方沉积通道层；
在该通道层上方沉积阻挡层，使得二维电子气(2DEG)区域形成在该通道层与该阻挡层间的接口处；
在该阻挡层和该通道层中形成隔离区域，以将该2DEG区域的第一部分与该2DEG区域的第二部分电气隔离；
在该2DEG区域的该第一部分上方形成用于增强模式装置的栅极结构；
在该栅极结构上方沉积第一绝缘层；
在该2DEG区域的该第二部分上方形成背栅极；
在该背栅极上方沉积第二绝缘层；
在该第二绝缘层上沉积多晶硅层，且对该多晶硅层蚀刻，使得经蚀刻的多晶硅层的至少一部分设置在该背栅极上方；
掺杂该经蚀刻的多晶硅层，以在该多晶硅层中形成至少一个p型区域；
在该经蚀刻的多晶硅层上沉积第三绝缘层；及
在该第三绝缘层上形成至少一个金属互连层，其通过形成在该第三绝缘层中的至少一个通孔来电气耦合至该多晶硅层的该至少一个p型区域。
9.如权利要求8所述的方法，其中在该2DEG区域的该第二部分上方形成背栅极的步骤包括在该第一绝缘层上沉积栅极金属并蚀刻该栅极金属，使得经蚀刻的栅极金属设置在该2DEG区域的该第二部分上方。
10.如权利要求8所述的方法，其中在该2DEG区域的该第一部分上方形成该栅极结构以及在该2DEG区域的该第二部分上方形成背栅极的步骤包括：
在该阻挡层上方沉积p型GaN层；
在该p型GaN层上沉积栅极金属；
在设置在该2DEG区域的该第一部分上方的该栅极金属的第一部分、及在设置在该2DEG区域的该第二部分上方的该栅极金属的第二部分上形成图案化光阻；及
蚀刻该栅极金属与该p型GaN层。
11.如权利要求8所述的方法，
其中掺杂该多晶硅层的步骤还包括掺杂该多晶硅层以在该多晶硅层中形成至少一个n型区域；及
其中掺杂该多晶硅层的步骤还包括形成第二n型区域或第二p型区域，使得经掺杂的多晶硅层包括作为FET装置的源极、栅极与漏极的PNP层或NPN层。
12.一种集成电路，其包括：
设置在至少一个缓冲层上方的通道层；
设置在该通道层上方的阻挡层，而二维电子气(2DEG)区域形成在该通道层与该阻挡层间的接口处；
设置在该阻挡层及该通道层中的隔离区域，其将该2DEG区域的第一部分与该2DEG区域的第二部分电气隔离；
设置在该2DEG区域的该第一部分上方用于增强模式装置的栅极结构；
设置在该栅极结构上方的第一绝缘层；
设置在该2DEG区域的该第二部分上方的背栅极；
设置在该背栅极上方的第二绝缘层；
设置在该第二绝缘层上且在该背栅极上方的多晶硅层，该多晶硅层包括至少一个p型区域；
设置在经蚀刻的该多晶硅层上的第三绝缘层；及
设置在该第三绝缘层上的至少一个金属互连层，其通过形成在该第三绝缘层中的至少一个通孔电气耦合至该多晶硅层的该至少一个p型区域。
13.如权利要求12所述的集成电路，其中该2DEG区域的该第二部分上方的该背栅极设置在该第一绝缘层上。
14.如权利要求12所述的集成电路，其中该栅极结构及该背栅极各包括设置在该阻挡层上方的p型GaN层、及设置在该p型GaN层上的栅极金属。
15.如权利要求12所述的集成电路，其中该多晶硅层还包括至少一个n型区域，及第二n型区域或第二p型区域，使得经掺杂的多晶硅层包括作为FET装置的源极、栅极与漏极的PNP层或NPN层。
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