TWI449175B - 雙通道溝槽ldmos電晶體和bcd方法 - Google Patents

雙通道溝槽ldmos電晶體和bcd方法 Download PDF

Info

Publication number
TWI449175B
TWI449175B TW099141739A TW99141739A TWI449175B TW I449175 B TWI449175 B TW I449175B TW 099141739 A TW099141739 A TW 099141739A TW 99141739 A TW99141739 A TW 99141739A TW I449175 B TWI449175 B TW I449175B
Authority
TW
Taiwan
Prior art keywords
trench
gate
region
metal oxide
oxide semiconductor
Prior art date
Application number
TW099141739A
Other languages
English (en)
Other versions
TW201133856A (en
Inventor
Shekar Mallikarjunaswamy
Original Assignee
Alpha & Omega Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Publication of TW201133856A publication Critical patent/TW201133856A/zh
Application granted granted Critical
Publication of TWI449175B publication Critical patent/TWI449175B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

雙通道溝槽LDMOS電晶體和BCD方法
本發明涉及高壓半導體裝置及其製備過程，尤其是具有平面通道和溝槽通道的LDMOS電晶體，以及在BCD(雙極CMOS和DMOS)製備過程中的溝槽隔離。
橫向雙擴散金屬氧化物半導體(Lateral double-diffused metal-oxide-semiconductor，簡稱LDMOS)電晶體憑藉其高擊穿電壓的特點以及在低壓裝置中與互補金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor，簡稱CMOS)技術的相容性，通常用於高壓裝置(20至500伏)。一般來說，一個LDMOS電晶體包括一個多晶矽柵極、一個形成在P-型本體區中形成的N+源極區以及一個N+漏極區。N+漏極區與一個N漂移區在體區域形成的通道隔開，位於多晶矽柵極之下。眾所周知，通過增大N漂移區的長度，可以相應地提高LDMOS電晶體的擊穿電壓。
雙極-CMOS-DMOS(Bipolar-CMOS-DMOS，簡稱BCD)方法技術是指，將雙極裝置、互補MOS(CMOS)裝置和DMOS裝置納入到一個單一制備方法流程中的半導體製備方法。一般而言，雙極裝置適用於類比電路，CMOS裝置適用於數位電路，DMOS裝置適用於管理片上或系統電源時處理高壓和電流的要求。因此，BCD方法常用於 生產製造高壓混合信號積體電路或類比片上系統應用，以及在無線掌上型電子設備和消費類電子產品中的特殊應用。
依據本發明的一個實施例，雙通道溝槽LDMOS電晶體包括一個第一導電類型的襯底；一個形成在襯底上的第二導電類型的半導體層；一個形成在半導體層中的第一溝槽，用溝槽電介質填充第一溝槽，並在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；一個形成在第一溝槽附近半導體層中的第一導電類型的本體區；一個形成在本體區中第一溝槽附近的第二導電類型的源極區；一個通過第二柵極介質層與半導體層絕緣的平面柵極，加在本體區上，所形成的源極區與平面柵極的第一邊緣對齊；一個形成在半導體層中的第二導電類型的漏極區，漏極漂移區將漏極區和本體區間隔開來。平面柵極構成在源極區和漏極漂移區之間的本體區中的LDMOS電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成LDMOS電晶體的垂直通道。
具體而言，本發明提供一種雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，包括：一個第一導電類型的襯底；一個形成在襯底上的第二導電類型的半導體層；一個形成在半導體層中的第一溝槽，用溝槽電介質填充第一溝槽，並在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；一個形成在第一溝槽附近半導體層中的第一導電類型的本體區； 一個形成在本體區中，第一溝槽附近的第二導電類型的源極區；一個通過第二柵極介質層與半導體層絕緣的平面柵極，加在本體區上，所形成的源極區與平面柵極的第一邊緣對齊；以及一個形成在半導體層中的第二導電類型的漏極區，漏極漂移區將漏極區和本體區間隔開來；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第一溝槽僅僅延伸到半導體層中。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第一溝槽穿過半導體層延伸到襯底中，溝槽柵極形成在第一溝槽的上部。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括：一個形成在第一溝槽下部的底部柵極電極，通過具有第二厚度的溝槽電介質，與第一溝槽的側壁絕緣，第二厚度大於使溝槽柵極絕緣的第一柵極介質層的厚度，底部柵極電極電接觸到源極電勢上。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括：一個形成在半導體層中，並延伸到襯底中的第二溝槽，用溝槽電介質填充第二溝槽，其中第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括一個溝槽柵極，形成在第二溝槽的上部，通過第三柵極介質層，與第二溝槽的側壁絕緣，溝槽柵極處於電浮動狀態或電連接到指定電勢上，以便使第二溝槽中的溝槽柵極無效。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中第三柵極介質層的厚度大於第一柵極介質層的厚度。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括：一個形成在半導體層中，並延伸到襯底中的第二溝槽，用溝槽電介質填充第二溝槽，一個形成在第二溝槽的上部，通過第三柵極介質層，與第二溝槽的側壁絕緣的溝槽柵極，以及一個形成在第二溝槽的下部，通過溝槽電介質，與第二溝槽的側壁絕緣的底部柵極電極，溝槽電介質的厚度大於第三柵極介質層的厚度，溝槽柵極處於電浮動狀態或電連接到指定電勢上，以便使第二溝槽中的溝槽柵極無效，底部柵極電極電連接到源極電勢上；其中第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第三柵極介質層的厚度大於第一柵極介質層的厚度。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，漏極漂移區包括一個形成在半導體層中的第二導電類型的阱。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，漏極漂移區包括多個形成在半導體層中的第二導電類型的阱，這多個阱具有不同的摻雜濃度等級。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括形成在平面柵極和漏極區之間的半導體層表面上或表面中的場氧化層或一步氧化層，平面柵極的第二邊緣延伸到一部分場氧化層的上方或一步氧化層的上方。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，半導體層含有一個第二導電類型的外延層。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第二半導體層還包括一個形成在襯底上的第二導電類型的掩埋層，外延層形成在掩埋層上。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括多個形成在漏極漂移區中的溝槽叉指，用溝槽電介質填充多個溝槽叉指，多個溝槽叉指形成相互交錯的溝槽和漏極區，溝槽柵極形成在每個溝槽叉指的上部，並通過第三柵極介質層，與溝槽叉指的側壁絕緣，溝槽柵極電連接到源極電勢上。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第三柵極介質層的厚度大於第一柵極介質層的厚度。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第一溝槽包括相互交錯的溝槽區，這些溝槽區延伸到源極區和本體區中，形成溝槽柵極的延伸物。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括：一個位於源極區的本體接觸區，以便電接觸到本體區。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，第一導電類型為P-型，第二導電類型為N-型。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，還包括：多個形成在漏極漂移區中的交替的N-型和P-型區，這多個交替的N-型和P-型區的摻雜濃度高於漏極漂移區的摻雜濃度，在漏極漂移區構成一個超級結結構。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，多個交替的N-型和P-型區包括第一N-型區、第二N-型區以及夾在第一和第二N-型區之間的P-型區，第一和第二N-型區自對準到平面柵極的第二邊緣上，P-型區延伸到本體區。
上述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，多個交替的N-型和P-型區包括第一P-型區、第二P-型區以及夾在第一和第二P-型區之間的N-型區，第一和第二N-型區自對準到平面柵極的第二邊緣上。
本發明還提供一種用於製備雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體的方法，包括：製備一個第一導電類型的襯底；在襯底上形成一個第二導電類型的半導體層；在半導體層中形成一個第一溝槽，用溝槽電介質填充第一溝槽；在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；在半導體層中第一溝槽附近形成一個第一導電類型的本體區；在本體區中第一溝槽附近形成一個第二導電類型的源極區；形成第二柵極介質層，覆蓋在本體區上，在第二柵極介質層上形成一個與半導體層絕緣的平面柵極，形成源極區與平面柵極的第一邊緣對 齊；以及在半導體層中形成一個第二導電類型的漏極區，漏極漂移區將漏極區和本體區間隔開來；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
上述的方法，還包括：在半導體層中製備第二溝槽，並延伸到襯底中，用溝槽電介質填充第二溝槽，第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
本發明還提供一種由垂直溝槽橫向雙擴散金屬氧化物半導體電晶體構成的半導體裝置，垂直溝槽橫向雙擴散金屬氧化物半導體電晶體包括：一個第一導電類型的襯底；一個形成在襯底上的第一導電類型的半導體層；一個形成在半導體層中的第一溝槽，用溝槽電介質填充第一溝槽，並在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；一個形成在半導體層中第一溝槽附近的第二導電類型的本體區；一個形成在本體區中第一溝槽附近的第一導電類型的源極區；一個通過第二柵極介質層與半導體層絕緣的平面柵極，加在本體區上，所形成的源極區與平面柵極的第一邊緣對齊；一個形成在半導體層中的第一導電類型的漏極漂移區；以及 一個形成在襯底背部的漏極電極；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
上述的由垂直溝槽橫向雙擴散金屬氧化物半導體電晶體構成的半導體裝置，還包括一個形成在相同襯底的獨立區域和相同的半導體層中的垂直溝槽MOS電晶體，該垂直溝槽MOS電晶體包括：一個形成在半導體層中的第二溝槽，用溝槽電介質填充第二溝槽，第二溝槽柵極形成在第二溝槽中，通過第二柵極介質層，與第二溝槽的側壁絕緣；一個形成在第二溝槽附近的半導體層中的第二導電類型的第二本體區，第二本體區延伸到形成在第二溝槽中的第二溝槽柵極的底部邊緣附近的深度；以及一個形成在本體區中的、鄰近第二溝槽的第一導電類型的源極區，源極區形成在本體區的頂部；其中所形成的垂直溝槽MOS電晶體中，襯底作為垂直溝槽MOS電晶體的漏極區，半導體層作為漏極漂移區，第二溝槽柵極作為柵極電極。
閱讀以下詳細說明及附圖之後，將更好地理解本發明。
10、100、250、300、350‧‧‧溝槽LDMOS電晶體
34、36‧‧‧金屬接頭
35‧‧‧絕緣介質層
24、224‧‧‧N+漏極區
28b、28、128b、128、228、228b、262、378、428、528、828‧‧‧溝槽柵極
30b、130、230、230b、330、380、430‧‧‧溝槽
38‧‧‧P-型通道終止區
12、412、912‧‧‧P-型襯底
14、NBL、414、814‧‧‧N-型掩埋層
18、HVNW、518、618‧‧‧高壓N-阱
20、LVNW‧‧‧低壓N-阱
32‧‧‧場氧化層
26、226、426、526、626、726‧‧‧平面柵極
25‧‧‧薄柵極氧化層
23、223、323、723、823‧‧‧N+源極區
22‧‧‧P-型本體區
16、216、416、816‧‧‧N-型外延層
30、930B、930C‧‧‧深溝槽
140‧‧‧底部柵極電極
200、500、600、700‧‧‧雙通道溝槽LDMOS電晶體
242、370‧‧‧P+本體接觸區
260‧‧‧溝槽叉指
390‧‧‧P+島
470、NPN‧‧‧雙極結型電晶體
410‧‧‧LDMOS電晶體
450、NMOS‧‧‧N-型金屬氧化物半導體電晶體
460、PMOS‧‧‧P-型金屬氧化物半導體電晶體
422、522、822‧‧‧低壓P-阱
421‧‧‧高壓P-阱
595、597‧‧‧曲線
590‧‧‧第一N-型區
592‧‧‧P-型區
594‧‧‧第二N-型區
690‧‧‧第一P-型區
694‧‧‧第二P-型區
692‧‧‧N-型區
724‧‧‧漏極區
712、812‧‧‧N+襯底
728‧‧‧垂直柵極
800‧‧‧垂直溝槽MOS電晶體
824‧‧‧漏極電極
818‧‧‧P+本體接頭
819‧‧‧源極金屬
930A‧‧‧淺溝槽
第1圖表示依據本發明的第一實施例，一個雙通道溝槽LDMOS電晶體的橫截面視圖。
第2圖表示依據本發明的第二實施例，一個雙通道溝槽LDMOS電 晶體的橫截面視圖。
第3圖表示依據本發明的第三實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。
第4圖表示依據本發明的第四實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。
第5圖表示依據本發明的第五實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。
第6圖表示依據本發明的第六實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。
第7圖表示依據本發明的一個實施例，利用BCD方法，採用深溝槽隔離技術製成的電晶體裝置的橫截面視圖。
第8圖表示依據本發明的另一個實施例，利用BCD方法，採用深溝槽隔離技術製成的電晶體裝置的橫截面視圖。
第9圖表示依據本發明的一個實施例，一個採用漏極超級結結構的雙通道溝槽LDMOS電晶體的橫截面視圖。
第10圖表示第9圖所示的LDMOS晶體管帶有或不帶有超級結結構時的電場分佈。
第11圖表示依據本發明的一個可選實施例，一個採用漏極超級結結構的雙通道溝槽LDMOS電晶體的橫截面視圖。
第12圖表示依據本發明的另一個實施例，一個採用底部漏極的雙通道溝槽LDMOS電晶體的橫截面視圖。
第13圖表示依據本發明的一個實施例，一個可以與雙通道裝置集成的垂直溝槽MOS電晶體的橫截面視圖。
第14圖表示依據本發明的一個可選實施例，利用BCD方法，採用 深溝槽隔離技術製成的電晶體裝置的橫截面視圖。
按照本發明的原理，BCD(雙極-CMOS-DMOS)製備方法將填充氧化物的深溝槽與單一或堆積式柵極合併，作為深溝槽隔離技術使用，並用於有源柵極。在一些實施例中，將溝槽柵極用作垂直溝槽，將平面柵極用作橫向通道，來製備雙通道溝槽LDMOS。在其他實施例中，底部柵極電極電連接到源極電勢上，以增強對所形成裝置的遮罩，並提高其擊穿承受能力。在其他實施例中，超級結結構形成在LDMOS電晶體的漏極漂移區中，以降低漏極漂移區中的漏極電阻，並提高擊穿電壓。
通過使用帶有溝槽柵極結構的深溝槽隔離技術，實現了低成本、高性能的BCD方法。根據本發明所述的BCD方法，可以節省多個掩膜，從而減少製備方法的步驟和複雜性。帶有深溝槽隔離技術的BCD方法也實現了緊湊隔離，緊湊隔離與重摻雜的N-型掩埋層(NBL)一起，降低了寄生PNP增益，從而提高對閉鎖的免疫能力。通過深溝槽隔離技術，以及利用在深溝槽底部的P通道阻絕植入，可以降低橫向NPN增益。
由於雙通道LDMOS電晶體的兩個通道形成在傳統LDMOS電晶體的同一區域中，實現了更高的通道密度。因此，LDMOS電晶體的通道電阻(Rds*A)降低了一半。利用LDMOS電晶體中的垂直和橫向通道，LDMOS電晶體的導通電阻降低了，LDMOS電晶體的性能得以提高。
當本發明所述的LDMOS電晶體在漏極區引入超級結結構時，電晶體的通道電阻(Rds*A)會進一步降低。在一個實施例中， LDMOS的總電阻(Rds*A)降低了70%以上。
(1)雙通道溝槽LDMOS
依據本發明的一個方面，雙通道溝槽LDMOS包括一個形成橫向通道的平面柵極以及一個形成垂直通道的有源溝槽柵極。溝槽柵極形成在深氧化物填充的溝槽中，深氧化物填充的溝槽也可以用於LDMOS電晶體或相同方法製備的其他裝置的高壓隔離。LDMOS電晶體的溝槽柵極形成一個遮罩柵極溝槽(SGT)結構，實現了每個單位面積上較低的柵極至漏極電容，並提升了擊穿性能。
在本發明的一些實施例中，通過將單一的淺溝槽柵極用作LDMOS電晶體的有源柵極，來製備雙通道溝槽LDMOS電晶體。在其他實施例中，在溝槽中形成一個堆積式柵極結構，其底部柵極形成一個連接到源極電壓上的電極，用於漏極區中的超級結效應，並提供遮罩。
(a)單一的有源柵極
第1圖表示依據本發明的第一實施例，一個雙通道溝槽LDMOS電晶體的橫截面視圖。參見第1圖，溝槽LDMOS電晶體10形成在P-型襯底12上，N一型掩埋層(N-type buried layer，簡稱NBL)14形成在溝槽LDMOS電晶體10上。N-型外延層16形成在掩埋層14上，電晶體的有源區就形成在掩埋層14中。N-型掩埋層14是可選的，通常選用它是為了改善裝置的隔離性能和免除閉鎖。在其他實施例中，可以省略N-型掩埋層14。可以通過標準的掩埋層植入方法或一步外延方法，形成NBL14。也就是說，首先在P襯底12上方生長一個重摻雜的N-型外延層，作為NBL14，然後在外延形成的NBL14上方生長一個比NBL14摻雜濃度輕的N-型外延層16。在本說明中，N-外延層16、N 掩埋層14以及襯底12有時都稱為“半導體層”。
深溝槽30形成在N-外延層16中，N-掩埋層14形成在襯底12中。用電介質材料填充溝槽30。在本實施例中，是用氧化矽填充溝槽30，因此稱為“填充氧化物的溝槽”。在其他實施例中，也可使用其他電介質材料填充溝槽30。另外，溝槽柵極28形成在溝槽30的上部。在本實施例中，溝槽柵極28為多晶矽柵極。在其他實施例中，也可使用其他導電柵極材料。溝槽柵極28通過一個柵極介質層，與溝槽的側壁絕緣。其特點是，所形成的柵極介質層與溝槽氧化物分離開來，以獲得較高品質的氧化物。更確切地說，其特點是，利用熱氧化，在溝槽側壁上形成柵極介質層。這樣一來，填充氧化物的溝槽30構成了溝槽LDMOS電晶體10的深溝槽隔離結構，溝槽柵極28構成了溝槽LDMOS電晶體10的有源柵極，這將在下文中詳細說明。
溝槽LDMOS電晶體10包括一個平面柵極26，以及一個形成在P-型本體區22和N+漏極區24中形成的N+源極區23。在本實施例中，平面柵極26為多晶矽柵極，通過薄柵極氧化層25，與半導體層絕緣。在其他實施例中，可以利用其他導電柵極材料，製備平面柵極26。源極區23典型地自對準到平面柵極26的邊緣上。在本實施例中，利用低壓P-阱(Low voltage P-well，簡稱LVPW)技術在製備過程中，形成P-型本體區22。在其他實施例中，所形成的P-型本體區22穿過P-型植入物，自對準到平面柵極多晶矽26的邊緣上。漏極區24形成在N-型區中，作為LDMOS電晶體的漏極接觸區。在本實施例中，利用形成在高壓N-阱(High voltage N-well，簡稱HVNW)18中的低壓N-阱(Low voltage N-well，簡稱LVNW)20，製備漏極漂移區(Drain drift region)，高壓N-阱(HVNW)18和低壓N-阱(LVNW)20都形成在 N-外延層16中。一般而言，低壓N-阱20的摻雜濃度高於高壓N-阱18。此處所用的摻雜方案有時是指分級摻雜的漏極，其中從本體區22向N+漏極區24摻雜濃度遞增。在其他實施例中，可以利用一個或多個N-型區形成漏極漂移區。
在雙通道溝槽LDMOS電晶體10中，所含的P+區用於電接觸到本體區22上。在本實施例中，P+本體接觸區形成在裝置的z-方向上，也就是說，垂直於第1圖所示的橫截面。因此，第1圖中並沒有表示出P+本體接觸區。因此，如第3-6圖所示，P+本體接觸區可以作為交替的N+和P+區形成，或者P+區可以形成在島或條紋中，這將在下文中詳細說明。P+本體接觸區的準確結構，對於本發明的實施並不起決定作用，它僅當P+本體接觸區要與含有有源溝槽柵極的溝槽30分隔開時，是必需的。
在本實施例中，平面柵極26的末端部分延伸到場氧化層32上方。延伸到場氧化層32上方的平面柵極26，具有使平面柵極26邊緣處的電場弛豫的效果。在其他實施例中，平面柵極可以延伸到一步氧化層或其他氧化物結構的上方。場氧化層在形成時消耗了半導體層最頂部的矽，從而場氧化層的一部分形成在半導體層中，由於一步氧化層面對著場氧化層，一步氧化層是指形成在半導體層上方的氧化層。然而在其他實施例中，平面柵極可以全部形成在柵極氧化層上，柵極氧化層形成在半導體層上，其末端不再延伸到任何其他氧化物結構上方。
溝槽LDMOS電晶體10還包括一個形成在半導體層上方的絕緣介質層35。在絕緣介質層中，製造一個向N+源極23的接觸開口，並形成金屬接頭34作為到N+源極(如果可用，還可以到P+本體) 的電接觸。在絕緣介質層35中，製造另一個向N+漏極24的接觸開口，並形成金屬接頭36作為到N+漏極的電接觸。
因此，所形成的溝槽LDMOS電晶體10含有兩個有源柵極和兩個通道。平面柵極26在P-本體區22中半導體層(即N-外延層16)的表面附近，形成一個橫向通道。電子從N+源極區23開始，流經P-本體區22中的橫向通道，在水準方向上，流入N-外延層16、N-阱18和N-阱20所構成的漏極漂移區中，直到到達N+漏極區24為止。與此同時，溝槽柵極28在P-本體區22中沿溝槽30的一邊，形成一個垂直通道。電子從N+源極區23開始，流經P-本體區22中的垂直通道，在垂直方向上，流入N-外延層16和N-掩埋層14。來自垂直通道的電子橫向流經N-掩埋層14，然後向上穿過N-阱18、20，到達N+漏極區24。
假設平面柵極和垂直柵極的寬度相等，通過在LDMOS電晶體10中形成一個垂直通道和一個橫向通道相結合，就可以直接降低多達50%的通道電阻Rds*A。這兩個通道可增加電晶體的通道寬度W，同時使通道電阻減半。
在一個實施例中，平面柵極和溝槽柵極電連接在一起，因此橫向通道和垂直通道要同時開啟和關閉。在另一個實施例中，可以分別控制平面柵極和溝槽柵極，因此每個柵極可以獨立地開啟和關閉。由於可以把電晶體的寬度任選地切換到增加或降低有源柵極的總寬度，因此，該結構稱為“W切換”。更確切地說，當電流很高時，平面柵極和溝槽柵極都一致地開啟和關閉。然而，當電流需要降低時，僅啟動使用其中一個柵極即可。在電流很低時，可以任選使用平面柵極或溝槽柵極。在這種情況下，由於僅使用了總柵極的一部分(例如 僅啟動平面柵極)，電流很低時，也降低了柵極電容。
在第1圖中，形成在LDMOS電晶體10的漏極邊緣上的溝槽30b中的溝槽柵極28b，可以用作相鄰的溝槽LDMOS電晶體的有源柵極。當漏極邊緣上的填充氧化物的溝槽30僅用於隔離時，要將溝槽柵極28b接地或連接到使柵極無效的電勢上。
另外，在第1圖中，在溝槽30的底部，形成一個P-型通道終止區38。P-型通道終止區38具有降低橫向NPN增益的作用，從而提高對閉鎖的免疫能力。在本發明的其他實施例中，通道終止區38是可選的，也可以省略。
(b)堆積式柵極
第2圖表示依據本發明的第二實施例，一個雙通道溝槽LDMOS電晶體的橫截面視圖。參見第2圖，除了在溝槽中使用了堆積式柵極結構之外，溝槽LDMOS電晶體100的製備方法與第1圖所示的溝槽LDMOS電晶體10的製備方法完全相同。兩圖中相似的元件在此不再贅述。在本實施例中，溝槽LDMOS電晶體100包括帶有堆積式柵極結構的深填充氧化物的溝槽130。也就是說，每個填充氧化物的溝槽130都含有一個形成在溝槽上部的溝槽柵極128，以及一個形成在溝槽底部的底部柵極電極140。溝槽柵極128和底部柵極電極140相互絕緣。在一個實施例中，溝槽柵極和底部柵極電極都是由多晶矽製成的。在其他實施例中，也可以使用其他導電柵極材料。
更確切地說，當溝槽柵極128作為溝槽LDMOS電晶體100的有源柵極時，溝槽柵極128要連接到柵極電勢。當不使用溝槽柵極作為有源柵極(例如溝槽柵極128b)時，溝槽柵極也可以接地或無效(例如連接到使柵極無效的電勢上)。底部柵極電極140電連接到源 極電勢，在漏極區中實現了超級結效應。底部柵極電極140還具有增加溝槽柵極128對於N-掩埋層14處的漏極電勢遮罩作用。
因此在本實施例中，底部柵極電極140比溝槽柵極128薄，溝槽氧化物相鄰底部柵極電極140時要更厚。較厚的溝槽氧化物提高了對於溝槽隔離結構的擊穿承受力。底部柵極電極處的溝槽氧化物夾在底部柵極電極之間，底部柵極電極電連接到源極上，N-掩埋層14電連接到漏極上。因此，底部柵極附近的溝槽氧化物必須能夠承受溝槽LDMOS電晶體漏極至源極的電壓。
(c)溝槽和多晶矽柵極的佈局圖
第3圖表示依據本發明的第三實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。參見第3圖，雙通道溝槽LDMOS電晶體200含有平面柵極226、N+源極區223、P+本體接觸區242以及N+漏極區224。P-型本體區(圖中沒有表示出)位於平面柵極226和源極223下方。漏極漂移區形成在N-外延層216中。漏極漂移區也可以含有其他N-型區，例如高壓N-阱(HVNW)和/或低壓N-阱(LVNW)(第3圖中沒有表示出)。在本實施例中，含有一個溝槽柵極228b的溝槽230b，構成溝槽LDMOS電晶體200的隔離結構。溝槽230b包圍著溝槽LDMOS電晶體200的有源區，將溝槽LDMOS電晶體200與形成在相同襯底上的其他裝置隔離出來。溝槽柵極228b可以處於浮動狀態。
在溝槽LDMOS電晶體200中，另一個溝槽230含有溝槽柵極228，用作LDMOS電晶體200中的有源柵極。用作有源柵極的溝槽柵極228，與用作隔離的溝槽柵極228b隔離開來。這樣一來，所形成的雙通道溝槽LDMOS電晶體200，就具有一個由平面柵極226構成的橫向通道，以及一個由溝槽柵極228構成的垂直通道。
第4圖表示依據本發明的第四實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。第4圖中所示的溝槽LDMOS電晶體250與第3圖所示的溝槽LDMOS電晶體200大致相同，兩圖中相似的元件在此不再贅述。參見第4圖，溝槽LDMOS電晶體250包括一個形成在電晶體漏極漂移區中的溝槽叉指260，以形成相互交錯的溝槽和漏極漂移區。相互交錯的溝槽叉指260的溝槽柵極262電連接到源極電勢上。在這種情況下，超級結結構形成在溝槽LDMOS電晶體250的漏極中。這樣形成的超級結結構允許使用更高的漏極摻雜等級，從而增加了擊穿電壓，降低了漏極-至源極電阻。在本實施例中，相互交錯的溝槽叉指260的側壁氧化物比柵極氧化物更厚，以便承載源極至漏極電壓。必須要注意的是，溝槽叉指260與平面柵極226相互交叉的位置，平面柵極226實際上位於溝槽叉指260的上方，但是在第4圖中卻是從相反的方向上表示的，以便更好地展示溝槽叉指260的結構。
在溝槽LDMOS電晶體250中，含有一個溝槽柵極228b的溝槽230b，構成溝槽LDMOS電晶體250的隔離結構。如上所述，溝槽柵極228b可以處於浮動狀態。另外，隔離溝槽柵極228b的溝槽氧化物的厚度大於溝槽柵極中柵極氧化物層的厚度，所以溝槽230b的隔離結構可以承受更高的電壓。
第5圖表示依據本發明的第五實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。第6圖表示依據本發明的第六實施例，一個雙通道溝槽LDMOS電晶體的俯視圖。第5圖中所示的溝槽LDMOS電晶體300以及第6圖所示的溝槽LDMOS電晶體350，與第4圖所示的溝槽LDMOS電晶體250大致相同，這些圖中相似的元件在此不再贅述。如上所述，在溝槽LDMOS電晶體中的P+本體接觸區，用於電連接到電 晶體的本體。參見第5圖，雖然P+本體接觸區370形成在N+區323中，但是卻與溝槽330的側壁以及平面柵極226分離開。參見第6圖，所形成的P+本體接觸區，在N+源極區323中作為分立的P+島390。也可以利用其他適合電連接到LDMOS電晶體的P-本體區的方式製備溝槽LDMOS電晶體的本體接觸區。
第6圖所示的LDMOS電晶體350進一步說明了，相互交錯的填充氧化物的溝槽380的形成，以及溝槽柵極378延伸到相互交錯的溝槽區，形成柵極延伸物。柵極延伸物增大了雙通道LDMOS電晶體的通道寬度。
(2)BCD方法中的溝槽隔離
依據本發明的另一方面，上述帶有單一或堆積式柵極的填充氧化物的深溝槽，除了可用作有源柵極之外，也可用於BCD方法中裝置的深溝槽隔離技術。在這種情況下，BCD方法中的單一的填充氧化物的溝槽結構可用於隔離全部裝置(雙極、CMOS、DMOS)，也用作雙通道溝槽LDMOS電晶體的有源柵極。
第7圖表示依據本發明的一個實施例，利用BCD方法，採用深溝槽隔離技術製成的電晶體裝置的橫截面視圖。參見第7圖，BCD製備方法形成LDMOS電晶體410、N-型金屬氧化物半導體(NMOS)電晶體450、P-型金屬氧化物半導體(PMOS)電晶體460和NPN雙極結型電晶體(BJT)470，所有這些裝置都位於帶有N-掩埋層414和N-外延層416的P-型襯底412上。填充氧化物的溝槽430形成在半導體層中，並延伸到P-型襯底412中，以提供裝置隔離。在本實施例中，單一的溝槽柵極428形成在溝槽430中。
在本實施例中，形成帶有單一溝槽柵極的填充氧化物的 溝槽430，用於在溝槽LDMOS電晶體410、MOS電晶體450和雙極電晶體470之間提供隔離。由於在BCD製備方法中，所有裝置使用的都是同一種溝槽結構，因此無論溝槽柵極是否用作有源柵極，所有的氧化物填充的溝槽430都含有溝槽柵極428。當溝槽430僅用於裝置隔離時，溝槽柵極428就成為一個偽柵極，處於電浮動或電連接到其他適當的電勢上，使柵極無效。利用溝槽430，BCD方法中形成的電晶體裝置可以單獨隔離。另外，溝槽430實現了緊湊隔離體系，從而提高了密度，降低了BCD方法的成本。
在本實施例中，溝槽柵極428在LDMOS電晶體410中，構成一個到N-掩埋層414的垂直通道。因此，LDMOS電晶體410是一個帶有平面柵極426和垂直柵極428的雙通道溝槽LDMOS電晶體裝置。在一個備用的實施例中，LDMOS電晶體410可以作為一個單一通道電晶體裝置。可以僅用電晶體中的有源柵極製備平面柵極426。LDMOS電晶體的本體區(低壓P-阱422)附近的溝槽柵極428，通過置於浮動狀態或連接到使柵極無效的合適的電勢上，可以使其失去活性。
在第7圖所示的LDMOS電晶體410中，通過低壓P-阱422以及高壓P-阱421，可以製成P-本體區。高壓P-阱421的摻雜濃度低於低壓P-阱422的摻雜濃度。
在本發明的其他實施例中，BCD方法採用使用P-型掩埋層的裝置，利用與上述相同的填充氧化物的溝槽結構隔離形成在P-掩埋層上方的裝置。然而，在另一個實施例中，BCD方法採用一個垂直MOSFET裝置，例如垂直DMOS裝置。利用填充氧化物的溝槽結構，作為垂直MOSFET裝置的垂直通道的有源柵極。
第8圖表示依據本發明的一個可選實施例，利用BCD方 法，採用深溝槽隔離技術製成的電晶體裝置的橫截面視圖。第8圖所示的BCD製備方法與第7圖所示的BCD製備方法基本相同，形成LDMOS電晶體、NMOS電晶體、PMOS電晶體和雙極電晶體(圖中沒有表示出)，所有這些裝置都位於帶有N-掩埋層和N-外延層的P-型襯底上。第8圖所示的BCD製備方法說明了，利用一個在填充氧化物溝槽中的堆積式柵極結構，提供額外的遮罩。
(3)漏極超級結結構
依據本發明的另一方面，超級結結構形成在雙通道溝槽LDMOS電晶體的漏極漂移區中，以降低LDMOS電晶體的漏極電阻，並提高擊穿電壓。在本發明的一個實施例中，超級結結構是利用N-型和P-型區的交替層構成的。由於選取超級結結構的N-型和P-型區合適的寬度，使它們在實際運行中完全耗盡，因此可以用比傳統的漏極漂移區的摻雜等級還高的摻雜等級，製備超級結結構。耗盡超級結結構導致漏極漂移區的擊穿電壓增大，而較高的摻雜等級可以降低漏極電阻。
第9圖和第11圖表示依據本發明的不同實施例，帶有形成在漏極漂移區中的超級結結構的雙通道溝槽LDMOS電晶體的橫截面視圖。首先參見第9圖，雙通道溝槽LDMOS電晶體500的製備方式與第1圖所示的雙通道溝槽LDMOS電晶體10的製備方式基本相同，兩圖中類似的元件在此不再贅述。雙通道溝槽LDMOS電晶體500包括一個形成橫向通道的平面柵極526，以及一個形成垂直通道的溝槽柵極528。在本實施例中，平面柵極526並不延伸到場氧化層上方。
溝槽LDMOS電晶體500含有交替的N-型和P-型摻雜區，在溝槽LDMOS電晶體的漏極漂移區中構成超級結結構。在本實施 例中，交替的N-型和P-型摻雜區包括第一N-型區590、第二N-型區594以及夾在第一和第二N-型區之間的P-型區592，這些區域都形成在高壓N-阱518中，作為漏極漂移區。由於N-型區590和594以及P-型區592要在實際運行中耗盡，因此它們的摻雜濃度比下面的N-阱518的摻雜濃度更高。在本實施例中，P-型區592延伸到由低壓P-阱522構成的P-本體區中。
在一個實施例中，利用多種能量的植入物，通過一個單一掩膜，製成交替的N-型和P-型區。另外，在另一個實施例中，所形成的交替的N-型和P-型區自對準到平面柵極526上。通過有角度的植入以及隨後驅動，可以使P-型區592延伸到低壓P-阱522中。
因此，這樣製成的位於漏極漂移區中的交替的N-型和P-型區，具有分散電場並提高LDMOS電晶體的擊穿電壓的作用。第10圖表示帶有和不帶有超級結結構的第9圖所示的溝槽LDMOS電晶體的電場分佈圖。曲線595表示不帶有超級結結構的電場分佈。電場在本體區中不斷升高，直到本體區和N-外延層之間的P-N結達到臨界電場為止。然後，電場沿漏極漂移區的長度方向降低。曲線597表示帶有超級結結構的電場分佈。電場為P-N結任一邊上的摻雜等級的函數。如果摻雜等級較高，臨界電場也會升高。因此，如第10圖所示，曲線597升高到本體區中的高電場等級。然後，由N-型和P-型區590、592、594構成的超級結區域，具有使電場均勻排布的作用，與曲線595所示的三角形狀的電場相比，該電場分佈呈現梯形形狀，眾所周知，電場下方的面積為電晶體的擊穿電壓。通過將電場分佈轉化成梯形形狀，曲線597下方的面積會遠大於曲線595下方的面積，因此帶有超級結結構的溝槽LDMOS電晶體500的擊穿電壓也隨之增大。
現在參見第11圖，雙通道溝槽LDMOS電晶體600的製備方式，除了超級結結構之外，其他都與第9圖所示的溝槽LDMOS電晶體500的製備方式相同，兩圖中類似的元件在此不再贅述。在溝槽LDMOS電晶體600中，超級結結構是由第一P-型區690、第二P-型區694以及夾在第一和第二P-型區之間的N-型區692構成的，這些區域都形成在高壓N-阱618中。在本實施例中，N-型區692的摻雜濃度高於P-型區。通過將N-型區692置於兩個P-型區690和694之間，P-型區就像一個超級結一樣，或者作為降低表面電場區，用於降低LDMOS電晶體的表面電場。因此，提高了溝槽LDMOS電晶體的擊穿電壓。在溝槽LDMOS電晶體600中，所形成的交替N-型和P-型區自對準到平面柵極626上。在本實施例中，N-型區692並沒有延伸到高壓N-阱(HVNW)618以外。在一個可選實施例中，例如通過有角度的植入代替自對準的N-型植入，植入到平面柵極626的邊緣上，N-型區692可以延伸到高壓N-阱以外。
(4)可選實施例
第12圖表示依據本發明的一個可選實施例，一個雙通道溝槽LDMOS電晶體的橫截面視圖。參見第12圖，雙通道溝槽LDMOS電晶體700形成在N+襯底712上，而不是像之前的實施例那樣形成在P+襯底上。漏極區724形成在N+襯底712的背部，從而構成一個垂直LDMOS裝置。溝槽LDMOS電晶體700包括一個平面柵極726、一個垂直柵極728以及N+源極區723，這些裝置的形成方式與上述內容類似。
第13圖表示依據本發明的一個實施例，一個垂直溝槽MOS電晶體的橫截面視圖。參見第13圖，垂直溝槽MOS電晶體800形成在N+襯底812上，可以與一個雙通道LDMOS電晶體裝置(例如第12 圖所示的電晶體700)集成。在垂直溝槽MOS電晶體800中，溝槽柵極828構成MOS電晶體的垂直柵極，並且垂直通道形成在低壓P-阱(LVPW)822中。在垂直溝槽MOS電晶體800中，電流從源極區823開始，流經LVPW822中的通道區，流入N-外延層816、N-掩埋層814，然後流至N+襯底812。在襯底812的背部，製成漏極電極824。在表面上製成P+本體接頭818，以便良好地接觸源極金屬819。
第14圖表示依據本發明的一個可選實施例，利用BCD方法，採用深溝槽隔離技術製成的電晶體裝置的橫截面視圖。第14圖中所示的電晶體裝置的製備方式，與第8圖所示的電晶體裝置大致相同，兩圖中相似的元件在此不再贅述。參見第14圖，深溝槽930B和930C用於裝置隔離，它們延伸到P-型襯底912中。在本實施例中，深溝槽930B和930C並不包含任何溝槽柵極結構，而僅僅是填充氧化物的溝槽。在其他實施例中，如上所述，深溝槽可以包括單一溝槽柵極或堆積式柵極結構。與此同時，淺溝槽(例如溝槽930A)用於承載有源柵極。淺溝槽930A僅僅延伸到N-外延層中，並不延伸到P-型襯底中。
上述詳細說明僅用於解釋本發明的特殊實施例，並不作為局限。本發明範圍內可能存在各種修正和變化。本發明的範圍由所附的申請專利範圍限定。
10‧‧‧溝槽LDMOS電晶體
34、36‧‧‧金屬接頭
35‧‧‧絕緣介質層
24‧‧‧N+漏極區
28b、28‧‧‧溝槽柵極
30b‧‧‧溝槽
38‧‧‧P-型通道終止區
12‧‧‧P-型襯底
14、NBL‧‧‧N-型掩埋層
18、HVNW‧‧‧高壓N-阱
20、LVNW‧‧‧低壓N-阱
32‧‧‧場氧化層
26‧‧‧平面柵極
25‧‧‧薄柵極氧化層
23‧‧‧N+源極區
22‧‧‧P-型本體區
16‧‧‧N-型外延層
30‧‧‧深溝槽

Claims (26)

  1. 一種雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，包括：一個第一導電類型的襯底；一個形成在襯底上的第二導電類型的半導體層；一個形成在半導體層中的第一溝槽，用溝槽電介質填充第一溝槽，並在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；一個形成在第一溝槽附近半導體層中的第一導電類型的本體區；一個形成在本體區中，第一溝槽附近的第二導電類型的源極區；一個通過第二柵極介質層與半導體層絕緣的平面柵極，加在本體區上，所形成的源極區與平面柵極的第一邊緣對齊；以及一個形成在半導體層中的第二導電類型的漏極區，漏極漂移區將漏極區和本體區間隔開來；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
  2. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第一溝槽僅僅延伸到半導體層中。
  3. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第一溝槽穿過半導體層延伸到襯底中，溝槽柵極形成在第一溝槽的上部。
  4. 如申請專利範圍第3項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括：一個形成在第一溝槽下部的底部柵極電極，通過具有第二厚度的溝槽電介質，與第一溝槽的側壁絕緣，第二厚度大於使溝槽柵極絕緣的第一柵極介質層的厚度，底部柵極電極電接觸到源極電勢上。
  5. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括：一個形成在半導體層中，並延伸到襯底中的第二溝槽，用溝槽電介質填充第二溝槽，其中第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
  6. 如申請專利範圍第5項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括一個溝槽柵極，形成在第二溝槽的上部，通過第三柵極介質層，與第二溝槽的側壁絕緣，溝槽柵極處於電浮動狀態或電連接到指定電勢 上，以便使第二溝槽中的溝槽柵極無效。
  7. 如申請專利範圍第6項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，其中第三柵極介質層的厚度大於第一柵極介質層的厚度。
  8. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括：一個形成在半導體層中，並延伸到襯底中的第二溝槽，用溝槽電介質填充第二溝槽，一個形成在第二溝槽的上部，通過第三柵極介質層，與第二溝槽的側壁絕緣的溝槽柵極，以及一個形成在第二溝槽的下部，通過溝槽電介質，與第二溝槽的側壁絕緣的底部柵極電極，溝槽電介質的厚度大於第三柵極介質層的厚度，溝槽柵極處於電浮動狀態或電連接到指定電勢上，以便使第二溝槽中的溝槽柵極無效，底部柵極電極電連接到源極電勢上；其中第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
  9. 如申請專利範圍第8項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第三柵極介質層的厚度大於第一柵極介質層的厚度。
  10. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，漏極漂移區包括一個形成在半導體層中的第二導電類型的阱。
  11. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，漏極漂移區包括多個形成在半導體層中的第二導電類型的阱，這多個阱具有不同的摻雜濃度等級。
  12. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括形成在平面柵極和漏極區之間的半導體層表面上或表面中的場氧化層或一步氧化層，平面柵極的第二邊緣延伸到一部分場氧化層的上方或一步氧化層的上方。
  13. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，半導體層含有一個第二導電類型的外延層。
  14. 如申請專利範圍第13項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第二半導體層還包括一個形成在襯底上的第二導電類型的掩埋層，外延層形成在掩埋層上。
  15. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括多個形成在漏極漂移區中的溝槽叉指，用溝槽電介質填充多個溝槽叉指，多個溝槽叉指形成相互交錯的溝槽和漏極區，溝槽柵極形成在每個溝槽叉指的上部，並通過第三柵極介質層，與溝槽叉指的側壁絕緣，溝槽柵極電連接到源極電勢上。
  16. 如申請專利範圍第15項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第三柵極介質層的厚度大於第一柵極介質層的厚度。
  17. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第一溝槽包括相互交錯的溝槽區，這些溝槽區延伸到源極區和本體區中，形成溝槽柵極的延伸物。
  18. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括：一個位於源極區的本體接觸區，以便電接觸到本體區。
  19. 如申請專利範圍第1項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，第一導電類型為P-型，第二導電類型為N-型。
  20. 如申請專利範圍第19項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，還包括：多個形成在漏極漂移區中的交替的N-型和P-型區，這多個交替的N-型和P-型區的摻雜濃度高於漏極漂移區的摻雜濃度，在漏極漂移區構成一個超級結結構。
  21. 如申請專利範圍第20項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，多個交替的N-型和P-型區包括第一N-型區、第二N-型區以及夾在第一和第二N-型區之間的P-型區，第一和第二N-型區自對準到平面柵極的第 二邊緣上，P-型區延伸到本體區。
  22. 如申請專利範圍第20項所述的雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體，其中，多個交替的N-型和P-型區包括第一P-型區、第二P-型區以及夾在第一和第二P-型區之間的N-型區，第一和第二N-型區自對準到平面柵極的第二邊緣上。
  23. 一種用於製備雙通道溝槽橫向雙擴散金屬氧化物半導體電晶體的方法，包括：製備一個第一導電類型的襯底；在襯底上形成一個第二導電類型的半導體層；在半導體層中形成一個第一溝槽，用溝槽電介質填充第一溝槽；在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；在半導體層中第一溝槽附近形成一個第一導電類型的本體區；在本體區中第一溝槽附近形成一個第二導電類型的源極區；形成第二柵極介質層，覆蓋在本體區上，在第二柵極介質層上形成一個與半導體層絕緣的平面柵極，形成源極區與平面柵極的第一邊緣對齊；以及在半導體層中形成一個第二導電類型的漏極區，漏極漂 移區將漏極區和本體區間隔開來；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
  24. 如申請專利範圍第23項所述的方法，其中，還包括：在半導體層中製備第二溝槽，並延伸到襯底中，用溝槽電介質填充第二溝槽，第二溝槽包圍著橫向雙擴散金屬氧化物半導體電晶體的有源區，以隔離橫向雙擴散金屬氧化物半導體電晶體。
  25. 一種由垂直溝槽橫向雙擴散金屬氧化物半導體電晶體構成的半導體裝置，垂直溝槽橫向雙擴散金屬氧化物半導體電晶體包括：一個第一導電類型的襯底；一個形成在襯底上的第一導電類型的半導體層；一個形成在半導體層中的第一溝槽，用溝槽電介質填充第一溝槽，並在第一溝槽中形成一個溝槽柵極，通過第一柵極介質層，溝槽柵極與第一溝槽的側壁絕緣；一個形成在半導體層中第一溝槽附近的第二導電類型的本體區；一個形成在本體區中第一溝槽附近的第一導電類型的 源極區；一個通過第二柵極介質層與半導體層絕緣的平面柵極，加在本體區上，所形成的源極區與平面柵極的第一邊緣對齊；一個形成在半導體層中的第一導電類型的漏極漂移區；以及一個形成在襯底背部的漏極電極；其中平面柵極構成在源極區和漏極漂移區之間的本體區中的橫向雙擴散金屬氧化物半導體電晶體的橫向通道，第一溝槽中的溝槽柵極在本體區中，沿源極區和半導體層之間的第一溝槽的側壁，構成橫向雙擴散金屬氧化物半導體電晶體的垂直通道。
  26. 如申請專利範圍第25項所述的由垂直溝槽橫向雙擴散金屬氧化物半導體電晶體構成的半導體裝置，其中，還包括一個形成在相同襯底的獨立區域和相同的半導體層中的垂直溝槽MOS電晶體，該垂直溝槽MOS電晶體包括：一個形成在半導體層中的第二溝槽，用溝槽電介質填充第二溝槽，第二溝槽柵極形成在第二溝槽中，通過第二柵極介質層，與第二溝槽的側壁絕緣；一個形成在第二溝槽附近的半導體層中的第二導電類型的第二本體區，第二本體區延伸到形成在第二溝槽中的第二溝槽柵極的底部邊緣附近的深度；以及 一個形成在本體區中的、鄰近第二溝槽的第一導電類型的源極區，源極區形成在本體區的頂部；其中所形成的垂直溝槽MOS電晶體中，襯底作為垂直溝槽MOS電晶體的漏極區，半導體層作為漏極漂移區，第二溝槽柵極作為柵極電極。
TW099141739A 2009-12-02 2010-12-01 雙通道溝槽ldmos電晶體和bcd方法 TWI449175B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/629,844 US8174070B2 (en) 2009-12-02 2009-12-02 Dual channel trench LDMOS transistors and BCD process with deep trench isolation

Publications (2)

Publication Number Publication Date
TW201133856A TW201133856A (en) 2011-10-01
TWI449175B true TWI449175B (zh) 2014-08-11

Family

ID=44068205

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099141739A TWI449175B (zh) 2009-12-02 2010-12-01 雙通道溝槽ldmos電晶體和bcd方法

Country Status (3)

Country Link
US (6) US8174070B2 (zh)
CN (1) CN102097327B (zh)
TW (1) TWI449175B (zh)

Families Citing this family (168)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011009352A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置およびその製造方法ならびにそれを用いた電源装置
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US8431457B2 (en) 2010-03-11 2013-04-30 Alpha And Omega Semiconductor Incorporated Method for fabricating a shielded gate trench MOS with improved source pickup layout
WO2011148427A1 (en) * 2010-05-27 2011-12-01 Fuji Electric Co., Ltd. Mos-driven semiconductor device and method for manufacturing mos-driven semiconductor device
WO2011161748A1 (ja) 2010-06-21 2011-12-29 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8618627B2 (en) * 2010-06-24 2013-12-31 Fairchild Semiconductor Corporation Shielded level shift transistor
US20120007140A1 (en) * 2010-07-12 2012-01-12 National Semiconductor Corporation ESD self protecting NLDMOS device and NLDMOS array
US9064712B2 (en) * 2010-08-12 2015-06-23 Freescale Semiconductor Inc. Monolithic microwave integrated circuit
US8896064B2 (en) * 2010-10-18 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection circuit
US9893209B2 (en) * 2010-12-02 2018-02-13 Alpha And Omega Semiconductor Incorporated Cascoded high voltage junction field effect transistor
US8299547B2 (en) * 2011-01-03 2012-10-30 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates
US8901676B2 (en) 2011-01-03 2014-12-02 International Business Machines Corporation Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs
SE535621C2 (sv) * 2011-03-08 2012-10-16 Eklund Innovation K Halvledarkomponent bestående av en lateral JFET kombinerad med en vertikal JFET
US8643101B2 (en) * 2011-04-20 2014-02-04 United Microelectronics Corp. High voltage metal oxide semiconductor device having a multi-segment isolation structure
DE112012002136T5 (de) 2011-05-18 2014-03-13 Vishay-Siliconix Halbleitervorrichtung
US8921933B2 (en) * 2011-05-19 2014-12-30 Macronix International Co., Ltd. Semiconductor structure and method for operating the same
US8754476B2 (en) * 2011-07-19 2014-06-17 Richtek Technology Corporation, R.O.C. High voltage device and manufacturing method thereof
US8829603B2 (en) 2011-08-18 2014-09-09 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET package
US9054133B2 (en) 2011-09-21 2015-06-09 Globalfoundries Singapore Pte. Ltd. High voltage trench transistor
US8999769B2 (en) * 2012-07-18 2015-04-07 Globalfoundries Singapore Pte. Ltd. Integration of high voltage trench transistor with low voltage CMOS transistor
US9356012B2 (en) * 2011-09-23 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage ESD protection apparatus
CN102354686A (zh) * 2011-11-17 2012-02-15 上海先进半导体制造股份有限公司 60v高边ldnmos结构及其制造方法
CN102394246B (zh) * 2011-11-29 2017-12-22 上海华虹宏力半导体制造有限公司 可升级的横向双扩散金属氧化物半导体晶体管及制造方法
CN102496575A (zh) * 2011-12-23 2012-06-13 上海先进半导体制造股份有限公司 60v非对称高压pmos结构及其制造方法
US8637370B2 (en) 2012-01-19 2014-01-28 Globalfoundries Singapore Pte. Ltd. Integration of trench MOS with low voltage integrated circuits
KR101899556B1 (ko) 2012-02-03 2018-10-04 에스케이하이닉스 시스템아이씨 주식회사 Ｂｃｄｍｏｓ 소자 및 그 제조방법
TWI548090B (zh) * 2012-02-07 2016-09-01 聯華電子股份有限公司 半導體裝置及其製作方法
US9093296B2 (en) 2012-02-09 2015-07-28 United Microelectronics Corp. LDMOS transistor having trench structures extending to a buried layer
CN103390645B (zh) * 2012-05-08 2016-08-03 上海韦尔半导体股份有限公司 横向扩散金属氧化物半导体晶体管及其制作方法
JP2013247188A (ja) * 2012-05-24 2013-12-09 Toshiba Corp 半導体装置
US9041105B2 (en) * 2012-07-20 2015-05-26 International Business Machines Corporation Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure
US8686505B2 (en) * 2012-07-27 2014-04-01 Infineon Technologies Dresden Gmbh Lateral semiconductor device and manufacturing method therefor
US8847310B1 (en) 2012-07-31 2014-09-30 Azure Silicon LLC Power device integration on a common substrate
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US8674440B2 (en) 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
US8994105B2 (en) 2012-07-31 2015-03-31 Azure Silicon LLC Power device integration on a common substrate
KR101585537B1 (ko) 2012-07-31 2016-01-14 실라나 아시아 피티이 리미티드 공통 기판 상의 파워 소자 집적
US10290702B2 (en) * 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate
US8928116B2 (en) 2012-07-31 2015-01-06 Silanna Semiconductor U.S.A., Inc. Power device integration on a common substrate
US8916440B2 (en) 2012-08-03 2014-12-23 International Business Machines Corporation Semiconductor structures and methods of manufacture
TWI467765B (zh) * 2012-08-20 2015-01-01 Vanguard Int Semiconduct Corp 半導體裝置及其製造方法
CN103681791B (zh) * 2012-09-05 2016-12-21 上海华虹宏力半导体制造有限公司 Nldmos器件及制造方法
JP5787853B2 (ja) * 2012-09-12 2015-09-30 株式会社東芝 電力用半導体装置
WO2014061254A1 (ja) 2012-10-16 2014-04-24 旭化成エレクトロニクス株式会社 電界効果トランジスタ及び半導体装置
CN103779329B (zh) * 2012-10-23 2016-11-16 无锡华润上华半导体有限公司 用于mosfet噪声测试的半导体测试结构
CN103811402B (zh) * 2012-11-15 2016-08-17 上海华虹宏力半导体制造有限公司 一种超高压bcd工艺的隔离结构制作工艺方法
CN103855212B (zh) * 2012-12-04 2018-10-23 中芯国际集成电路制造(上海)有限公司 一种横向扩散半导体器件
US9337178B2 (en) 2012-12-09 2016-05-10 Semiconductor Components Industries, Llc Method of forming an ESD device and structure therefor
US20140167173A1 (en) * 2012-12-14 2014-06-19 Broadcom Corporation Increasing the breakdown voltage of a metal oxide semiconductor device
TWI476926B (zh) * 2012-12-25 2015-03-11 Richtek Technology Corp 橫向雙擴散金屬氧化物半導體元件製造方法
CN103050541B (zh) * 2013-01-06 2015-08-19 上海华虹宏力半导体制造有限公司 一种射频ldmos器件及其制造方法
US9324838B2 (en) 2013-01-11 2016-04-26 Stmicroelectronics S.R.L. LDMOS power semiconductor device and manufacturing method of the same
US9117845B2 (en) * 2013-01-25 2015-08-25 Fairchild Semiconductor Corporation Production of laterally diffused oxide semiconductor (LDMOS) device and a bipolar junction transistor (BJT) device using a semiconductor process
US9245960B2 (en) 2013-02-08 2016-01-26 Globalfoundries Inc. Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates
CN103165678B (zh) * 2013-03-12 2015-04-15 电子科技大学 一种超结ldmos器件
JP6182921B2 (ja) * 2013-03-21 2017-08-23 富士電機株式会社 Ｍｏｓ型半導体装置
US9171903B2 (en) * 2013-05-17 2015-10-27 Micron Technology, Inc. Transistors having features which preclude straight-line lateral conductive paths from a channel region to a source/drain region
US9041144B2 (en) 2013-05-17 2015-05-26 Micron Technology, Inc. Integrated circuitry comprising transistors with broken up active regions
CN104241353B (zh) * 2013-06-07 2017-06-06 上海华虹宏力半导体制造有限公司 射频ldmos器件及其制造方法
US8981475B2 (en) * 2013-06-18 2015-03-17 International Business Machines Corporation Lateral diffusion metal oxide semiconductor (LDMOS)
TWI511293B (zh) * 2013-06-24 2015-12-01 Chip Integration Tech Co Ltd 雙溝渠式ｍｏｓ電晶體結構及其製造方法
US9059281B2 (en) 2013-07-11 2015-06-16 International Business Machines Corporation Dual L-shaped drift regions in an LDMOS device and method of making the same
US10199459B2 (en) * 2013-07-19 2019-02-05 Great Wall Semiconductor Corporation Superjunction with surrounding lightly doped drain region
KR102115619B1 (ko) * 2013-09-06 2020-05-27 에스케이하이닉스 시스템아이씨 주식회사 반도체 장치 및 그 제조방법
CN103489915B (zh) * 2013-09-16 2016-05-11 电子科技大学 一种横向高压超结功率半导体器件
US9224854B2 (en) * 2013-10-03 2015-12-29 Texas Instruments Incorporated Trench gate trench field plate vertical MOSFET
US8987820B1 (en) * 2013-10-11 2015-03-24 Vanguard International Semiconductor Corporation Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same
CN104617139B (zh) * 2013-11-05 2017-08-08 上海华虹宏力半导体制造有限公司 Ldmos器件及制造方法
US9431531B2 (en) * 2013-11-26 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having drain side contact through buried oxide
CN104681610B (zh) * 2013-12-03 2017-08-08 上海华虹宏力半导体制造有限公司 Nldmos器件
US9245998B2 (en) * 2013-12-29 2016-01-26 Texas Instruments Incorporated High voltage multiple channel LDMOS
CN103762241B (zh) * 2014-01-02 2016-08-24 杭州电子科技大学 一种梳状栅纵向沟道soi ldmos单元
US9570437B2 (en) * 2014-01-09 2017-02-14 Nxp B.V. Semiconductor die, integrated circuits and driver circuits, and methods of maufacturing the same
US9450076B2 (en) 2014-01-21 2016-09-20 Stmicroelectronics S.R.L. Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
CN104810398B (zh) * 2014-01-29 2018-06-22 世界先进积体电路股份有限公司 半导体装置及其制造方法
JP2015176974A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置
DE102014104589B4 (de) * 2014-04-01 2017-01-26 Infineon Technologies Ag Halbleitervorrichtung und integrierte Schaltung
US9263436B2 (en) * 2014-04-30 2016-02-16 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
KR20160001913A (ko) * 2014-06-27 2016-01-07 에스케이하이닉스 주식회사 전력용 전자 소자
CN105448983B (zh) * 2014-07-30 2020-07-07 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
US9520367B2 (en) 2014-08-20 2016-12-13 Freescale Semiconductor, Inc. Trenched Faraday shielding
US9331196B2 (en) * 2014-10-02 2016-05-03 Nuvoton Technology Corporation Semiconductor device
US9281379B1 (en) 2014-11-19 2016-03-08 International Business Machines Corporation Gate-all-around fin device
KR102168302B1 (ko) * 2014-11-21 2020-10-22 삼성전자주식회사 3차원 채널을 이용하는 반도체 장치
CN105789298B (zh) 2014-12-19 2019-06-07 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管及其制造方法
KR102286012B1 (ko) * 2015-02-17 2021-08-05 에스케이하이닉스 시스템아이씨 주식회사 전력용 집적소자와, 이를 포함하는 전자장치 및 전자시스템
US9520492B2 (en) * 2015-02-18 2016-12-13 Macronix International Co., Ltd. Semiconductor device having buried layer
US9837411B2 (en) * 2015-07-14 2017-12-05 Tower Semiconductors Ltd. Semiconductor die with a metal via
US10153213B2 (en) 2015-08-27 2018-12-11 Semiconductor Components Industries, Llc Process of forming an electronic device including a drift region, a sinker region and a resurf region
US9647109B2 (en) * 2015-09-07 2017-05-09 Kabushiki Kaisha Toshiba Semiconductor device
JP2017055102A (ja) * 2015-09-10 2017-03-16 株式会社豊田自動織機 トレンチゲート型半導体装置及びその製造方法
US10217733B2 (en) 2015-09-15 2019-02-26 Semiconductor Components Industries, Llc Fast SCR structure for ESD protection
US9543299B1 (en) * 2015-09-22 2017-01-10 Texas Instruments Incorporated P-N bimodal conduction resurf LDMOS
CN106571388B (zh) * 2015-10-08 2018-10-12 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
US9755066B2 (en) * 2015-11-30 2017-09-05 Infineon Technologies Austria Ag Reduced gate charge field-effect transistor
US9660073B1 (en) * 2015-12-17 2017-05-23 Vanguard International Semiconductor Corporation High-voltage semiconductor device and method for manufacturing the same
US9905688B2 (en) 2016-01-28 2018-02-27 Texas Instruments Incorporated SOI power LDMOS device
US9680473B1 (en) * 2016-02-18 2017-06-13 International Business Machines Corporation Ultra dense vertical transport FET circuits
JP6695188B2 (ja) * 2016-03-29 2020-05-20 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6688653B2 (ja) * 2016-03-30 2020-04-28 エイブリック株式会社 半導体装置および半導体装置の製造方法
JP6651957B2 (ja) * 2016-04-06 2020-02-19 株式会社デンソー 半導体装置およびその製造方法
US10388781B2 (en) * 2016-05-20 2019-08-20 Alpha And Omega Semiconductor Incorporated Device structure having inter-digitated back to back MOSFETs
US10199475B2 (en) * 2016-05-24 2019-02-05 Maxim Integrated Products, Inc. LDMOS transistors and associated systems and methods
US9893070B2 (en) * 2016-06-10 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabrication method therefor
KR102495452B1 (ko) 2016-06-29 2023-02-02 삼성전자주식회사 반도체 장치
US9761707B1 (en) * 2016-08-19 2017-09-12 Nxp Usa, Inc. Laterally diffused MOSFET with isolation region
US10978869B2 (en) 2016-08-23 2021-04-13 Alpha And Omega Semiconductor Incorporated USB type-C load switch ESD protection
US10103140B2 (en) * 2016-10-14 2018-10-16 Alpha And Omega Semiconductor Incorporated Switch circuit with controllable phase node ringing
US10211784B2 (en) 2016-11-03 2019-02-19 Nxp Usa, Inc. Amplifier architecture reconfiguration
CN106449759B (zh) * 2016-11-11 2019-08-02 电子科技大学 隔离型ldmos结构及其制造方法
US9941171B1 (en) * 2016-11-18 2018-04-10 Monolithic Power Systems, Inc. Method for fabricating LDMOS with reduced source region
KR102140358B1 (ko) * 2016-12-23 2020-08-03 매그나칩 반도체 유한회사 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자
CN108242467B (zh) * 2016-12-27 2020-05-22 无锡华润上华科技有限公司 Ldmos器件及其制作方法
JP6726092B2 (ja) * 2016-12-28 2020-07-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US9842896B1 (en) * 2017-02-17 2017-12-12 Vanguard International Semiconductor Corporation Ultra-high voltage devices and method for fabricating the same
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
CN108807512B (zh) * 2017-05-05 2021-06-04 世界先进积体电路股份有限公司 半导体装置及其形成方法
US10269951B2 (en) * 2017-05-16 2019-04-23 General Electric Company Semiconductor device layout and method for forming same
KR102227666B1 (ko) * 2017-05-31 2021-03-12 주식회사 키 파운드리 고전압 반도체 소자
TWI614891B (zh) * 2017-07-03 2018-02-11 世界先進積體電路股份有限公司 高壓半導體裝置
CN109216175B (zh) * 2017-07-03 2021-01-08 无锡华润上华科技有限公司 半导体器件的栅极结构及其制造方法
US10037988B1 (en) * 2017-08-24 2018-07-31 Globalfoundries Singapore Pte. Ltd. High voltage PNP using isolation for ESD and method for producing the same
TWI670799B (zh) * 2017-09-06 2019-09-01 世界先進積體電路股份有限公司 半導體裝置及其製造方法
US10262997B2 (en) 2017-09-14 2019-04-16 Vanguard International Semiconductor Corporation High-voltage LDMOSFET devices having polysilicon trench-type guard rings
US10388649B2 (en) 2017-10-04 2019-08-20 Vanguard International Semiconductor Corporation Semiconductor devices and methods for manufacturing the same
CN108565286B (zh) * 2017-12-26 2021-01-29 西安电子科技大学 高k介质沟槽横向双扩散金属氧化物元素半导体场效应管及其制作方法
US10347509B1 (en) 2018-02-09 2019-07-09 Didrew Technology (Bvi) Limited Molded cavity fanout package without using a carrier and method of manufacturing the same
WO2019160566A1 (en) 2018-02-15 2019-08-22 Didrew Technology (Bvi) Limited Method of simultaneously fabricating multiple wafers on large carrier with warpage control stiffener
US10734326B2 (en) 2018-02-15 2020-08-04 Didrew Technology (Bvi) Limited Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage
US10680099B2 (en) * 2018-02-19 2020-06-09 Globalfoundries Singapore Pte. Ltd. Isolated laterally diffused metal oxide semiconductor (LDMOS) transistor having low drain to body capacitance
JP7000240B2 (ja) * 2018-04-18 2022-01-19 ルネサスエレクトロニクス株式会社 半導体装置
KR102359373B1 (ko) * 2018-06-11 2022-02-08 에스케이하이닉스 시스템아이씨 주식회사 고전압 반도체소자의 제조방법
TWI656646B (zh) * 2018-06-12 2019-04-11 立錡科技股份有限公司 高壓元件及其製造方法
CN110634949B (zh) * 2018-06-22 2023-03-28 立锜科技股份有限公司 高压元件及其制造方法
CN109148444B (zh) * 2018-08-22 2020-10-27 电子科技大学 Bcd半导体器件及其制造方法
US11289570B2 (en) 2018-08-24 2022-03-29 Semiconductor Components Industries, Llc Semiconductor device having optimized drain termination and method therefor
US11069804B2 (en) * 2018-08-31 2021-07-20 Alpha And Omega Semiconductor (Cayman) Ltd. Integration of HVLDMOS with shared isolation region
US11296075B2 (en) * 2018-08-31 2022-04-05 Texas Instruments Incorporated High reliability polysilicon components
CN109216352B (zh) * 2018-09-13 2020-10-27 电子科技大学 一种bcd半导体集成器件
US10770584B2 (en) * 2018-11-09 2020-09-08 Texas Instruments Incorporated Drain extended transistor with trench gate
TWI673880B (zh) * 2018-11-21 2019-10-01 新唐科技股份有限公司 橫向擴散金氧半導體裝置
CN109860300B (zh) * 2018-12-27 2022-04-22 北京顿思集成电路设计有限责任公司 半导体器件及其制造方法
CN109830523B (zh) * 2019-01-08 2021-08-24 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法
CN113330578A (zh) * 2019-01-21 2021-08-31 日产自动车株式会社 半导体装置及其制造方法
US10886418B2 (en) * 2019-02-21 2021-01-05 Texas Instruments Incorporated Split-gate JFET with field plate
CN110534513B (zh) * 2019-09-06 2022-02-08 电子科技大学 一种高低压集成器件及其制造方法
TWI765335B (zh) * 2019-09-09 2022-05-21 愛爾蘭商亞德諾半導體國際無限公司 半導體裝置、具有閘極介電質監控能力之半導體裝置、以及用以監控金屬氧化物半導體電晶體中閘極介電質之方法
CN112530805B (zh) * 2019-09-19 2022-04-05 无锡华润上华科技有限公司 横向双扩散金属氧化物半导体器件及制作方法、电子装置
FR3103318B1 (fr) * 2019-11-15 2021-12-10 St Microelectronics Crolles 2 Sas Circuit intégré comprenant un transistor nldmos et procédé de fabrication d’un tel circuit intégré
US11552190B2 (en) 2019-12-12 2023-01-10 Analog Devices International Unlimited Company High voltage double-diffused metal oxide semiconductor transistor with isolated parasitic bipolar junction transistor region
US10910478B1 (en) * 2020-03-04 2021-02-02 Shuming Xu Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance
CN113496939A (zh) * 2020-04-03 2021-10-12 无锡华润上华科技有限公司 一种半导体器件及其制作方法
CN111477681A (zh) * 2020-04-23 2020-07-31 西安电子科技大学 双通道均匀电场调制横向双扩散金属氧化物元素半导体场效应管及制作方法
CN111477680A (zh) * 2020-04-23 2020-07-31 西安电子科技大学 双通道均匀电场调制横向双扩散金属氧化物宽带隙半导体场效应管及制作方法
US11024749B1 (en) * 2020-06-15 2021-06-01 Taiwan Semiconductor Manufacturing Company Limited Dual channel transistor device and methods of forming the same
CN111682024B (zh) * 2020-06-30 2022-12-02 电子科技大学 一种bcd半导体器件
US11380759B2 (en) * 2020-07-27 2022-07-05 Globalfoundries U.S. Inc. Transistor with embedded isolation layer in bulk substrate
CN112436057B (zh) * 2020-10-15 2021-09-17 上海芯导电子科技股份有限公司 一种低导通电阻mos器件及制备工艺
TWI818371B (zh) * 2021-01-12 2023-10-11 立錡科技股份有限公司 高壓元件及其製造方法
US20220262907A1 (en) * 2021-02-12 2022-08-18 Nuvolta Technologies (Hefei) Co., Ltd. Lateral Double Diffused MOS Device
US11810976B2 (en) 2021-02-18 2023-11-07 Semiconductor Components Industries, Llc Semiconductor device
CN113113495B (zh) * 2021-04-12 2022-07-05 东南大学 一种具有交错槽栅结构的横向双扩散金属氧化物半导体器件
CN113394291A (zh) * 2021-04-29 2021-09-14 电子科技大学 横向功率半导体器件
TWI798809B (zh) * 2021-06-18 2023-04-11 力晶積成電子製造股份有限公司 半導體結構以及其形成方法
KR20230144201A (ko) * 2022-04-07 2023-10-16 주식회사 키파운드리 아이솔레이션 항복 전압 향상을 위한 반도체 소자
CN114937695B (zh) * 2022-07-25 2022-10-21 北京芯可鉴科技有限公司 双沟道ldmos器件及其制备方法以及芯片
CN115662900A (zh) * 2022-10-21 2023-01-31 苏州华太电子技术股份有限公司 超级结ldmos器件的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849854A (en) * 1986-11-12 1989-07-18 Mitsubihsi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5736753A (en) * 1994-09-12 1998-04-07 Hitachi, Ltd. Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide
US20090108403A1 (en) * 2007-10-26 2009-04-30 Bishnu Prasanna Gogoi Semiconductor structure and method of manufacture
TW200947706A (en) * 2008-04-30 2009-11-16 Alpha & Omega Semiconductor Ltd Short channel lateral MOSFET and method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3324832B2 (ja) * 1993-07-28 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US20080197408A1 (en) * 2002-08-14 2008-08-21 Advanced Analogic Technologies, Inc. Isolated quasi-vertical DMOS transistor
TW563244B (en) * 2002-10-25 2003-11-21 Vanguard Int Semiconduct Corp Deep trench isolation structure of high voltage device and its manufacturing method
US7015115B1 (en) * 2003-02-20 2006-03-21 Newport Fab, Llc Method for forming deep trench isolation and related structure
US7087491B1 (en) * 2003-02-28 2006-08-08 Micrel, Inc. Method and system for vertical DMOS with slots
CN103199017B (zh) * 2003-12-30 2016-08-03 飞兆半导体公司 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法
US6903421B1 (en) 2004-01-16 2005-06-07 System General Corp. Isolated high-voltage LDMOS transistor having a split well structure
US7154159B2 (en) * 2004-02-24 2006-12-26 Nanya Technology Corporation Trench isolation structure and method of forming the same
US7291541B1 (en) * 2004-03-18 2007-11-06 National Semiconductor Corporation System and method for providing improved trench isolation of semiconductor devices
US7087959B2 (en) * 2004-08-18 2006-08-08 Agere Systems Inc. Metal-oxide-semiconductor device having an enhanced shielding structure
US7453119B2 (en) * 2005-02-11 2008-11-18 Alphs & Omega Semiconductor, Ltd. Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact
EP1703566A1 (en) * 2005-03-18 2006-09-20 AMI Semiconductor Belgium BVBA MOS device having at least two channel regions
US7468307B2 (en) * 2005-06-29 2008-12-23 Infineon Technologies Ag Semiconductor structure and method
KR101009399B1 (ko) 2008-10-01 2011-01-19 주식회사 동부하이텍 Ｌｄｍｏｓ 트랜지스터 및 그 제조방법
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849854A (en) * 1986-11-12 1989-07-18 Mitsubihsi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US5736753A (en) * 1994-09-12 1998-04-07 Hitachi, Ltd. Semiconductor device for improved power conversion having a hexagonal-system single-crystal silicon carbide
US20090108403A1 (en) * 2007-10-26 2009-04-30 Bishnu Prasanna Gogoi Semiconductor structure and method of manufacture
TW200947706A (en) * 2008-04-30 2009-11-16 Alpha & Omega Semiconductor Ltd Short channel lateral MOSFET and method

Also Published As

Publication number Publication date
US9190408B2 (en) 2015-11-17
TW201133856A (en) 2011-10-01
CN102097327A (zh) 2011-06-15
US8704303B2 (en) 2014-04-22
US20140225190A1 (en) 2014-08-14
US10020369B2 (en) 2018-07-10
US9595517B2 (en) 2017-03-14
US20170213894A1 (en) 2017-07-27
US20110127602A1 (en) 2011-06-02
US8378420B2 (en) 2013-02-19
US20130119465A1 (en) 2013-05-16
CN102097327B (zh) 2013-10-23
US8174070B2 (en) 2012-05-08
US20160099242A1 (en) 2016-04-07
US20120187481A1 (en) 2012-07-26

Similar Documents

Publication Publication Date Title
TWI449175B (zh) 雙通道溝槽ldmos電晶體和bcd方法
TWI575718B (zh) 利用深擴散區在單片功率積體電路中製備jfet和ldmos電晶體
US9673323B2 (en) Embedded JFETs for high voltage applications
US8652930B2 (en) Semiconductor device with self-biased isolation
TWI546967B (zh) 低導通電阻的半導體裝置
JP5641131B2 (ja) 半導体装置およびその製造方法
CN107123681B (zh) 半导体装置以及半导体装置的制造方法
EP1227523A2 (en) High-Voltage transistor with buried conduction layer and method of making the same
US20140061790A1 (en) Split-gate lateral diffused metal oxide semiconductor device
KR100985373B1 (ko) 드레인 확장형 ｍｏｓ 트랜지스터 및 그 반도체 장치 제조방법
US20170179279A1 (en) Partial, self-biased isolation in semiconductor devices
US9257517B2 (en) Vertical DMOS-field effect transistor
JP2009239096A (ja) 半導体装置
KR20110078621A (ko) 반도체 소자 및 그 제조 방법
KR20090107024A (ko) Ｐｎ접합 및 모스 커패시터 하이브리드 리설프 트랜지스터
JP2000260990A (ja) 高電圧素子及びその製造方法
TWI436483B (zh) 半導體裝置
JP2017073410A (ja) 半導体装置および半導体装置の製造方法
TWI546961B (zh) 高壓金氧半導體電晶體元件
TWI540724B (zh) 高壓金氧半導體電晶體元件