TWI476926B - 橫向雙擴散金屬氧化物半導體元件製造方法 - Google Patents

橫向雙擴散金屬氧化物半導體元件製造方法 Download PDF

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TWI476926B
TWI476926B TW101149675A TW101149675A TWI476926B TW I476926 B TWI476926 B TW I476926B TW 101149675 A TW101149675 A TW 101149675A TW 101149675 A TW101149675 A TW 101149675A TW I476926 B TWI476926 B TW I476926B
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Tsung Yi Huang
Chien Wei Chiu
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Richtek Technology Corp
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Description

橫向雙擴散金屬氧化物半導體元件製造方法
本發明係有關一種橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件製造方法，特別是指一種利用同一氧化區遮罩定義通道阻擋區、上層區、絕緣氧化區、與場氧化區之LDMOS元件製造方法。
第1A-1D圖顯示先前技術之雙降低表面電場(double reduced surface field,double RESURF)橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件100製造方法中前段製程之剖視示意圖。如第1A圖所示，於P型基板11上，形成N型磊晶層11a。接下來如第1B圖所示，以微影製程形成光阻層12a為遮罩，定義通道阻擋(channel stop)區12，並以離子植入製程，將P型雜質，以加速離子的形式，如圖中虛線箭號所示意，植入定義的區域內，而形成通道阻擋區12於磊晶層11a中。接著，如第1C圖所示，以微影製程形成光阻層13a為遮罩，定義上層區13，並以離子植入製程，將P型雜質，以加速離子的形式，如圖中虛線箭號所示意，植入定義的區域內，而形成上層區13於磊晶層11a中。
接下來，接下來如第1D圖所示，以微影製程與沉積製程，形成氮化矽層14為遮罩，定義隔絕氧化區14a與場氧化區14b，並以氧化及/或沉積製程形成隔絕氧化區14a與場氧化區14b。隔絕氧化區14a與場氧化區14b例如為淺溝槽絕緣(shallow trench isolation,STI)結構或如圖所示之區域氧化 (local oxidation of silicon,LOCOS)結構。
此種先前技術需要三道微影製程來定義通道阻擋區12、上層區13、隔絕氧化區14a與場氧化區14b，在LDMOS元件的製造中，尤其是分離(discrete)元件的雙降低表面電場LDMOS元件製造中，每一道微影製程佔其整個LDMOS元件之製造成本與製程時間的比例相對較高，若能節省任何一道微影製程，對降低LDMOS元件製造成本與縮短製程時間皆有相當大的助益。
有鑑於此，本發明即針對上述先前技術之改善，提出一種LDMOS元件製造方法，可降低製造成本，縮段製程時間。
本發明提供了一種橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件製造方法，包含：提供一基板；形成一磊晶層於該基板上；形成一氧化區遮罩於該磊晶層上；根據該氧化區遮罩形成一第一導電型通道阻擋區與一第一導電型上層區於該磊晶層中；根據該氧化區遮罩形成一隔絕氧化區與一場氧化區分別於該通道阻擋區與該上層區上；移除該氧化區遮罩；形成一第一導電型井區於該磊晶層中；形成一閘極於該磊晶層上，其中，部分該閘極位於該場氧化區上，另一部分該閘極位於部分該井區上；形成一第二導電型輕摻雜區於該井區中，且至少部分該輕摻雜區位於該閘極下方；形成一第二導電型源極與一第二導電型汲極於該閘極兩側，分別位於該井區中與該磊晶層中，於該LDMOS元件導通操作時，一橫向通道形成於該源極與該汲極之間。
在其中一種較佳的實施例中，該LDMOS元件製造方 法，更包含：形成一第二導電型漂移區於該磊晶層中，與該汲極連接，且該漂移區與該源極之間，由該井區隔開。
另一種較佳實施例中，該通道阻擋區包括一高濃度區與一低濃度區，且該高濃度區介於該低濃度區與該隔絕氧化區之間。
又一種較佳實施例中，該通道阻擋區與該上層區由同一雜質摻雜製程步驟所形成。
上述的實施例中，該雜質摻雜製程步驟宜包括一離子植入製程步驟，且形成該通道阻擋區與該上層區之步驟較佳地包括：由氧化區遮罩定義該通道阻擋區與該上層區，並以該離子植入製程步驟，將第一導電型雜質，以加速離子的形式，植入定義的區域內。
另一種較佳實施例中，該氧化區遮罩包括一氮化矽層。
又一種較佳實施例中，該輕摻雜區與該源極連接。
再一種較佳實施例中，由上視圖視之，該場氧化區與該上層區由該氧化區遮罩定義於一相同區域，且該隔絕氧化區與該通道阻擋區由該氧化區遮罩定義於另一相同區域。
又再一種較佳實施例中，該LDMOS元件包括一雙降低表面電場(double reduced surface field,double RESURF)LDMOS元件。
上述的實施例中，該雙降低表面電場LDMOS元件宜係一分離(discrete)元件。
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。
請參閱第2A-2G圖，顯示本發明的第一個實施例。第2A-2F圖顯示本發明應用於LDMOS元件200之剖視示意圖，第2G圖顯示第2F圖之上視示意圖。首先，如第2A圖所示，提供基板21，其導電型例如但不限於為P型，並於基板21上形成磊晶層21a，其導電型例如但不限於為N型。接著，請參閱第2B圖，於磊晶層21a上形成氧化區遮罩24，其例如但不限於為氮化矽層。需說明的是，若氧化區遮罩24為氮化矽層，一種較佳的實施方式為，如第2B圖所示，在磊晶層21a上，先形成襯墊氧化層21b，再於襯墊氧化層21b上形成氮化矽層，以緩和氮化矽層與磊晶層21a間的應力。
請繼續參閱第2B圖，根據氧化區遮罩24，例如以氧化區遮罩24為硬遮罩(hard mask)，定義通道阻擋區22與上層區23，並以離子植入製程，將例如但不限於P型雜質，以加速離子的形式，如圖中虛線箭號所示意，植入定義的區域內，而形成P型通道阻擋區22與P型上層區23於磊晶層21a中。需說明的是，通道阻擋區22與上層區23例如但不限於由同一雜質摻雜製程步驟(在本實施例中例如為離子植入製程)所形成。
接下來請參閱第2C圖，根據氧化區遮罩24，例如以氧化及/或沉積製程，分別於通道阻擋區22與上層區23上，形成隔絕氧化區24a與場氧化區24b。隔絕氧化區24a與場氧化區24b例如為STI結構或如圖所示之LOCOS結構。需說 明的是，形成通道阻擋區22與上層區23的離子植入製程，可以在形成隔絕氧化區22與場氧化區23之前或之後，皆屬於本發明的範圍。
接下來請參閱第2D圖，移除氧化區遮罩24後，例如但不限於以微影製程及離子植入製程，形成井區25於磊晶層21a中，其導電型例如但不限於為P型。請接著參閱第2E圖，於磊晶層21A上，形成閘極27；其中，部分閘極27位於場氧化區24b上，另一部分閘極27位於部分井區25上。
接下來請參閱第2F圖，於井區25中，形成輕摻雜區28，其導電型例如但不限於為N型，且至少部分輕摻雜區28位於閘極27下方，以於LDMOS元件200在導通操作時，可形成電流通道。接著，如圖所示，於閘極27兩側，分別於井區25中與磊晶層21a中，形成源極29a與汲極29b；使得LDMOS元件200導通操作時，於源極29a與汲極29b之間，形成橫向電流通道。其中，一種較佳的安排為，使輕摻雜區28與源極29a連接，以形成上述電流通道。
與先前技術不同的是，本實施例利用同一氧化區遮罩24定義通道阻擋區22、上層區23、絕緣氧化區24a、與場氧化區24b，而非如先前技術需要利用三道微影製程來定義上述各區域。此外，通道阻擋區22、上層區23例如可以利用相同的雜質摻雜步驟形成。如此一來，不但可以降低製造成本，也大幅縮短了製造的流程與時間。
第2G圖顯示第2F之上視示意圖，舉例顯示LDMOS元件200各區的一種安排方式。上視圖第2G圖舉例說明場氧化區24b與上層區23由氧化區遮罩24定義於一相同區域，且隔絕氧化區24a與通道阻擋區22由氧化區遮罩24定義於另一 相同區域，因此在上視圖第2G圖上顯示為重疊的區域。
第3圖顯示本發明的第二個實施例。本實施例舉例說明利用第一個實施例LDMOS元件200的製造方法，可增加至少一製程步驟，以形成漂移區26於磊晶層21a中，其導電型例如但不限於為N型。漂移區26與汲極29b連接，且漂移區26與源極29a之間，由井區25隔開；而形成如圖所示之LDMOS元件300。較佳的實施方式為：當磊晶層21a為P型時，需要漂移區26以形成電流通道，而當磊晶層21a為N型時，則漂移區26可依設計者需求決定省略或加入。
第4圖顯示本發明的第3個實施例。本實施例舉例說明利用第一個實施例LDMOS元件200的製造方法，可增加至少一製程步驟，而使通道阻擋區包括高濃度區22b與低濃度區22a，以形成LDMOS元件400。如圖所示，高濃度區22b介於低濃度區22a與隔絕氧化區24a之間。這樣安排的優點為：當LDMOS元件400在數百伏的超高壓操作時，高濃度區22b之雜質濃度相對較低濃度區22b高，可以防止場元件導通(field device turns ON)。
需說明的是，本發明之LDMOS元件，例如但不限於包括雙降低表面電場(double reduced surface field,double RESURF)LDMOS元件。以第一個實施例LDMOS元件200為例，其中，上方RESURF區形成於上層區23與磊晶層21a之間，而下方RESURF區形成於磊晶層21a與基板21之間。而以第二個實施例LDMOS元件300為例，其中，上方RESURF區形成於上層區23與漂移區26之間，而下方RESURF區形成於漂移區26與磊晶層21a之間。此外，上述雙降低表面電場LDMOS元件例如但不限於為分離(discrete)元 件，指獨立的高壓元件，在電路應用時，需要與其他電路結合，以形成完整的電路。
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如臨界電壓調整區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術；再如，上述所有實施例中，漂移區、源極、汲極、輕摻雜區等不限於為N型，且井區、通道阻擋區、上層區等不限於為P型，而可以互換，只要其他摻雜區做相應之調整即可，又基板和磊晶層也不限於為實施例所述的摻雜型態，例如可為相反的摻雜型態而具有適當摻雜型態的深井區等。本發明的範圍應涵蓋上述及其他所有等效變化。
11,21‧‧‧基板
11a,21a‧‧‧磊晶層
12,22‧‧‧通道阻擋區
12a,13a‧‧‧光阻
13,23‧‧‧上層區
14‧‧‧氮化矽層
14a,24a‧‧‧隔絕氧化區
14b,24b‧‧‧場氧化區
21b‧‧‧襯墊氧化層
24‧‧‧氧化區遮罩
25‧‧‧井區
26‧‧‧漂移區
27‧‧‧閘極
28‧‧‧輕摻雜區
29a‧‧‧源極
29b‧‧‧汲極
100,200,300,400‧‧‧LDMOS元件
第1A-1D圖顯示先前技術之雙降低表面電場LDMOS元件100製造方法中前段製程之剖視示意圖。
第2A-2G圖顯示本發明的第一個實施例。
第3圖顯示本發明的第二個實施例。
第4圖分別顯示本發明的第三個實施例。
21‧‧‧基板
21a‧‧‧磊晶層
22‧‧‧通道阻擋區
23‧‧‧上層區
24a‧‧‧隔絕氧化區
24b‧‧‧場氧化區
25‧‧‧井區
27‧‧‧閘極
28‧‧‧輕摻雜區
29a‧‧‧源極
29b‧‧‧汲極
200‧‧‧LDMOS元件

Claims (10)

  1. 一種橫向雙擴散金屬氧化物半導體(lateral double diffused metal oxide semiconductor,LDMOS)元件製造方法，包含：提供一基板；形成一磊晶層於該基板上；形成一氧化區遮罩於該磊晶層上；根據該氧化區遮罩形成一第一導電型通道阻擋區與一第一導電型上層區於該磊晶層中；根據該氧化區遮罩形成一隔絕氧化區與一場氧化區分別於該通道阻擋區與該上層區上；移除該氧化區遮罩；形成一第一導電型井區於該磊晶層中；形成一閘極於該磊晶層上，其中，部分該閘極位於該場氧化區上，另一部分該閘極位於部分該井區上；形成一第二導電型輕摻雜區於該井區中，且至少部分該輕摻雜區位於該閘極下方；形成一第二導電型源極與一第二導電型汲極於該閘極兩側，分別位於該井區中與該磊晶層中，於該LDMOS元件導通操作時，一橫向電流通道形成於該源極與該汲極之間。
  2. 如申請專利範圍第1項所述之LDMOS元件製造方法，更包含：形成一第二導電型漂移區於該磊晶層中，與該汲極連接，且該漂移區與該源極之間，由該井區隔開。
  3. 如申請專利範圍第1項所述之LDMOS元件製造方法，其中該通道阻擋區包括一高濃度區與一低濃度區，且該高濃度區介於該低濃度區與該隔絕氧化區之間。
  4. 如申請專利範圍第1項所述之LDMOS元件製造方法，其 中該通道阻擋區與該上層區由同一雜質摻雜製程步驟所形成。
  5. 如申請專利範圍第4項所述之LDMOS元件製造方法，其中該雜質摻雜製程步驟包括一離子植入製程步驟，且形成該通道阻擋區與該上層區之步驟包括：由氧化區遮罩定義該通道阻擋區與該上層區，並以該離子植入製程步驟，將第一導電型雜質，以加速離子的形式，植入定義的區域內。
  6. 如申請專利範圍第1項所述之LDMOS元件製造方法，其中該氧化區遮罩包括一氮化矽層。
  7. 如申請專利範圍第1項所述之LDMOS元件製造方法，其中該輕摻雜區與該源極連接。
  8. 如申請專利範圍第1項所述之LDMOS元件製造方法，其中，由上視圖視之，該場氧化區與該上層區由該氧化區遮罩定義於一相同區域，且該隔絕氧化區與該通道阻擋區由該氧化區遮罩定義於另一相同區域。
  9. 如申請專利範圍第1項所述之LDMOS元件製造方法，其中該LDMOS元件包括一雙降低表面電場(double reduced surface field,double RESURF)LDMOS元件。
  10. 如申請專利範圍第9項所述之LDMOS元件製造方法，其中該雙降低表面電場LDMOS元件係一分離(discrete)元件。
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