CN103050541B - 一种射频ldmos器件及其制造方法 - Google Patents

一种射频ldmos器件及其制造方法 Download PDF

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CN103050541B
CN103050541B CN201310003606.6A CN201310003606A CN103050541B CN 103050541 B CN103050541 B CN 103050541B CN 201310003606 A CN201310003606 A CN 201310003606A CN 103050541 B CN103050541 B CN 103050541B
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trap
drift region
radio frequency
ldmos device
frequency ldmos
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CN103050541A (zh
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钱文生
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本申请公开了一种射频LDMOS器件，具有侧面接触的沟道掺杂区与漂移区。在沟道掺杂区与漂移区的侧面接触部位的下方具有与之接触的第一阱，在漂移区远离沟道掺杂区的那一端下方具有与之接触的第二阱；所述第一阱与第二阱的掺杂类型相同，均与沟道掺杂区的掺杂类型相同，而与漂移区的掺杂类型相反。本申请还公开了其制造方法。由于在沟道下方、漏端下方分别增加了第一阱和第二阱，本申请可以提高副阻效应发生时的漏端触发电压，以获取高可靠性。

Description

一种射频LDMOS器件及其制造方法
技术领域
本申请涉及一种半导体器件，特别是涉及一种应用于射频领域的LDMOS器件。
背景技术
射频LDMOS(横向扩散MOS晶体管)器件通常应用于大功率射频领域，例如射频基站和广播站。通常，多个射频LDMOS器件以阵列形式组合使用。因此每个射频LDMOS器件都需具有高可靠性，以免因个别器件的薄弱(例如过早击穿)而造成整个阵列毁坏。
请参阅图1，这是一种现有的射频LDMOS器件。以n型射频LDMOS器件为例，在p型重掺杂衬底1上具有p型轻掺杂外延层2。在外延层2中具有侧面接触的p型沟道掺杂区7和n型漂移区3。在沟道掺杂区7中具有n型重掺杂源区8。在漂移区3中具有n型重掺杂漏区9。在沟道掺杂区7和部分漂移区3之上依次具有栅氧化层4和多晶硅栅极5。在多晶硅栅极5的正上方、以及部分漂移区3的正上方具有连续的一块氧化硅10。在部分氧化硅10的上方具有连续的一块栅掩蔽层(G-shield)11，为金属或n型重掺杂多晶硅。栅掩蔽层11至少要相隔氧化硅10而在部分的漂移区3的上方。下沉结构12从源区8表面向下穿透源区8、沟道掺杂区7、外延层2，并抵达到衬底1之中。
在漏端9加高压时，所述射频LDMOS器件会出现副阻效应(snapback effect)，这是造成器件烧坏的一个重要原因。为提高器件的可靠性，应尽量提高副阻效应发生时的漏端触发电压，这可以通过提高漏端9与衬底1之间的击穿电压、降低器件沟道电阻、降低器件击穿时的沟道电流这三种手段的一种或多种组合来实现。但当衬底1和漂移区3的掺杂浓度一旦确定，漏端9与衬底1之间的击穿电压就已经确定，不能随意调整。
发明内容
本申请所要解决的技术问题是提供一种射频LDMOS器件，可以提高副阻效应发生时的漏端触发电压，以获取高可靠性。为此，本申请还要提供所述射频LDMOS器件的制造方法。
为解决上述技术问题，本申请射频LDMOS器件具有侧面接触的沟道掺杂区与漂移区，在沟道掺杂区与漂移区的侧面接触部位的下方具有与之接触的第一阱，在漂移区远离沟道掺杂区的那一端下方具有与之接触的第二阱；所述第一阱与第二阱的掺杂类型相同，均与沟道掺杂区的掺杂类型相同，而与漂移区的掺杂类型相反；所述第一阱在栅极和栅氧化层的正下方。
所述射频LDMOS器件的制造方法为：先以光刻和离子注入工艺在漂移区的两端下方形成相互独立的第一阱和第二阱，第一阱和第二阱分别与漂移区的两端的底部相接触；接着在漂移区的一端侧面形成与之接触的沟道掺杂区，所述沟道掺杂区的底部还与第一阱的顶部相接触；接着形成栅极和栅氧化层，栅氧化层在第一阱的正上方。
本申请射频LDMOS器件由于增加了沟道下方的第一阱、和漏端下方的第二阱，而具有如下优点：
其一，第一阱可以在器件其它特性不变的情况下，在沟道掺杂区下面形成低阻通道，有效地降低总的沟道电阻，抑制器件的副阻效应。
其二，第一阱还会横向扩散到器件漂移区的下方，从而改善漂移区内的电场分布均匀性，产生的RESURF(Reduced SURfsce Field，减小表面电场)效应能够提高器件的漂移区击穿电压，进一步保证器件的击穿电压发生在漏极。
其三，第二阱可以适当降低漏端与衬底之间的击穿电压，保证器件击穿时绝大多数漏端电流流向衬底，而不是流向沟道，从而提高器件在副阻效应发生时的漏端触发电压。
附图说明
图1是现有的射频LDMOS器件的结构示意图；
图2a～图2h是本申请射频LDMOS器件的制造方法各步骤示意图。
图中附图标记说明：
1为衬底；2为外延层；3为漂移区；4为栅氧化层；5为多晶硅栅极；6a为第一p阱；6b为第二p阱；7为沟道掺杂区；8为源区；9为漏区；10为氧化硅；11为栅掩蔽层；12为下沉结构；20为光刻胶。
具体实施方式
请参阅图2h，这是本申请所述的射频LDMOS器件。以n型射频LDMOS器件为例，在p型重掺杂衬底1上具有p型轻掺杂外延层2。在外延层2中具有侧面接触的p型沟道掺杂区7和n型漂移区3。在外延层2中还具有相互独立的第一p阱6a和第二p阱6b。第一p阱6a在沟道掺杂区7和漂移区3的侧面接触部位的下方且三者相互接触。第二p阱6b在漂移区3远离沟道掺杂区7的那一端的下方且相互接触。在沟道掺杂区7中具有n型重掺杂源区8。在漂移区3中具有n型重掺杂漏区9。在沟道掺杂区7和部分的漂移区3之上依次具有栅氧化层4和多晶硅栅极5。在多晶硅栅极5的正上方、以及部分漂移区3的正上方连续地具有一块氧化硅10。在部分或全部的氧化硅10的上方具有连续的一块栅掩蔽层(G-shield)11。栅掩蔽层11至少要相隔氧化硅10而在部分的漂移区3的上方。下沉结构12从源区8表面向下穿透源区8、沟道掺杂区7、外延层2，并抵达到衬底1之中。在源区8和下沉结构12、多晶硅栅极5、栅掩蔽层11和漏区9之上形成有金属硅化物。或者，源区8和下沉结构12也可从硅片背面以金属硅化物引出。
可选地，也可将外延层2去除掉。
如果是p型射频LDMOS器件，将上述各部分结构的掺杂类型变为相反即可。
与现有的射频LDMOS器件相比，本申请的主要创新在于：在沟道下方增加了第一p阱，在漏端下方增加了第二p阱。第一p阱可以显著地降低器件的沟道电阻。第二p阱适当降低了漏端与衬底之间的击穿电压，保证器件击穿时绝大多数漏端电流流向衬底，而不是流向沟道，从而提高器件在副阻效应发生时的漏端触发电压。
下面以n型射频LDMOS器件为例，介绍其制造方法：
第1步，请参阅图2a，在重掺杂p型硅衬底1上具有轻掺杂p型外延层2，采用光刻工艺利用光刻胶作为掩蔽层，并以一次或多次注入n型离子，在外延层2中形成n型漂移区3。
或者，也可以将外延层2省略掉，这样其后的各结构与工艺均直接在衬底1上进行。
第2步，请参阅图2b，采用光刻工艺利用光刻胶20作为掩蔽层，形成窗口A和窗口B。所述窗口A至少为外延层2远离漂移区3的一端，也可以包括外延层2紧邻漂移区3的另一端，甚至包括漂移区3紧邻外延层2的一端。所述窗口B为漂移区3远离外延层2的另一端。在窗口A和窗口B中同时对外延层2和漂移区3注入p型杂质。在窗口A下方的外延层2(可能还包括漂移区3)中形成第一p阱6a。在窗口B下方的外延层2(可能还包括漂移区3)中形成第二p阱6b。第一p阱6a、第二p阱6b的顶部分别与漂移区3的两端的底部相接触。然后去除光刻胶20。
所述离子注入工艺可以是一次或多次，总的注入能量为1×1012～1×1013原子/平方厘米。
所述第一p阱6a、第二p阱6b的顶部距离硅材料(外延层2或漂移区3)的上表面的距离在0.5μm以上。
第3步，请参阅图2c，先以热氧化工艺在硅材料(包括外延层2和漂移区3)的表面生长出氧化硅4，再在整个硅片表面淀积多晶硅5。接着采用光刻和刻蚀工艺，在氧化硅4和多晶硅5上形成一个窗口C。所述窗口C仅暴露出部分的外延层2。整个漂移区3以及其余部分的外延层2仍被氧化硅4和多晶硅5以及光刻胶20所覆盖。在窗口C中对外延层2注入p型杂质，优选为硼，从而形成与漂移区3的侧面接触、且与第一p阱6a的顶部接触的沟道掺杂区7。离子注入时光刻胶20也作为掩蔽层，离子注入后再去除光刻胶20。
优选地，离子注入具有一定的倾斜角度，从而使沟槽掺杂区7更容易向氧化硅4的下方延伸，并且与漂移区3的侧面相接触。
第4步，请参阅图2d，采用光刻和刻蚀工艺，将氧化硅4和多晶硅5分别刻蚀为栅氧化层4和多晶硅栅极5。栅氧化层4的一部分在沟道掺杂区7的上方，其余部分在漂移区3的上方。第一p阱6a相隔沟道掺杂区7和漂移区3，而在栅氧化层4的正下方。
第5步，请参阅图2e，采用光刻工艺，以光刻胶作为掩蔽层形成窗口D和窗口E，它们分别位于栅氧化层4远离漂移区3的那一端外侧、漂移区3远离栅氧化层4的那一端外侧。对这两个窗口采用n型杂质的源漏注入工艺分别形成源区8和漏区9。此时，沟道掺杂区7的主体部分缩小至仅在栅氧化层4的下方，还有少部分的沟道掺杂区7在源区8的下方。漏区9相隔漂移区3而在第二p阱6b的正上方。
第6步，请参阅图2f，在整个硅片淀积一层氧化硅10，采用光刻和刻蚀工艺对该层氧化硅10进行刻蚀，使其仅连续地残留在多晶硅栅极5的上方、以及漂移区3的部分面的上方。
第7步，请参阅图2g，在整个硅片淀积一层金属11，采用光刻和刻蚀工艺对该层金属11进行刻蚀形成栅掩蔽层(G-shield)11。栅掩蔽层11为连续的一块，覆盖在部分或全部的氧化硅10之上。栅掩蔽层11至少要相隔氧化硅10而在部分的漂移区6的上方。
或者，栅掩蔽层11也可以是n型重掺杂多晶硅。此时，可先淀积多晶硅再进行n型杂质的离子注入，也可直接淀积n型掺杂多晶硅(即原位掺杂)。
第8步，请参阅图2h，采用光刻和刻蚀工艺，在源区8中刻蚀出深孔。所述深孔穿越源区8、沟道掺杂区7、外延层2，并抵达到衬底1之中，故称“深”孔。在该深孔中填充金属，优选为钨，形成下沉(sinker)结构12。所述深孔也可改为沟槽结构。
如要制造p型射频LDMOS器件，将上述方法各步骤中的掺杂类型变为相反即可。例如：第1步中采用重掺杂n型硅衬底、或者位于重掺杂n型硅衬底之上的轻掺杂n型外延层。第2、3步离子注入n型杂质，优选为磷或砷。第5步离子注入p型杂质，优选为硼。
以上仅为本申请的优选实施例，并不用于限定本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (9)

1.一种射频LDMOS器件，具有侧面接触的沟道掺杂区与漂移区；其特征是，在沟道掺杂区与漂移区的侧面接触部位的下方具有与之接触的第一阱，在漂移区远离沟道掺杂区的那一端下方具有与之接触的第二阱；所述第一阱与第二阱的掺杂类型相同，均与沟道掺杂区的掺杂类型相同，而与漂移区的掺杂类型相反；所述第一阱在栅极和栅氧化层的正下方。
2.根据权利要求1所述的射频LDMOS器件，其特征是，所述第一阱相隔沟道掺杂区和漂移区，而在所述射频LDMOS器件的栅氧化层的正下方。
3.根据权利要求1所述的射频LDMOS器件，其特征是，所述第二阱相隔漂移区，而在所述射频LDMOS器件的漏区的正下方。
4.根据权利要求1所述的射频LDMOS器件，其特征是，所述第一阱、第二阱的顶部距离硅材料的上表面的距离在0.5μm以上。
5.一种射频LDMOS器件的制造方法，其特征是，先以光刻和离子注入工艺在漂移区的两端下方形成相互独立的第一阱和第二阱，第一阱和第二阱分别与漂移区的两端的底部相接触；接着在漂移区的一端侧面形成与之接触的沟道掺杂区，所述沟道掺杂区的底部还与第一阱的顶部相接触；接着形成栅极和栅氧化层，栅氧化层在第一阱的正上方。
6.根据权利要求5所述的射频LDMOS器件的制造方法，其特征是，包括如下步骤：
第1步，以离子注入工艺在第一导电类型的外延层中形成第二导电类型的漂移区；
第2步，以离子注入工艺在漂移区两端下方分别形成第一阱和第二阱，它们均为第一导电类型；
第3步，以热氧化工艺在硅材料表面生长出第一氧化硅，再淀积多晶硅；接着以光刻和刻蚀工艺在第一氧化硅和多晶硅上形成第一窗口，该第一窗口仅暴露出部分的外延层；接着在第一窗口中注入第一导电类型杂质，从而形成与漂移区的侧面相接触、且与第一阱的顶部相接触的沟道掺杂区；
第4步，将第一氧化硅和多晶硅分别刻蚀为栅氧化层和多晶硅栅极；
第5步，以源漏注入工艺在栅氧化层远离漂移区的那一端外侧形成第二导电类型的源区，在漂移区远离栅氧化层的那一端外侧形成第二导电类型的漏区；
第6步，整个硅片淀积第二氧化硅，采用光刻和刻蚀工艺使其仅残留在多晶硅栅极的上方、以及漂移区的部分表面的上方；
第7步，整个硅片淀积一层金属或多晶硅，对其刻蚀形成栅掩蔽层；栅掩蔽层覆盖在部分或全部的第二氧化硅之上；
第8步，在源区中刻蚀出穿越源区、沟道掺杂区、外延层并抵达到衬底中的孔或沟槽，在该孔或沟槽中填充金属形成下沉结构。
7.根据权利要求6所述的射频LDMOS器件的制造方法，其特征是，所述方法各步骤中去除外延层，将外延层中的结构均改为衬底中。
8.根据权利要求6所述的射频LDMOS器件的制造方法，其特征是，所述方法第2步中，所述离子注入工艺是一次或多次，总的注入能量为1×1012～1×1013原子/平方厘米。
9.根据权利要求6所述的射频LDMOS器件的制造方法，其特征是，所述方法第3步中，离子注入具有倾斜角度。
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