TWI381482B - 形成貫穿電極之方法 - Google Patents
形成貫穿電極之方法 Download PDFInfo
- Publication number
- TWI381482B TWI381482B TW094120930A TW94120930A TWI381482B TW I381482 B TWI381482 B TW I381482B TW 094120930 A TW094120930 A TW 094120930A TW 94120930 A TW94120930 A TW 94120930A TW I381482 B TWI381482 B TW I381482B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- forming
- electrode
- perforation
- substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 44
- 239000010410 layer Substances 0.000 claims description 182
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 41
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 32
- 229910052802 copper Inorganic materials 0.000 claims description 32
- 239000010949 copper Substances 0.000 claims description 32
- 239000010931 gold Substances 0.000 claims description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 29
- 229910052737 gold Inorganic materials 0.000 claims description 29
- 229910052759 nickel Inorganic materials 0.000 claims description 29
- 239000012790 adhesive layer Substances 0.000 claims description 25
- 239000002390 adhesive tape Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000011800 void material Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000007747 plating Methods 0.000 description 21
- 235000012431 wafers Nutrition 0.000 description 21
- HEMHJVSKTPXQMS-UHFFFAOYSA-M sodium hydroxide Inorganic materials [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 13
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 239000002585 base Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052763 palladium Inorganic materials 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000004380 ashing Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000003094 microcapsule Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001764 infiltration Methods 0.000 description 2
- 230000008595 infiltration Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05164—Palladium [Pd] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Micromachines (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明是有關於一種貫穿電極(through electrode)及形成此電極之方法,且特別是有關於於小孔內填入導電材料之所形成之一種貫穿電極及形成此電極之方法。
具有如微機械封裝物與內連物(micromachine packages and interposers)之微電子機械系統(MEMS)之三維結構之電子裝置等及其利用之半導體微製程技術已為習知。近年來,用於形成連結電子裝置中之上方導線圖案與下方導線圖案之貫穿電極之技術已廣為發展。舉例來說,於部份內連物中,貫穿電極係形成於延伸基板之一上方表面與一下方表面間之穿孔(through hole)內,藉以提供導電圖案間之電性連結關係。(請參照如早期公開申請案第1-258457號之日本專利)。
上述公開申請案揭露了一種填充穿孔之方法,該些穿孔係形成於基板內且為絕緣層所覆蓋,其包括經電鍍而成之金屬材質。依據如此之方法,晶種層係藉由濺鍍法以形成於基板之一上表面上。接著,將用於電鍍之電極接觸晶種層之一上表面處,並採用電解電鍍法以沉積例如銅之導電金屬至其晶種層表面。由導電材料所形成之導體層則成長並將上述穿孔填滿金屬材料。
然而,上述方法仍存在有問題,由於形成於晶種層表面之導電層係形成於穿孔的內部表面上且導電金屬之沉積係於穿孔之內部表面上形成,因此隨著導電層的沉積將於於接近各穿孔內中心處產生孔洞(voids)。
特別地,於微機電封裝物之應用中,當穿孔之尺寸相對於基板厚度為小而造成深寬比(厚度/穿孔直徑)為高時,便使得於如此小之穿孔內形成貫穿電極變的困難。
有鑑於此,本發明的主要目的之一就是提供一種貫穿電極以及形成此貫穿電極之方法,藉以解決至少一上述習知問題。
依據本發明之一目的,本發明提供了一種形成貫穿電極之方法,包括下列步驟:一第一步驟,於一支撐體(support body)之一表面上形成一晶種層於;一第二步驟,於該晶種層之一表面上形成一黏著層(adhesive layer);一第三步驟,壓擠其內具有一穿孔之一基板至該黏著層上;一第四步驟,移除連結於基板上之該穿孔之該黏著層之一部分,於該穿孔之一下端處形成寬於該穿孔之一剖面之一空隙;一第五步驟,於該空隙與該穿孔內填入一導體並形成覆蓋該穿孔之下端之一下端電極接墊與填滿該穿孔之一柱狀電極(column electrode);以及一第六步驟,自該基板上移除該支撐體、該晶種層與該黏著層。
其中該第五步驟較佳地更包括以下步驟:
形成構成該下端電極接墊之一金(Au)層於該晶種層上之步驟;形成一鎳(Ni)層於該金層之一表面上之步驟;以及形成一銅層於該鎳層之表面,形成該柱狀電極之步驟。
較佳地,於將一黏著膠帶貼於該支撐體之表面後,接著於該第一步驟中形成該晶種層於該黏著層之一黏著表面上;以及於第五步驟中形成該柱狀電極後,於第六步驟中藉由加熱該黏著膠帶,以分離該支撐體處與該晶種層。
再者,較佳地,於該第一步驟中,該晶種層係形成於該支撐體之該表面上,而該黏著層接著形成於該晶種層上;以及於該第五步驟中,於該穿孔內側形成該柱狀電極後,於該第六步驟中則藉由加熱該黏著層以分離該支撐體與該晶種層。
較佳地,該黏著層包括一光阻層;以及該第四步驟更包括下列步驟:藉由一顯影程序移除形成於連結該基板之該穿孔之該區域內該光阻層之一步驟;以及於該穿孔之該下端處形成寬於該穿孔之剖面之該空隙之一步驟。
較佳地,上述形成貫穿電極之方法更包括形成一阻劑層於該基板之一上表面以及於該阻劑層內形成寬於該穿孔之一上端之剖面之一開口之一步驟;於該阻劑層內之該開口內填入一導體,以形成連結於該柱狀電極之一上端之一上端電極接墊之一步驟;以及移除環繞該上端電極接墊之該阻劑層之一步驟。
依據本發明之另一目的,本發明之貫穿電極,適用於設置於延伸通過一基板且電性連結形成於該基板之一上表面之一導電圖案與形成於該基板之一下表面之一導體圖案之一穿孔內,包括:一下端電極接墊,其寬於該穿孔之一剖面且密封了該穿孔之一下端開口;以及一柱狀電極,藉由層疊一導電材料於下端電極接墊上而由下往上填滿該穿孔。
較佳地,更包括一上端電極接墊,形成於該柱狀電極之一上端,並寬於該穿孔之剖面,以密封該穿孔之一上端開口。
依據本發明,晶種層係形成於支撐體之表面,而基板則安裝於形成於晶種層表面之黏著層上。如此便不需要分別地形成用於固定基板之一黏著層,因而簡化了製造程序與降低製造成本。形成於連結基底之穿孔之黏著層可藉由顯影方式移除以於穿孔之下端處形成寬於穿孔剖面尺寸之一空隙。如此,可於空隙內之晶種層上形成下端電極接墊。再者,由於柱狀電極係形成於下端電極接墊上且由下往上形成,如此可避免了於穿孔中心處之孔洞的形成。因此,即使穿孔深寬比很大之情形下,柱狀電極亦可穩定地形成。
此外,黏著層係形成於具有晶種層之支撐體表面,因此支撐體可藉由加熱黏著層而輕易地與基板分離。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉一較佳實施例,並配合所附圖示,作詳細說明如下:
本發明之實施例將配合以下對應圖式作一詳細敘述如下。
第一實施例:第1圖為一垂直剖面圖,圖示了依據本發明之一實施例之具有貫穿電極(through electrode)之電子裝置10以及其形成方法。第2圖則圖示了貫穿電極之一放大剖面圖。
於如第1圖所示之電子裝置10中,作為微機電元件之功能元件18係形成於由基板12與一上蓋(基板)14所定義出之一元件安裝空間16。從上視觀之,基板12、上蓋14與元件安裝空間16分別具有一四邊形外型。依據本實施例,基板12例如為一矽晶圓(矽基板)或一玻璃基板。當使用矽作為基板12時,於下文中描述則較佳地使用矽晶圓或玻璃基板作為一支撐體。本實施例不僅可於簡單基板內形成貫穿電極,其亦可應用於包含積體電路之半導體晶圓形成貫穿電極。
雖然於第1圖內未顯示,但是於該基板12之表面形成有用於上述功能元件18之電路,除此之外,功能元件18亦包含一懸臂樑(cantilever)。上述電子裝置包括由鋁或銅所構成之電極20。功能元件18係藉由微機械方式形成於基板12之表面。
依據於基板12上功能元件18之安裝型態,本實施例之電子裝置10可應用於如加速度計(accelerometer)之感應器與微迴轉儀(micro gyro)。
電子裝置10包括電性連結基板12與上蓋14之超音波連結部22。上蓋14包括由表面上塗佈有絕緣層15且由矽晶圓所製成之基板14a,定義出元件安裝空間16之凹口14b與環繞凹口14b之基座(frame)14c。超音波接合部22分別包括電極20、形成於上蓋14內之貫穿電極24與用以連結貫穿電極24之一下端與電極20之一金凸塊26。於貫穿電極24之一上端處則形成有一錫凸塊27。
上蓋14之基座14c內包括用以形成貫穿電極24用之穿孔28。穿孔28之直徑介於30-100微米而其高度(對應於基板14a之厚度)介於150-500微米。如此,本實施例之深寬比(厚度/直徑)介於1.5~16.67。
如第2圖所示,貫穿電極24之整體包括填入於穿孔28內之一柱狀電極30、形成於柱狀電極30之一下端側且具有(水平表面區域)寬於穿孔28之剖面之尺寸之一下端電極接墊32,以及形成於貫穿電極30之一上端側且具有寬於貫穿電極28之剖面之尺寸之一上端電極接墊34。
電子裝置10具有用於密封該上蓋14之四個邊緣之周圍之超音波接合片段。此超音波接合部36藉由透過金凸塊42、形成於上蓋34之一下方面周圍上之一四邊形之密封圖案38以及形成於基板12之一上方面週邊之一四邊形之密封圖案40而密封了整個元件設置空間16。密封圖案38係由銅所製成,而密封圖案40係由銅或鋁所製成。密封圖案38、40係整體的透過金凸塊或金電鍍而藉由銅-鋁連結物完成連結。
由於貫穿電極24包括用於密封穿孔28之下端開口之下方側電極接墊32,而於穿孔28內之柱狀電極30之填入藉由銅(導電材料)沉積於下端電極接墊32上所形成,因此避免了於形成圓狀電極30時之中心處之形成孔洞。因此,即使深寬比(厚度/孔洞直徑)為高時,柱狀電極30亦可穩定的形成。
下端電極接墊32與上端電極接墊34分別具有寬於穿孔28之剖面之尺寸,因而可緊密地密封穿孔28。如此確保了元件安裝空間16之密閉性。由於下端電極接墊32與上端電極接墊34分別具有寬於穿孔28之剖面之一尺寸。如此之較寬表面區域適用作為連接區域之用,並有利於如銲接之連結程序之操作。
以下藉由第3-14圖說明形成穿孔24之方法。
於第3圖所示之步驟1A中,於作為支撐體之一矽晶圓44表面上藉由層積方法以形成一膜狀之黏著膠帶46。黏著膠帶46緊密黏著於矽晶圓44之表面,其具有位於其上表面與下表面黏著層之兩面黏著特性。黏著膠帶46係用於黏著下文中所述之阻劑層(黏著層)52與矽晶圓44。因此,黏著膠帶46可於穿孔24形成後,經由一熱處理之施行以曝光微膠囊而減少其接觸區域,因而移除之。
於第4圖所示之步驟2A中,於形成於矽晶圓44之表面上之黏著膠帶46之一上表面上形成晶種層48。形成晶種層48之方法例如藉由真空沉積或濺鍍方式所形成之銅塗佈層,以及例如一銅薄片(copper coil)之金屬薄片之沉積。
於第5圖所示之步驟3A中,於晶種層48之表面上藉由沉積或滾輪擠壓法而形成一乾膜(dry film)50。乾膜50係為一雙層結構,其包括利用一黏著層連結於阻劑層52之一上表面上之一保護層(PET層)53。阻劑層52緊密地黏著於晶種層48之表面。阻劑層52係為由光敏感性有機材料組成之一負型阻劑層,其於曝光時會失去其黏著性而其未曝光部份可藉由顯影劑溶解而移除之。雖然於本實施例中阻劑層52係藉由形成乾膜50而形成於晶種層48表面,阻劑層52可藉由其他方法,例如印刷方式,而不限定使用乾膜50所形成。此外,亦可採用由環氧樹脂或聚亞醯胺樹脂之黏著劑作為黏著層以取代阻劑層52之使用。
於第6圖所示之步驟4A中,顯示了乾膜50中之保護層53自阻劑層52處脫落並分離之情形。由於阻劑層52之上下表面皆具有黏著性,而介於阻劑層52之下表面與晶種層48間之黏著關係阻劑層52之上表面與保護層53間之黏著關係為強。因此,當保護層53脫落後,阻劑層52並不會與晶種層48分離。阻劑層52具有介於10-15微米(μm)之一厚度,其相當於下文中所述之下端電極接墊32之厚度。
於第7圖所示之步驟5A中,接著將由矽晶圓製成之上蓋14安裝於阻劑層52之黏著表面上。如前所述,形成於位於上蓋14之下方表面之中心處之元件安裝空間16內凹口14b係形成於上蓋14之內。數個穿孔28則形成垂直延伸向下通過並突出基座14c而環繞凹口14b。上蓋14經擠壓朝向阻劑層52,使得基座14c之底面擠壓接合於阻劑層52之黏著表面。於步驟5A中,上蓋14係直接地擠壓接合於阻劑層52之表面而無須使用任何黏著膠帶,因而免於黏著膠帶的使用並簡化了製程流程。
於本實施例中,由於阻劑層52尚未曝光,於後續製程中,阻劑層52係固定於上蓋14上而不會失去其黏著性。本實施例中穿孔28具有約為30-60微米之內徑D以及介於約100-200微米之高度H。
於第8圖所示之步驟6A中,接著於各穿孔28內注入顯影劑以溶解對應於穿孔之一下方開口處之一區域A內之阻劑層52。為了將用於顯影之顯影劑注入至穿孔28處,可應用浸入式顯影系統(dip development system),以將安裝於矽晶圓44上之上蓋14浸入於顯影劑內或可藉由一噴灑顯影系統(spray development system)將顯影劑自其上表面噴灑至上蓋14之上方。上述兩顯影系統皆可溶解對應於穿孔28之一下方開口之區域A內阻劑層52,因此藉由控制滲透時間,便可形成具有一寬度Da(>D)大於穿孔28之內徑D之一凸緣空隙(flange clearance)54。
換句話說,自阻劑層52之表面滲透進入於對應於穿孔28之下方開口之區域A之顯影劑於其於厚度方向溶解了阻劑層52。隨著滲透時間的延長,顯影劑之滲透亦沿著其放射方向而溶解大於穿孔28之下方空間之區域之阻劑層52。滲透時間之設定則依據滲透速度以及隨著阻劑層52材料總類與顯影劑之類型有所不同。
接著,施行電漿灰化程序,藉由電子碰撞分解並利用電漿以產生活化於溶解之於區域A內阻劑層52內之氧原子。如此,自凸緣空隙54處移除了阻劑層52。上述電漿灰化成蓄亦改善了於下一步驟之電鍍程序中之電鍍溶液之濕潤效果(wetting efficiency)。
於第9圖所示之步驟7A中,接著於為穿孔28之底部所露出晶種層48之表面鍍金,以形成作為阻障金屬之一金層56,藉以避免貫穿電極24之擴散。接著,於金層56之一上表面處鍍鎳,以形成一鎳層58。接著,於鎳層58上藉由電化學電鍍法沉積銅,因而於穿孔28內側形成柱狀介層物60之一柱狀部60b。柱狀介層物60係於穿孔28內以鎳層58作為一基礎層表面而由下往上藉由沉積銅所形成。如此可避免了於柱狀介層物60之中心部附近形成孔洞,並可藉由沉積銅而填滿穿孔28至其上方開口。
由於金層56與鎳層58係形成於凸緣空隙54之內,金層56與鎳層58之尺寸寬於穿孔28之剖面。柱狀介層物60之沉積於鎳層58上之銅之突出部60a亦具有寬於穿孔28之剖面之尺寸。金層56、鎳層58以及銅凸出部60a構成了下端電極接墊32。銅之柱狀部60b沉積於對應於柱狀電極30處之銅之凸出部60a上。下端電極接墊32之電鍍結構可為包括鎳與鈀之一雙層電鍍結構(其中鈀於上側)或可為包括鎳、鈀與金之一三層電鍍結構(其中金在上側)。
於如第10圖所示之步驟8A中,接著於上蓋14之上表面藉由一沉積方法以形成一負型阻劑層62之乾膜。於對應於於柱狀介層物60上方端之一區域B內負型阻劑層62經曝光與硬化後並藉由顯影劑移除未曝光部份之負型阻劑層62。經由此圖案化程序,因而溶解了寬於穿孔28上方開口內之部分負型阻劑層62。如此形成了連結柱狀介層物60之上方端(穿孔28之上方側)之凸出空隙(flange clearance)62a。此形成於負型阻劑層62內之凸出空隙62a具有寬於穿孔28內徑D一寬度Db(>D)。
於第11圖所示之步驟9A中,藉由電化學電鍍法於銅之柱狀部60b之上方端處形成銅之凸出部60c。此銅之凸出部60c具有寬於穿孔28之剖面一尺寸,由於形成於凸出空隙62a內之銅之凸出部60c具有寬於穿孔28之剖面之一區域。因此,可藉由電化學電鍍於銅凸出部60c之一上方表面形成鎳層64。接著,藉由電化學電鍍法,於鎳層64之上表面電化學電鍍形成金層(或錫層)66以作為阻障層。金層或錫層66、鎳層65與銅之凸出部60c構成了上端電極接墊34。
電極接墊34之電鍍結構可為包括鎳及鈀(鈀於上側)之一雙層電鍍結構或可為包括鎳、鈀與金(金於上側)之一三層電鍍結構。
於第12圖所示之步驟10A中,使用移除劑(例如鹼液、氫氧化鈉等等)經由浸潤而移除於上蓋14上負型阻劑層62之露出部份。
於第13圖所示之步驟11A中,接著將矽晶圓44置於一烘焙程序中而加熱至一高溫,使得黏著膠帶46中之微膠囊***。當黏著膠帶46內之微膠囊***後,因而減低黏著膠帶之接觸區。因此,便可輕易自晶種層48處分離透過黏著膠帶46連結於晶種層48之矽晶圓。
亦可使用其他分離矽晶圓44之方法而不已上述方法為限。舉例來說,矽晶圓44可藉由摩擦法(buffing)所移除。
於第14圖所示之步驟12A中,藉由移除蝕刻晶種層48。接著,藉由移除劑(例如鹼液、氫氧化鈉等)移除黏著於上蓋之下方表面之阻劑層52。如此,便完成了形成有貫穿電極24之上蓋14。
藉由前述方法所形成之貫孔電極24具有以下外型,其中柱狀電極30填入於自基板14a延伸至上蓋14之穿孔28內,於柱狀電極30之下端側形成有下端電極接墊,其具有寬於穿孔28之剖面之一尺寸,以及形成於圓柱狀電極30之上端側之上端電極接墊34,其亦具有寬於穿孔28之剖面之一尺寸並形成整體的連結。因此,穿孔28之上端與下端之緊密的密封。此外,由於圓柱狀電極30自底部之下端電極接墊32往上部而形成,如此可避免於穿孔28之中心處形成孔洞。因此,於穿孔28中可穩定的形成柱狀電極30,既使於深寬比(寬度/孔洞直徑)為高之情形。
於本實施例中,晶種層48係形成於矽晶圓44表面,且其間設置有黏著膠帶46設置於。因此,於貫穿電極24形成後,矽晶圓44可藉由加熱黏著膠帶46而輕易的自晶種層44處分離。如此簡化了製造流程且降低了製造成本。
第二實施例:以下藉由第15-26圖以說明依據本發明之第二實施例之形成貫穿電極24之方法。於第2實施例中,相同於第一實施例內之構件將使用相同之標號。
於第15圖所示之步驟1B中,首先提供一玻璃晶圓70作為一支撐體。
於第16圖所示之步驟2B中,於玻璃晶圓70之一上表面形成一晶種層48。形成該晶種層48之方法例如為銅或鎳之真空沉積法或濺鍍法。
於第17圖所示之步驟3B中,藉由沉積方法於晶種層48之表面形成一乾膜50。
於第18圖所示之步驟4B中,分離乾膜50中之阻劑層52與保護層53。
於第19圖所示之步驟5B中,將由矽晶圓製成之上蓋14黏著於阻劑層52之一黏著表面。如前所述,形成於位於上蓋14之下方表面之中心處之元件安裝空間16內(請參照第1圖)凹口14b係形成於上蓋14之內。數個穿孔28則形成垂直延伸向下通過並突出基座14c而環繞凹口14b。上蓋14經擠壓朝向阻劑層52,使得基座14c之底面擠壓接合於阻劑層52之黏著表面。
於第20圖所示之步驟6B中,接著於各穿孔28內注入顯影劑以溶解對應於穿孔之一下方開口處之一區域A內之阻劑層52(請參照第8圖)。進入穿孔28內之顯影劑可溶解對應於穿孔28之一下方開口之區域A內阻劑層52,因此藉由控制滲透時間,便可形成具有一寬度Da(>D)大於穿孔28之內徑D之一凸緣空隙(flange clearance)54。
接著,施行電漿灰化程序,藉由電子碰撞分解並利用電漿以產生活化於溶解之於區域A內阻劑層52內之氧原子。如此,自凸緣空隙54處移除了阻劑層52。上述電漿灰化成蓄亦改善了於下一步驟之電鍍程序中之電鍍溶液之濕潤效果(wetting efficiency)。
於第21圖所示之步驟7B中,接著於為穿孔28之底部所露出晶種層48之表面鍍金,以形成作為阻障金屬之一金層56,藉以避免貫穿電極24之擴散。接著,於金層56之一上表面處鍍鎳,以形成一鎳層58。接著,於鎳層58上藉由電化學電鍍法沉積銅,因而於穿孔28內側形成柱狀介層物60之一柱狀部60b。柱狀介層物60係於穿孔28內以鎳層58作為一基礎層表面而由下往上藉由沉積銅所形成。如此可避免了於柱狀介層物60之中心部附近形成孔洞,並可藉由沉積銅而填滿穿孔28至其上方開口。
由於金層56與鎳層58係形成於凸緣空隙54之內,金層56與鎳層58之尺寸寬於穿孔28之剖面。柱狀介層物60之沉積於鎳層58上之銅之突出部60a亦具有寬於穿孔28之剖面之尺寸。
於第22圖所示之步驟8B中,接著於上蓋14之上表面藉由一沉積方法以形成一負型阻劑層62之乾膜。於對應於於柱狀介層物60上方端之一區域B內負型阻劑層62經曝光與硬化後並藉由顯影劑移除未曝光部份之負型阻劑層62。經由此圖案化程序,因而溶解了寬於穿孔28上方開口內之部分負型阻劑層62。如此形成了連結柱狀介層物60之上方端(穿孔28之上方側)之凸出空隙(flange clearance)62a。此形成於負型阻劑層62內之凸出空隙62a具有寬於穿孔28內徑D一寬度Db(>D)。
於第23圖所示之步驟9B中,藉由電化學電鍍法於銅之柱狀部60b之上方端處形成銅之凸出部60c。此銅之凸出部60c具有寬於穿孔28之剖面一尺寸,由於形成於凸出空隙62a內之銅之凸出部60c具有寬於穿孔28之剖面之一區域。因此,可藉由電化學電鍍於銅凸出部60c之一上方表面形成鎳層64。接著,藉由電化學電鍍法,於鎳層64之上表面電化學電鍍形成金層(或錫層)66以作為阻障層。
於第24圖所示之步驟10B,使用移除劑(例如鹼液、氫氧化鈉等等)經由浸潤而移除於上蓋14上負型阻劑層62之露出部份。
於第25圖所示之步驟11B中,接著將玻璃晶圓70置於一烘焙程序中而加熱至一高溫,因而硬化了阻劑層52並降低了阻劑層52之黏著度,使得阻劑層52可自上蓋14處分離。
於第26圖所示之步驟12B中,自下側端分離玻璃晶圓70使得上蓋14之下側表面之阻劑層52因而分離。如此因而完成了具有貫穿電極14之上蓋14。
當於步驟11B中加熱玻璃晶圓70以分離阻劑層52時,亦可施行其他方法以分離之。舉例來說,自上蓋14之下方表面處移除阻劑層52可藉由碾磨法移除玻璃晶圓70,並接著藉由蝕刻移除晶種層48而達成。
藉由前述方法所形成之貫孔電極24具有以下外型,其中柱狀電極30填入於自基板14a延伸至上蓋14之穿孔28內,於柱狀電極30之下端側形成有下端電極接墊,其具有寬於穿孔28之剖面之一尺寸,以及形成於圓柱狀電極30之上端側之上端電極接墊34,其亦具有寬於穿孔28之剖面之一尺寸並形成整體的連結。因此,穿孔28之上端與下端之緊密的密封。此外,由於圓柱狀電極30自底部之下端電極接墊32往上部而形成,如此可避免於穿孔28之中心處形成孔洞。因此,於穿孔28中可穩定的形成柱狀電極30,既使於深寬比(寬度/孔洞直徑)為高之情形。
於本實施例中,玻璃晶圓70可藉由加熱***有晶種層48於其間之於玻璃晶圓70表面之阻劑層52而輕易的自上蓋14處分離。如此簡化了製成並降低了製造成本。
經由前述實施例係採用用於電子裝置微機電封裝物解釋,本發明亦可應用於其他產品中之電極方面(例如具用於連結上端線路圖案與下段線路圖案穿孔之內連物與產品)。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...電子裝置
12、14a...基板
14...上蓋
14b...凹口
14c...基座
15...絕緣層
16...元件安裝空間
18...功能元件
20...電極
22、36...超音波連結部
24...貫穿電極
26...金凸塊
27...錫凸塊
28...穿孔
30...柱狀電極
32...下端電極接墊
34...上端電極接墊
38、40...密封圖案
44...矽晶圓
46...黏著膠帶
48...晶種層
50...乾膜
52...阻劑層
53...保護層
54、62a...凸緣空隙
56...金層
58、64...錫層
60a、60c...突出部
60b...柱狀部
60...柱狀介層物
62...負型阻劑層
66...金錫層
70...玻璃晶圓
A...穿孔下方開口之區域
D...穿孔之內徑
B...穿孔上方開口之區域
H...穿孔之高度
Da、Db...凸緣空隙的內徑
第1圖為一垂直剖面圖,用以說明依據本發明之一實施例之電子裝置中之一貫穿電極與形成此貫穿電極之方法;第2圖為一放大之垂直剖面圖,用以圖示一貫穿電極;第3-14圖為一系列之垂直剖面圖,用以圖示一第一實施例中之製程步驟;以及第15-26圖為一系列垂直剖面圖,用以圖示一第二實施例中之製程步驟。
12、14a‧‧‧基板
14‧‧‧上蓋
14b‧‧‧凹口
14c‧‧‧基座
15‧‧‧絕緣層
16‧‧‧元件安裝空間
20‧‧‧電極
24‧‧‧貫穿電極
22、36‧‧‧超音波連結部
26‧‧‧金凸塊
27‧‧‧錫凸塊
28‧‧‧穿孔
30‧‧‧柱狀電極
32‧‧‧下端電極接墊
34‧‧‧上端電極接墊
38、40‧‧‧密封圖案
Claims (6)
- 一種形成貫穿電極之方法,包括下列步驟:一第一步驟,於一支撐體(support body)之一表面上形成一晶種層;一第二步驟,於該晶種層之一表面上形成一黏著層(adhesive layer);一第三步驟,壓擠其內具有一穿孔之一基板至該黏著層上;一第四步驟,移除連結於基板上之該穿孔之該黏著層之一部分,於該穿孔之一下端處形成寬於該穿孔之一剖面之一空隙;一第五步驟,於該空隙與該穿孔內填入一導體並形成覆蓋該穿孔之下端之一下端電極接墊與填滿該穿孔之一柱狀電極(column electrode);以及一第六步驟,自該基板上移除該支撐體、該晶種層與該黏著層。
- 如申請專利範圍第1項所述之形成貫穿電極之方法,其中該第五步驟更包括:形成構成該下端電極接墊之一金(Au)層於該晶種層上之步驟;形成一鎳(Ni)層於該金層之一表面上之步驟;以及形成一銅層於該鎳層之表面,形成該柱狀電極之步驟。
- 如申請專利範圍第1或2項所述之形成貫穿電極之方法,更包括: 將一黏著膠帶貼於該支撐體之表面,接著於該第一步驟中形成該晶種層於該黏著層之一黏著表面上;以及於第五步驟中形成該柱狀電極後,於第六步驟中藉由加熱該黏著膠帶,以分離該支撐體處與該晶種層。
- 如申請專利範圍第1或2項所述之形成貫穿電極之方法,其中於該第一步驟中,該晶種層係形成於該支撐體之該表面上,而該黏著層接著形成於該晶種層上;以及於該第五步驟中,於該穿孔內側形成該柱狀電極後,於該第六步驟中則藉由加熱該黏著層以分離該支撐體與該晶種層。
- 如申請專利範圍第1或2項所述之形成貫穿電極之方法,其中該黏著層包括一光阻層;以及該第四步驟更包括下列步驟:藉由一顯影程序移除形成於連結該基板之該穿孔之該區域內該光阻層之一步驟;以及於該穿孔之該下端處形成寬於該穿孔之剖面之該空隙之一步驟。
- 如申請專利範圍第1或2項所述之形成貫穿電極之方法,更包括下列步驟:形成一阻劑層於該基板之一上表面以及於該阻劑層內形成寬於該穿孔之一上端之剖面之一開口之一步驟;於該阻劑層內之該開口內填入一導體,以形成連結於該柱狀電極之一上端之一上端電極接墊之一步驟;以及移除環繞該上端電極接墊之該阻劑層之一步驟。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004191488A JP3751625B2 (ja) | 2004-06-29 | 2004-06-29 | 貫通電極の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200603237A TW200603237A (en) | 2006-01-16 |
TWI381482B true TWI381482B (zh) | 2013-01-01 |
Family
ID=34941762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094120930A TWI381482B (zh) | 2004-06-29 | 2005-06-23 | 形成貫穿電極之方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US20060001173A1 (zh) |
EP (1) | EP1612859B1 (zh) |
JP (1) | JP3751625B2 (zh) |
KR (1) | KR101117618B1 (zh) |
CN (1) | CN100461357C (zh) |
DE (1) | DE602005019124D1 (zh) |
TW (1) | TWI381482B (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100620810B1 (ko) * | 2005-03-07 | 2006-09-07 | 삼성전자주식회사 | Mems 소자 패키지 및 그 제조방법 |
US7633167B2 (en) * | 2005-09-29 | 2009-12-15 | Nec Electronics Corporation | Semiconductor device and method for manufacturing same |
TWI324800B (en) | 2005-12-28 | 2010-05-11 | Sanyo Electric Co | Method for manufacturing semiconductor device |
US7704800B2 (en) * | 2006-11-06 | 2010-04-27 | Broadcom Corporation | Semiconductor assembly with one metal layer after base metal removal |
JP5154819B2 (ja) * | 2007-04-03 | 2013-02-27 | 新光電気工業株式会社 | 基板及びその製造方法 |
JP5193503B2 (ja) * | 2007-06-04 | 2013-05-08 | 新光電気工業株式会社 | 貫通電極付き基板及びその製造方法 |
JP5137059B2 (ja) * | 2007-06-20 | 2013-02-06 | 新光電気工業株式会社 | 電子部品用パッケージ及びその製造方法と電子部品装置 |
TW200919593A (en) * | 2007-10-18 | 2009-05-01 | Asia Pacific Microsystems Inc | Elements and modules with micro caps and wafer level packaging method thereof |
KR100986296B1 (ko) * | 2008-09-05 | 2010-10-07 | 삼성전기주식회사 | 반도체 패키지 및 그 제조 방법 |
JP5453763B2 (ja) * | 2008-10-27 | 2014-03-26 | 大日本印刷株式会社 | 貫通電極基板の製造方法 |
US20120314390A1 (en) * | 2010-03-03 | 2012-12-13 | Mutual-Tek Industries Co., Ltd. | Multilayer circuit board |
JP5423572B2 (ja) | 2010-05-07 | 2014-02-19 | セイコーエプソン株式会社 | 配線基板、圧電発振器、ジャイロセンサー、配線基板の製造方法 |
JP2012004166A (ja) * | 2010-06-14 | 2012-01-05 | Fujitsu Ltd | 配線基板、配線基板組立体及び半導体装置 |
CN101916754B (zh) * | 2010-06-29 | 2012-08-29 | 香港应用科技研究院有限公司 | 通孔和通孔形成方法以及通孔填充方法 |
JP5619542B2 (ja) * | 2010-09-08 | 2014-11-05 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体基板の処理方法及び半導体装置の製造方法 |
US10526198B2 (en) | 2011-03-04 | 2020-01-07 | Texas Instruments Incorporated | Infrared sensor design using an epoxy film as an infrared absorption layer |
WO2013076830A1 (ja) * | 2011-11-22 | 2013-05-30 | 富士通株式会社 | 電子部品およびその製造方法 |
US8987871B2 (en) * | 2012-05-31 | 2015-03-24 | Stmicroelectronics Pte Ltd. | Cap for a microelectromechanical system device with electromagnetic shielding, and method of manufacture |
JP5874690B2 (ja) | 2012-09-05 | 2016-03-02 | 株式会社デンソー | 半導体装置の製造方法 |
JP2015177382A (ja) | 2014-03-15 | 2015-10-05 | キヤノン株式会社 | 素子電極が貫通配線と繋がったデバイス、及びその製造方法 |
US10882737B2 (en) | 2016-03-24 | 2021-01-05 | Agency For Science, Technology And Research | Through silicon interposer wafer and method of manufacturing the same |
CN108811354A (zh) * | 2017-04-28 | 2018-11-13 | 鹏鼎控股(深圳)股份有限公司 | 电路板及其制作方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258457A (ja) * | 1988-04-08 | 1989-10-16 | Nec Corp | 半導体集積回路の実装構造およびその製造方法 |
US20040043615A1 (en) * | 2002-08-30 | 2004-03-04 | Fujikura Ltd. | Manufacturing method of a semiconductor substrate provided with a through hole electrode |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3008143C2 (de) * | 1980-03-04 | 1982-04-08 | Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern | Verfahren zum Herstellen von gedruckten Leiterplatten mit Lochungen, deren Wandungen metallisiert sind |
JPH05243735A (ja) | 1992-03-03 | 1993-09-21 | Hitachi Chem Co Ltd | 多層配線板の製造法 |
JPH07307565A (ja) | 1994-05-10 | 1995-11-21 | Hitachi Chem Co Ltd | 配線板の製造方法 |
US5579207A (en) | 1994-10-20 | 1996-11-26 | Hughes Electronics | Three-dimensional integrated circuit stacking |
JP3724110B2 (ja) * | 1997-04-24 | 2005-12-07 | 三菱電機株式会社 | 半導体装置の製造方法 |
US6039889A (en) * | 1999-01-12 | 2000-03-21 | Fujitsu Limited | Process flows for formation of fine structure layer pairs on flexible films |
JP3681155B2 (ja) * | 1999-12-22 | 2005-08-10 | 新光電気工業株式会社 | 電子部品の実装構造、電子部品装置、電子部品の実装方法及び電子部品装置の製造方法 |
US6605551B2 (en) * | 2000-12-08 | 2003-08-12 | Intel Corporation | Electrocoating process to form a dielectric layer in an organic substrate to reduce loop inductance |
US6441486B1 (en) * | 2001-03-19 | 2002-08-27 | Texas Instruments Incorporated | BGA substrate via structure |
JP3860000B2 (ja) * | 2001-09-07 | 2006-12-20 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP3904484B2 (ja) | 2002-06-19 | 2007-04-11 | 新光電気工業株式会社 | シリコン基板のスルーホールプラギング方法 |
JP3910907B2 (ja) * | 2002-10-29 | 2007-04-25 | 新光電気工業株式会社 | キャパシタ素子及びこの製造方法、半導体装置用基板、並びに半導体装置 |
KR100691725B1 (ko) * | 2002-12-11 | 2007-03-12 | 다이니폰 인사츠 가부시키가이샤 | 다층 배선기판 및 그 제조 방법 |
-
2004
- 2004-06-29 JP JP2004191488A patent/JP3751625B2/ja not_active Expired - Fee Related
-
2005
- 2005-06-23 TW TW094120930A patent/TWI381482B/zh not_active IP Right Cessation
- 2005-06-24 EP EP05253943A patent/EP1612859B1/en not_active Expired - Fee Related
- 2005-06-24 DE DE602005019124T patent/DE602005019124D1/de active Active
- 2005-06-27 US US11/167,750 patent/US20060001173A1/en not_active Abandoned
- 2005-06-28 KR KR1020050056136A patent/KR101117618B1/ko not_active IP Right Cessation
- 2005-06-29 CN CNB2005100811765A patent/CN100461357C/zh not_active Expired - Fee Related
-
2006
- 2006-08-07 US US11/499,947 patent/US7498259B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01258457A (ja) * | 1988-04-08 | 1989-10-16 | Nec Corp | 半導体集積回路の実装構造およびその製造方法 |
US20040043615A1 (en) * | 2002-08-30 | 2004-03-04 | Fujikura Ltd. | Manufacturing method of a semiconductor substrate provided with a through hole electrode |
Also Published As
Publication number | Publication date |
---|---|
KR20060048594A (ko) | 2006-05-18 |
US7498259B2 (en) | 2009-03-03 |
EP1612859B1 (en) | 2010-01-27 |
JP3751625B2 (ja) | 2006-03-01 |
TW200603237A (en) | 2006-01-16 |
EP1612859A2 (en) | 2006-01-04 |
US20060001173A1 (en) | 2006-01-05 |
EP1612859A3 (en) | 2006-02-01 |
KR101117618B1 (ko) | 2012-03-07 |
DE602005019124D1 (de) | 2010-03-18 |
JP2006013330A (ja) | 2006-01-12 |
CN1716558A (zh) | 2006-01-04 |
US20060267210A1 (en) | 2006-11-30 |
CN100461357C (zh) | 2009-02-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI381482B (zh) | 形成貫穿電極之方法 | |
JP5347222B2 (ja) | 半導体装置の製造方法 | |
US8230591B2 (en) | Method for fabricating an electronic device substrate | |
JP2014090183A (ja) | 接合層を用いて基板に接続された金属ポストを有する超小型電子基板 | |
US20100071944A1 (en) | Chip capacitor embedded pwb | |
JP2002261190A (ja) | 半導体装置、その製造方法及び電子機器 | |
JP2011501410A (ja) | 頑健な多層配線要素および埋設された超小型電子素子とのアセンブリ | |
TWI666737B (zh) | 佈線基板、製造佈線基板之方法及電子組件裝置 | |
TWI390684B (zh) | 半導體封裝及其製造方法 | |
CN109844934B (zh) | 用于低温接合的结构和方法 | |
JP5543754B2 (ja) | 半導体パッケージ及びその製造方法 | |
CN113517270A (zh) | 大板级扇出基板预埋芯片的低厚度封装结构的制备方法 | |
CN103515311B (zh) | 芯片封装和制造芯片封装的方法 | |
KR20070068268A (ko) | 배선 기판의 제조 방법 | |
JP6643213B2 (ja) | リードフレーム及びその製造方法と電子部品装置 | |
CN111106013B (zh) | Tmv结构的制备方法、大板扇出型异构集成封装结构及其制备方法 | |
JP2002076166A (ja) | 樹脂封止型半導体装置及びその製造方法 | |
CN113299569A (zh) | 大板级扇出基板倒装芯片封装结构的制备方法 | |
JP2009043858A (ja) | 半導体装置およびその製造方法 | |
JP5429890B2 (ja) | 配線用電子部品及びその製造方法、並びに該配線用電子部品を組み込んで用いる電子デバイスパッケージ及びその製造方法 | |
JP6573415B1 (ja) | ビア配線形成用基板及びビア配線形成用基板の製造方法並びに半導体装置実装部品の製造方法 | |
JP7445717B2 (ja) | 多層基板の表面処理層構造 | |
TW200950031A (en) | Method for fabricating pakage substrate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |