200950031 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體裝置之製法，尤指一種具 細間距電性連接結構之封裝基板製法。 八 【先前技術】 隨著電子產業的蓬勃發展，電子產品之外型趨向㈣ 紐小’在功能上並逐漸邁入高性能、高功能、高速度化的 ^向發展。而覆晶式（Flip chip)半導體封裳技術為一種 進之半導體職技術，在現行覆晶式半導體封裝技術 二接:於半導體晶片上設有電極墊’並於該電極墊上形成 :與焊接凸塊，俾提供該半導體晶片透過該些焊接== 連接該封裝基板。 ^ 处由於越來越多的產品設計趨向於小型化、高速度、多 因此’覆晶技術的應用範圍將不斷擴大，成爲又一種 〇^率的晶片封裝技術，相較於打線接合（心β 術’覆晶技術之特徵在於半導體S κ盥 遠接孫, 與縣基板間的電性 優點在於：接凸塊而非一般之金線，而該種覆晶技術之 其可提高封裝密度以降低封裝元件尺寸，同時， =種覆B日技術不需使用長度較長之金線，故可提高電性性 上電至1D圖，係為習知於基板之電性接觸塾 —電料成導電凸柱及焊接材料之製法；如第1A圖所 不’知於一表面形成有複數電性接觸墊1〇]之基板本體 110782 5 200950031 有，且於該防焊層”中以曝 -，而該開孔1丨。底二露丨=出各該電性接觸塾 影能力的限制，而有：二=請上’因顯 y c 、 y \〉查產生，稱之為腺、、杏 命Γ易^響查11Ga於細小孔徑時愈容易產生二 _生:2:的可靠度;如第1β圖所示，接著於 生接觸塾;101、防焊屏 有導電層12，復於該導電；丨=;開孔Π。中形成 β層13中形成有門口 1qn 上形成有阻層13,且該阻 上之導電声12^如―，以露出形成於該電性接觸墊101 進行電，#le圖所示’接著藉由該導電層12 .純m， U生接觸塾！〇1上形成金屬凸柱14 .2 = _15;請參閱第，圖，之後移除該阻層13及 15。盍之導電層12 ’以露出該金屬凸柱14及焊接材料 孫士上述製法中，受限於對位精度，該阻層13之開口 13〇 ❹’、:该防焊層U之開子L 11〇，使該金屬凸柱 二及開孔U。之間形成頸縮之肩部141(如第1C: :虽該電性接觸墊101與金屬凸柱14持續縮小，且該 "妾材料15僅結合於該金屬凸柱14上使該金屬凸: 月邛141办易因後續熱循環製程中因熱應力導致應 力集中，致使該金屬凸柱14於肩部141處產生龜裂，： 屯性連接，且該金屬凸才主14之肩4 部分空間。 用7 再者，因以曝光顯影之圖案化製程於該防焊層丨1中 Π0782 6 200950031 形成有開孔11 〇，該開子In 1 0底。ί5外露之電性接觸墊1 〇】 *邊存有膠逢11Ga，使該開孔U0底部開口過小，導致 .該金f:柱14與該電性接觸塾ιοί之接觸面積縮小，甚 至可此造成該金屬凸柱η盘雷柯妓辟鈾 遠接不P/、屯性接觸墊丨〇1之間的電性 連接不良，或該金屬凸柱14與電性接觸塾101表面 強度降低，進而影響電性連接 1Λ1 ΒΒ 牧<οπ質，且當該電性接觸墊 1 〇 1之間的間距持續縮減時， I 1ni Ba 4金屬凸柱14與電性接觸 墊101之間的結合面積更小，使該金屬凸柱14 β觸墊101之間的結合性降低， 包注接 易因後續熱循環製程中因 …應力導致該電性接觸塾1G1與金屬凸柱14之間產生脫 離，進而影響電性連接功能。 因此，#於上述之問題，如何避免習知技術於細間距 B曰封裝基板上之金屬凸柱與電性接觸墊間的結合性 ’導致電性連接不良的情況，實已成目前亟欲解決的課 喊。 【發明内容】 馨於上述習知技術之缺失，本發明之主要目的係提供 -種封I基板f法，能減少電性接觸墊結合性不佳之問 本發明之主要目的係提供—種封褒基板製法，能提供 細間距之電性接觸墊。 為達上述目的及其他目；SS- ΗΒ ,*» 曰的本發明揭露一種封裝基板 製法’係包括··提供一基板本體，於1 土似+肢於具至少一表面具有複 數電性接觸墊；於該電性接觸執卜你士 镣躅墊上形成有凸柱；於該基板 110782 7 200950031 印刷形成有防辉層，該防焊層係低於 高於該防輝層，且該防輝層係未覆蓋該 .凸柱^曝光顯影製程於該防焊層中形成有複數開孔，以 對應洛出該電性接觸塾夺 該凸柱尺寸；於該防孔尺寸係大於 上:成有弟二導電層;於該第二導電層上形成有第三阻 .ΐ開層中形成有複數第三開口區，以對應露出 β今門孔及-弟一導電層’且該第三開口區大於該開孔;於 ❹該開孔及弟三開口區中雷 電鐘士成有知接材料，以完全包覆 ΐ阻層及^電性連接該凸柱及電性接觸塾；以及移除該第 材料。θ八所覆盖之第二導電層’以露出該防焊層及焊接 墊及Γΐ述ί封裝基板製法，該基板本體上形成電性接觸 電層·於ί第法莫係包括:於該基板本體上形成有第-導 於該第一導電層上形成有第一阻層，且該第 第一開口區’以露出部份之第一導電層；於該第 第Ί中n電層上電鑛形成該電性接觸塾；於該 中形成有第二開口區，以：出二阻層，且該第二阻層 二開口區中之電性接觸塾:電 第二阻芦、笛—K a 包鍍形成該凸柱；以及移除該 曰 阻層及該第一阻層所覆蓋之第一導電層。 rA、又依上述之製法，凸柱係為銅(Cu)、鎳(Ni)、金 U接rsn)、錯（Pb)、銀（Ag)所組成群組之其中一者； 糾接材料係為錫⑽、錯⑽、銀（Ag)、銅（㈤、鋅（Zn) 110782 8 200950031 及祕（B i )所組成群組之其中一者。 ‘ ，上所述，該開孔係對應露出各該凸柱及未為該凸柱 .所覆盍之電性接觸墊的部分或全部表面。 本發明復提供一種封裝基板製法，係包括：提供一基 板本體，於其至少一表面具有複數電性接觸墊；於該電ς 接觸墊上形成有凸柱；於該基板本體及電性接觸墊上印刷 形成有防烊層，該防焊層係低於該凸柱，使該凸極高於該 防焊層’且該防焊層係未覆蓋該凸柱；以曝光顯影製程於 ❹該料層巾形成有複數開孔，以對應露錢電性接觸塾之 表面及凸柱，該開孔尺寸係大於該凸柱尺寸；以及於該開 孔中之電性接觸墊之表面及凸柱上形成金屬，黏著層。 依上述之封裝基板製法’該基板本體上形成電S性接觸 墊及凸柱之製法，係包括：於該基板本體上形成有第一導 電層；於該第一導電層上形成有第一阻層，且該第一阻層 中形成有第一開口區，以露出部份之第一導電層；於該第 參開口區中之第一導電層上電鍍形成該電性接觸墊；於該 第一阻層及電性接觸墊上形成有第二阻層，且該第二阻層 中升7成有第二開口區，以露出部份之電性接觸墊；於該第 二開口區中之電性接觸墊上電鍍形成該凸柱；以及移除該 第二阻層、第一阻層及該第一阻層所覆蓋之第一導電層。 依上述之製法’該凸柱24係為銅（Cu)、鎳（Ni)、金 (Au)、錫（Sn) '鉛（Pb)、銀（Ag)所組成群組之其中一者； 該金屬黏著層係為金、鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、 錄/金、鈀/金及鎳/鈀/金所組成群組之其中一者。 110782 9 200950031 依上所述，該開孔係對應露出各該凸柱及未為該凸柱 ‘ 所覆蓋之電性接觸塾的部分或全部表面。 •因此，本發明之封裝基板製法，係於該基板本體上連 續電鍍電性接觸墊及凸柱，使該凸柱底部完全接置於該電 I1生接觸塾上，以提尚結合之穩固性，並於該電性接觸墊上 形成細間距之凸柱，以提高佈設密度，且使覆蓋該基板本 體之防焊層之開孔尺寸大於該凸柱尺寸，以露出該電性接 觸墊之上表面及其上之凸柱，使該焊接材料完全包覆該凸 ©柱，俾以提高結合之穩固性，進而避免產生電性連接不良 的情況。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 «月參閱第2A至2K圖，係詳細說明本發明封裝基板製 β法之剖面示意圖。 、 如第2Α圖所示，提供一基板本體2〇，於該基板本體 2〇上形成有第一導電層21a，該第一導電層21a主要係作 爲後續電鍍金屬材料所需之電流傳導路徑，其可由金屬、 合金或沉積數層金屬層所構成，如選自銅、錫、鎳、鉻、 鈦銅鉻合金或錫_鉛合金等所構成之群組之其中一者所 組成，係以濺鍍、蒸鍍、無電電鍍及化學沈積之一者形成； 或可使用例如聚乙炔、聚苯胺或有機硫聚合物等導電高分 子材料而以旋轉塗佈（spin coating )、喷墨印刷 110782 10 200950031 (ink-jet printing)或壓印（imprinting)等方式形成 ^該第一導電層21a。 . 如第2B圖所示，於該第一導電層21a上形成有第— 阻層22a，該第一阻層22a係為一例如乾膜或液態光阻等 光阻層（Photoresist)，其係利用印刷、旋塗或貼合等方 式分別形成於該第一導電層21&上，再藉由曝光影等 方式於該第一阻層22a中圖案化以形成第一開口區 220a，俾以露出部份之第一導電層2ja。 © 如第2C圖所示，於該第一開口區220a中之第一導電 層21a上電鍍形成有電性接觸墊23。 ，如第2D圖所示，於該第一阻層22a及電性接觸墊23 上形成有第二阻層22b，且該第二阻層22b中形成有第二 開口區220b，以露出部份之電性接觸墊23，該第二開口 區220b尺寸係小於第一開口區22〇&尺寸。 如第2E圖所示’於該第二開口區22〇b中之電性接觸 鬱墊23上電鍍形成有凸柱24;該凸柱％係為銅、鎳 ()金（Au)、錫（如）、鉛（Pb)、銀（Ag)所組成群組之 其中一者。 如第2F圖所示，移除該第二阻層22b、第一阻層22 及該第-阻層22a所覆蓋之第一導電層⑴，以露出㈣ 板本體20、電性接觸墊23及其上之凸柱24;接著，該負 性接觸塾23及練24之外露表面進行粗化，藉加矣 合性。 如第2G圖所示，於該基板本體20及電性接觸墊23 110782 11 200950031 上之凸柱24設有印刷網版30，以於該基板本體20及電 *性接觸塾23上以印刷形成有防焊層25，該防焊層25係 •低於該凸柱24,且該防焊層25係未覆蓋該凸柱24，使該 凸柱24间於該防焊層25提供適當高度，以利於後續盥 片接合及封裝製程之進行。 、/' 第2H 2H 1、2H-2及2H-3圖所示，於該防焊層 25中曝光顯影形成有複數開孔25G，以對應露出該凸柱 24及未為該凸柱24所覆蓋之電性接觸墊μ的部份表 ❹面’如第2Η圖所示；或於該電性接觸墊23的部份表面及 凸柱24上形成有金屬黏著層26a，如第2Η-1圖所示；或 f開孔25G亦可對應露出該凸柱24及未為該凸柱^所覆 蓋之電性接觸墊23的全部表面’如第2H_2圖所示；或於 該電性接觸墊23的全部表面及凸柱24上形成有金屬黏著 層26a，如第2H-3圖所示；其中該金屬黏著層咖係為 金、鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、鎳/金、鈀/金及鎳 ❹把/金所組成群組之其中一者；之後，以該第Μ圖所示 之結構作說明。 如第21圖所示，於該防焊層25、開孔25〇之孔壁、 電性接觸墊23及凸柱24上形成有第二導電層21b;接著 於該第二導電層21b上形成有第三阻層22c，且該第三阻 層22c中形成有複數第三開口區22〇c，以對應露出各該 開孔250中之第二導電層21b，且該第三開口區“吒大 於該開孔250。 如第2J圖所示，於該防焊層25之開孔25〇及第三開 110782 12 200950031 口區22Gc中電鍍形成有焊接材料撕，以完 •柱^並電性連接該凸柱24及電性接輕2 ㈣ .料㈣為錫㈤，、銀(Ag) = 及鉍（Bi)所組成群組之其中一者。 銲（Zn) 如第2K圖所示，移除該第三阻層如及其所覆雲之 ，以露出該防桿層25及焊接材料26二 ，用Ϊ 於該防焊層25’可減少該焊接材料26b的使 用1，並使該凸柱24深入該焊接材料勤中，而可提高 ❹，焊接材料26b與凸柱24之結合性，以及提供適當的高 X ’以利於後續與晶片接合及封裝製程之進行。 形成Ϊ = ί封裝基板製法，係於該基板本體上連續電鐘 及凸柱，使該凸柱底部完全接置於該電 墊上，俾以提高結合之穩固性，並於該電性接觸墊 上細間距之凸柱，以提高佈設密度，且使覆蓋於該基 2本體之防焊層之開孔尺寸大於該凸柱尺寸，以露出該凸 φ柱及未為該凸柱所覆蓋之電性接觸塾的部分或全部表 面由於該凸柱業已連續電鑛成形於該電性接觸塾上，即 使防焊層顯影產生膠渣’亦不致影響電性接觸塾及凸柱的 穩固性，並於後續製程使該焊接材料完全包覆該凸柱，俾 以提高結合之穩固性，進而避免產生電性連接不良的情 況；且該凸柱高於該防焊層，能提供適當高度，以利於後 續與晶片接合及封裝製程之進行。 ^上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 110782 13 200950031 在不适月本發明之精神及範脅下，對上述實施例進行修 .改。因此本發明之權利保護範圍，應如後述之申請專利範 . 圍所列。 【圖式簡單説明】 f 1A至1D圖係為習知半導體封裝基板增層製法之流 篆不意圖； 第2A至2K圖係為本發明 qΘ之封裝基板製法之剖面示意200950031 IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a package substrate having a fine pitch electrical connection structure. Eight [Prior Art] With the rapid development of the electronics industry, the appearance of electronic products tends to (4) New Zealand's function and gradually enter the development of high performance, high functionality and high speed. The Flip chip semiconductor sealing technology is a semiconductor technology. In the current flip-chip semiconductor packaging technology, an electrode pad is provided on a semiconductor wafer and formed on the electrode pad: And providing the semiconductor wafer through the solders == to connect the package substrate. ^ As more and more product designs tend to be smaller, faster, and more, the application range of flip chip technology will continue to expand, becoming another type of chip packaging technology, compared to wire bonding (heart β The technology of flip-chip technology is characterized by the fact that the semiconductor S 盥 is far away from the Sun, and the electrical advantage between it and the county substrate is that it is connected to the bump instead of the general gold wire, and the flip chip technology can increase the package density to reduce Package component size, at the same time, = B-day technology does not need to use a longer length of gold wire, so it can improve the electrical power-up to 1D map, which is known as the electrical contact of the substrate - the electrical material is conductive The method for manufacturing the stud and the solder material; as shown in FIG. 1A, the substrate body 110782 5 200950031 having a plurality of electrical contact pads formed on a surface thereof is exposed, and the solder resist layer is exposed. The opening is 1 丨. The bottom two dew = the limitation of each of the electrical contact photographic capabilities, and there are: two = please see the yc, y \> check, called gland, apricot Easy to check 11Ga in the small aperture is more likely to produce the second _: 2: the reliability; such as the first β As shown, the contact pad is formed; 101, the solder mask has a conductive layer 12, and the conductive layer is formed; 丨=; the opening Π. The resist layer 13 is formed on the gate layer 1qn formed in the β layer 13 and formed therein. The conductive sound 12^, such as ―, is exposed to be formed on the electrical contact pad 101 for electricity, as shown in Figure #', followed by the conductive layer 12. Pure m, U-contact 塾! The pillars 14 .2 = _15; please refer to the figure, and then remove the resist layers 13 and 15. The conductive layer 12' of the crucible to expose the metal studs 14 and the solder material Sun Shi in the above method is limited by the pair The positional accuracy of the opening 13 〇❹ ' of the resist layer 13 and the opening L 11 该 of the solder resist layer U form a necked shoulder 141 between the metal studs 2 and the opening U. 1C: : Although the electrical contact pad 101 and the metal stud 14 continue to shrink, and the "妾 material 15 is only bonded to the metal stud 14 to make the metal convex: the moon 141 is easy to be processed in the subsequent thermal cycle process The stress is concentrated due to thermal stress, causing the metal stud 14 to crack at the shoulder 141, which is a sinuous connection, and the metal is convex and the shoulder of the main body 14 is 4 parts of space. Because of the patterning process by exposure and development, in the solder resist layer Π1, Π0782 6 200950031 is formed with an opening 11 〇, the opener In 1 0 bottom. ί5 exposed electrical contact pad 1 * * At 11Ga, the opening at the bottom of the opening U0 is too small, resulting in a decrease in the contact area of the gold f: the pillar 14 and the electrical contact 塾ιοί, and even the metal stud n 盘 雷 妓 妓 铀 铀 铀 远P/, the electrical connection between the inert contact pads 1 is poor, or the surface strength of the metal stud 14 and the electrical contact 101 is reduced, thereby affecting the electrical connection 1Λ1 ΒΒ 牧 <οπ质, and When the spacing between the electrical contact pads 1 and 〇1 is continuously reduced, the bonding area between the I 1ni Ba 4 metal studs 14 and the electrical contact pads 101 is smaller, so that the metal studs 14 between the beta pads 101 The combination is reduced, and the package is easily separated from the metal stud 14 due to stress caused by the stress in the subsequent thermal cycle process, thereby affecting the electrical connection function. Therefore, in the above problem, how to avoid the combination of the metal studs and the electrical contact pads on the fine pitch B? package substrate by the prior art' leads to poor electrical connection, which has become a problem to be solved. The class shouted. SUMMARY OF THE INVENTION In order to eliminate the above-mentioned prior art, the main object of the present invention is to provide a method for sealing an I substrate, which can reduce the poor bondability of the electrical contact pads. The main object of the present invention is to provide a package. The substrate manufacturing method can provide fine pitch electrical contact pads. The present invention discloses a method for manufacturing a package substrate, which comprises providing a substrate body having a plurality of electrical contact pads on at least one surface of the soil. a bump is formed on the electrical contact pad; the substrate 110782 7 200950031 is printed with an anti-glaze layer, the solder resist layer is lower than the anti-glaze layer, and the anti-glaze layer is The cover is not covered. The exposure development process has a plurality of openings formed in the solder resist layer to correspondingly capture the size of the stud according to the electrical contact; the size of the anti-hole is greater than the upper: a second conductive layer; a third resistor is formed on the second conductive layer; a plurality of third open regions are formed in the split layer to correspondingly expose the β-door and the first conductive layer and the third open region is larger than The opening hole; in the opening and the third opening area, the lightning bell is formed by the lightning conductor to completely cover the barrier layer and electrically connect the protruding post and the electrical contact 塾; and remove the first material. a second conductive layer θ covered by θ8 to expose the solder resist layer and the solder pad and the method for manufacturing the package substrate, wherein the substrate body is formed with an electrical contact layer, and the substrate body comprises: Forming a first conductive layer formed on the first conductive layer, and the first open region is configured to expose a portion of the first conductive layer; and the nth electric layer is electrically connected to the first electrical layer Forming the electrical contact 塾; forming a second open area therein to: a second resistive layer, and the electrical contact 中 in the second open area of the second resistive layer: electric second resisting reed, flute-K a Coating the pillar to form the pillar; and removing the barrier layer and the first conductive layer covered by the first barrier layer. rA, according to the above method, the stud is one of a group consisting of copper (Cu), nickel (Ni), gold U connected to rsn), wrong (Pb), and silver (Ag); It is one of a group consisting of tin (10), wrong (10), silver (Ag), copper ((f), zinc (Zn) 110782 8 200950031 and secret (B i ). ', as described above, the opening is correspondingly exposed Each of the studs and a portion or all of the surface of the electrical contact pad that is not covered by the stud. The invention further provides a method for manufacturing a package substrate, comprising: providing a substrate body having a plurality of electrodes on at least one surface thereof a contact pad; a bump is formed on the contact pad; and a tamper-proof layer is formed on the substrate body and the electrical contact pad, and the solder resist layer is lower than the stud, so that the salient pole is higher than the anti-solder a solder layer 'and the solder resist layer does not cover the stud; the exposure and development process is formed on the web to form a plurality of openings to correspond to the surface and the stud of the electric contact 露, the opening size Greater than the size of the stud; and forming a metal, adhesive layer on the surface of the electrical contact pad and the stud in the opening. The method for manufacturing an encapsulating substrate, the method for forming an electric S-type contact pad and a stud on the substrate body comprises: forming a first conductive layer on the substrate body; forming a first resist layer on the first conductive layer; And forming a first opening region in the first resist layer to expose a portion of the first conductive layer; forming the electrical contact pad on the first conductive layer in the first reference opening region; a second resist layer is formed on the layer and the electrical contact pad, and the second resistive layer is raised into a second open area to expose a portion of the electrical contact pad; electrical contact in the second open area Forming the stud on the pad; and removing the second resistive layer, the first resistive layer and the first conductive layer covered by the first resistive layer. According to the above method, the stud 24 is made of copper (Cu), One of a group consisting of nickel (Ni), gold (Au), tin (Sn) 'lead (Pb), silver (Ag); the metal adhesion layer is gold, nickel, palladium, silver, tin, nickel /Palladium, Chromium/Titanium, Record/Gold, Palladium/Gold, and Nickel/Palladium/Gold. 110782 9 200950031 According to the above, the opening system The partial or total surface of each of the studs and the electrical contact 未 not covered by the studs should be exposed. Therefore, the method of manufacturing the package substrate of the present invention is to continuously electroform the electrical contact pads and the bumps on the substrate body. a column, such that the bottom of the stud is completely placed on the contact I of the electric I1 to improve the stability of the bond, and a fine pitch column is formed on the electrical contact pad to increase the layout density and cover the The size of the soldering layer of the substrate body is larger than the size of the pillar to expose the upper surface of the electrical contact pad and the protruding pillar thereon, so that the soldering material completely covers the convex column, so as to improve the bonding. The embodiment of the present invention is described below by way of specific embodiments, and those skilled in the art can easily understand the present invention by the contents disclosed in the present specification. Other advantages and effects. «Monthly Referring to Figures 2A to 2K, a schematic cross-sectional view of the β method of the package substrate of the present invention will be described in detail. As shown in FIG. 2, a substrate body 2 is provided, and a first conductive layer 21a is formed on the substrate body 2, and the first conductive layer 21a is mainly used as a current conduction path required for subsequent plating of a metal material. It may be composed of a metal, an alloy or a plurality of deposited metal layers, such as one selected from the group consisting of copper, tin, nickel, chromium, titanium-copper-chromium alloy or tin-lead alloy. One of plating, vapor deposition, electroless plating, and chemical deposition; or conductive polymer materials such as polyacetylene, polyaniline or organic sulfur polymer can be used for spin coating, inkjet printing 110782 10 200950031 The first conductive layer 21a is formed by ink-jet printing or imprinting. As shown in FIG. 2B, a first resist layer 22a is formed on the first conductive layer 21a, and the first resist layer 22a is a photoresist layer such as a dry film or a liquid photoresist. Formed on the first conductive layer 21 & by printing, spin coating or lamination, and then patterned in the first resist layer 22a by exposure or the like to form the first open region 220a, to expose Part of the first conductive layer 2ja. © As shown in Fig. 2C, an electrical contact pad 23 is electroplated on the first conductive layer 21a in the first opening region 220a. As shown in FIG. 2D, a second resist layer 22b is formed on the first resist layer 22a and the electrical contact pad 23, and a second open region 220b is formed in the second resist layer 22b to expose the portion. The electrical contact pad 23 has a second opening area 220b that is smaller in size than the first opening area 22 〇 & As shown in FIG. 2E, a bump 24 is formed on the electrical contact pad 23 in the second opening region 22〇b; the pillar is made of copper, nickel (Au), tin ( One of a group consisting of, for example, lead (Pb) and silver (Ag). As shown in FIG. 2F, the first conductive layer (1) covered by the second resist layer 22b, the first resist layer 22 and the first resist layer 22a is removed to expose the (four) board body 20, the electrical contact pads 23, and The convex column 24 thereon; then, the negative contact surface 23 and the exposed surface of the training 24 are roughened, and the coupling property is added. As shown in FIG. 2G, the pillars 24 on the substrate body 20 and the electrical contact pads 23 110782 11 200950031 are provided with a printing screen 30 for printing on the substrate body 20 and the electrical contact pads 23 There is a solder resist layer 25, which is lower than the stud 24, and the solder resist 25 does not cover the stud 24, so that the stud 24 provides an appropriate height between the solder resist layer 25. In order to facilitate the subsequent splicing and packaging process. And /' 2H 2H 1 , 2H-2 and 2H-3 are shown in the solder resist layer 25, and a plurality of openings 25G are formed in the solder resist layer 25 to correspondingly expose the studs 24 and not to be the studs 24 A part of the surface of the electrical contact pad μ is covered as shown in FIG. 2; or a metal adhesion layer 26a is formed on a part of the surface of the electrical contact pad 23 and the protrusion 24, such as the second Η-1 The opening 25G may also correspondingly expose the entire surface of the stud 24 and the electrical contact pad 23 not covered by the stud, as shown in FIG. 2H_2; or the electrical contact pad A metal adhesion layer 26a is formed on all of the surface 23 and the pillars 24, as shown in FIG. 2H-3; wherein the metal adhesion layer is gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium One of the groups consisting of nickel/gold, palladium/gold and nickel ruthenium/gold; the structure shown in the figure is explained later. As shown in FIG. 21, a second conductive layer 21b is formed on the solder resist layer 25, the hole wall of the opening 25, the electrical contact pad 23, and the stud 24; and then formed on the second conductive layer 21b. There is a third resistive layer 22c, and a plurality of third open regions 22〇c are formed in the third resistive layer 22c to correspondingly expose the second conductive layer 21b in each of the openings 250, and the third open region “吒” The opening is 250. As shown in FIG. 2J, the soldering material is torn in the opening 25 〇 of the solder resist layer 25 and the third opening 110782 12 200950031 22Gc to complete the column and the electrical property. Connecting the stud 24 and electrically connecting the light 2 (4). The material (4) is one of a group consisting of tin (five), silver (Ag) = and bismuth (Bi). Welding (Zn) as shown in Fig. 2K, Removing the third resist layer, such as the cloud thereof, to expose the anti-bar layer 25 and the solder material 26, and the solder resist layer 25' can reduce the use of the solder material 26b, and The studs 24 penetrate deep into the solder material to improve the bonding of the solder material 26b and the bumps 24, and provide a suitable high X' for subsequent wafer bonding and packaging processes. Forming Ϊ = ί package substrate method, which is a continuous electric clock and a stud on the substrate body, so that the bottom of the stud is completely connected to the electric pad, so as to improve the stability of the bond, and in the electrical contact Pads are arranged on the fine pitch to increase the layout density, and the size of the opening of the solder resist layer covering the body of the base 2 is larger than the size of the pillar to expose the convex φ pillar and the electricity not covered by the pillar Part or all of the surface of the contact enamel is formed by continuous electroforming of the stud on the electrical contact raft, even if the solder resist develops to produce slag, which does not affect the stability of the electrical contact 凸 and the stud. The subsequent process enables the solder material to completely cover the stud, so as to improve the stability of the joint, thereby avoiding the occurrence of electrical connection failure; and the stud is higher than the solder resist layer, and can provide an appropriate height to facilitate subsequent The present invention is exemplified to illustrate the principles of the present invention and its effects, and is not intended to limit the present invention. Anyone skilled in the art can use 110782 13 200950031 The above embodiments are modified and modified under the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as described in the following patent application. [Simple description of the figure] f 1A to The 1D diagram is a flow of the conventional semiconductor package substrate build-up method; the 2A to 2K diagrams are schematic diagrams of the method for manufacturing the package substrate of the present invention.
❹ 第罚-1圖係接續第2H 第2H-2圖係為第例’· 【主要元件符號說明】 10、20 基板本體 101 、 23 電性接觸墊 11、25 防焊層 110 、 250 開孔 110a 膠渣 12 導電層 13 阻層 130 開口 14 金屬凸柱 141 肩部 15 、 26b 焊接材料 21a 第一導電層 第2H-3圖係接績g 2H —貫施例’以及 ............ 2圖之實施例。 〇 110782 14 200950031 21b 第二導電層 * 22a 第一阻層 „ 220a 第一開口區 22b 第二阻層 220b 第二開口區 22c 第三阻層 220c 第三開口區 24 凸柱 〇 26a 金屬黏著層 30 印刷網版❹ The first penalty-1 is connected to the second 2H-2H-2 is the first example'· [Main component symbol description] 10, 20 substrate body 101, 23 electrical contact pads 11, 25 solder mask 110, 250 opening 110a slag 12 conductive layer 13 resist layer 130 opening 14 metal stud 141 shoulder 15 , 26b solder material 21a first conductive layer 2H-3 system g 2H - consistent example 'and... ... 2 embodiment of the figure. 〇110782 14 200950031 21b second conductive layer* 22a first resistive layer „ 220a first open region 22b second resistive layer 220b second open region 22c third resistive layer 220c third open region 24 stud 〇 26a metal adhesive layer 30 Printed version