TWI225672B - Connection terminals and manufacturing method of the same, semiconductor device and manufacturing method of the same - Google Patents
Connection terminals and manufacturing method of the same, semiconductor device and manufacturing method of the same Download PDFInfo
- Publication number
- TWI225672B TWI225672B TW092109745A TW92109745A TWI225672B TW I225672 B TWI225672 B TW I225672B TW 092109745 A TW092109745 A TW 092109745A TW 92109745 A TW92109745 A TW 92109745A TW I225672 B TWI225672 B TW I225672B
- Authority
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- Taiwan
- Prior art keywords
- protective film
- opening
- electrode
- connection terminal
- film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 27
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Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/05557—Shape in side view comprising protrusions or indentations
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13144—Gold [Au] as principal constituent
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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Description
1225672 玖、發明說明: 【發明所屬之技術領域】 本發明係有關如半導體裝置中,提供與外部配線電性連 接用之在電極墊上形成有突起電極(以下簡稱為凸塊)之連 接端子及其製造方法,以及使用其之半導體裝置及其製造 方法。 【先前技術】 近年來’卩过電子機器之小型化、高功能化,半導體裝置 趨方;小型化、多端子化及微間距化。因而逐漸採用將半導 骨豆裝置士 I於輸送膠帶封裝體(以下簡稱為TCp)之安裝方 式,或是採用將半導體裝置直接在基板上進行倒裝片接合 之安裝方式。 此種安裝方式的情況下,提供與半導體裝置之外部配線 電性連接用之連接端子,須形成在半導體裝置之電極墊上 形成連接用凸塊之構造。通常,因在電極墊上形成有保護 私極墊用(保?隻膜,因此凸塊係形成於除去電極墊上之保 護膜的部分(開口部)。 已實用化心凸塊之形成方法有:藉由電解電鏡形成金⑽)
凸塊及烊劑凸塊之;!一¥電鍍處理’及在焊墊上超音波接合 金及焊劑球之球凸塊處理。 Q 電解電鍍處理有利於多端子化及微間距化。但是,存在 需要使用兼用電解電鍍用導電膜之障壁金屬層之形成了及 光阻之塗敷、曝光及顯像’在凸塊形成部上開p,以及除 電解電鍍裝置之外,還需要錢射裝置及光裝置等製造設備 85071 1225672 之問題。 此外,基本上,球凸塊處理不需要連線焊接機以外的製 造設備。但是,焊墊間距之限度,在實用上約為8〇 “ m,在 開發上約為60 # m,上述球凸塊處理不利於微間距化及多端 子化。 其中,已實用化之最新凸塊形成處理為非電解電鍍凸塊 處理。非電解電鍍凸塊處理係在半導體裝置之電極墊上選 擇性進行非電解電鍍之方法。該處理如以下所述的形成凸 塊。 首先,除去電極墊上之氧化膜及殘留薄膜後,進行鋅酸 鹽處理,將電極墊表面之銘(A1)替換成鋅(Zn)。此時,亦可 取代鋅酸鹽處理,而進行鈀活化處理,在電極墊表面附 鈀(Pd)。 、,其次,於非電解鎳(Nl)電鍍液中浸潰上述電極墊。藉此, 進仃以下所明之非電解鎳電鍍反應。亦即,電極墊表面之 鋅或免與鎳引起替換反應,於電極塾表面析出鎳後,藉由 析出《鎳本身成為觸媒之自觸媒反應,鎳進—步析出。 鎳電鐘結束後,為求防止鎳表面氧化,而 鍍,在鎳表面使金析出。 θ挾至私 而,使用上述非電解電錢凸塊處理之凸塊形成時, 射裝置形成電鍍用導電膜。此外,亦不需要使 理’在凸塊形成邵之光阻上開口。因而與電解電鍍 乂:具有設備投資費用少的優點。此外,由於該處 〇廉價之鎳為主要材料,且通量佳,因此製造成本低 85071 1225672 使用電解電鍍處理而形成金凸塊。 另外,就藉由非電解電鍍處理而形成凸塊者,如揭示於 :日本公開專利公報昭63-164343號(1988年7月7日公開)、 日本公開專利公報昭63-3〇5532號(1988年12月13日公開)、 曰本公開專利公報平3-209725號(1991年9月12日公開)、曰 本公開專利公報平5_47768號(1993年2月26日公開卜日本公 開專利公報平8_26454 i號(1 996年i 〇月i!日公開卜 " 、主但是’以非電解電鐘處理製作凸塊之先前連接端子之構 j ’在對應於微間距化及多端子化的情況下,存在無法提 高凸塊之高度的問題。 此因非電解電鍍處理之特性。亦即,因非電解電鐘處理 係在光阻上*使用開π的處理,#電鑛±面高於保護膜時 ’電鍍亦向橫方向生長。因& ’焊墊間空間變窄之微間距 製品,於提高凸塊高度時’ τ能因鄰接之各凸塊相連而產 生短路,因此凸塊之高度受到限制。 當然’藉由縮小保護膜之開口寬度及縮小凸塊寬度,可 提高凸塊之高度。但是,縮小保護膜之開口寬度時,因電 «與凸塊之密著面積(密著部分之面積)變小,因而發生密 著強度降低的問題。亦即,保護膜之開口寬度有其下限值 :峨電極整與凸塊之密著強度,無法超過該下限值來 縮小保謾膜之開口寬度。 【發明内容】 本發明之目的在提供—秸碴山 /、 種連接邮予,與電解電鍍處理比 較,即使以設備投資f用少,且製造成本亦低之非電解電 85071 1225672 鐘處理進^千金』、皮 化,不致降低凸塊與電極塾之密著強度,且 η乙万、藉由凸塊上邵寬度小,且可提高凸塊高度之#電 解電鍍處理進行製造的構造。 為求達成上逑目的,本發明之連接端子包含:電極塾,其 :在表面形成有層狀之數個保護膜,·及突起電極,其係形成 極墊上之保護膜的開口部;其特徵為:上述保護膜包 含兩層以上,下層之保護膜之開口部大於上層之保護膜之開 口邯,上述突起電極之底部進入上層保護膜之下。 此寺由於保瘦膜係配置成層狀,因此係使用其下層保 獲膜與上層保護膜之表現。但^,㈣膜為包含兩層之疊 層膜時,下層保護膜與上層保護膜各有一層。 此外,保護膜為三層以上時,上層保護膜或下層保護膜 之土 任何一方形成兩層以上之疊層膜構造的保護膜,最 上層之保護膜的開口部最小,隨向下層而變大,最下層之 保護膜之開口部最大。 上述構造係使成層狀之數個保護膜之開口部的大小在上 層保疫膜與下層保謾膜上不同,而形成使上層保護膜突出 的構造。亦即,擴大突起電極與電極墊之密著強度之下層 保護膜的開口部,而縮小以非電解電鍍法形成突起電極時 ,電鍍亦向橫方向開始生長時之起點之上層保護膜的開口 部。 藉由形成此種構造,即使以非電解電鍍法形成突起電柘 ,配合下層保護膜之大開口部而形成其底部之突起電極, 係以底邵之一邵分進入突出之上層保護膜之下的方式形成 85071 1225672 。因此,增加^電極與電極塾之冑著面積,可確保密著 強度。此外,由於突起電極之上部超過上層保護膜之小開 口部後開始在橫方向生長,因此可抑制突起電極寬度而提 高高度。 因而’藉由形成此種連接端子,為求對應於微間距化及 多端子化,即使縮小突起電極之寬度而提高高度,鄭接之 凸塊間不致產生短路,且亦可確保突起電極與電極 著強度。 土山 為”成上述目的’丰發明之連接端子之製造方法,亦 成二二成上層保護膜之開口部後,以濕式㈣形 :=::、:Γ部’並藉由非電解電鍍法形成突起電 拉’來製造上述連接端子。 對,藉由對上層保護膜以乾式飾刻形成開口部, 可方性進行㈣之m卿成開口部, 了幸二易地加工成上層保護膜突出的 部以兆命妒不2、丄 再k 精由對此種開口 非電解電鍍法形成突起電極,可製迕上、f… 連接端子。 I込上逑<本發明之 為求達成上述目的,本發明之連接、、 為:在表面形成有層狀之數個 4万法《特 膜上,以上層#確a p又膜又笔極墊上的保護 ,於該開口: 護膜突出之方式形成開口部 吻同口 4内猎由非電 如前述之說明,係以上:/'成哭起電極。 式形成開口部,因此即使以非電解i:=膜突出之万 仍可以下層保護膜之大的開口部^ 起電極, 曰加大起電極與電極整之 85〇7i -10- 1225672 密著面積,而確保密著強度,且可以上層保護膜之小的開 口 4抑制哭起電極之上邵寬度而提高突起電極之高度。 因而,以此種製造方法製造連接端子時,為求對應於微 門距化及多‘子化,即使縮小突起電極寬度,並提高突起 包極之回度,仍可獲得在鄰接之凸塊間不致產生短路,亦 可確保突起電極與電極墊之密著強度之連接端子。 為求達成上述目的,本發明之半導體裝置之特徵為··具 備上述本發明之連接端子。 夕則述之說明,本發明之連接端子為求對應於微間距化 及夕π子化,即使縮小突起電極寬度並提高高I,在鄰接
i α鬼間不致產生短路,亦可確保突起電極與電極墊之密 著虫度® alb Κ莆此種連接端子之本發明纟 對應於微間距化及多端子化。 芊取直J
、為求達成上述目W,本發明之半導體裝置之製造方法, ㈣形成上層保護膜之開口部後,以濕式飯 起電極 護膜之開口部,並藉由非電解電鍍法形成突 部,對下:說、::猎由對上層保護膜以乾式蝕刻形成開I 、㈢保謾膜以等方性進行蝕列之@ 4 # μ y 部,^ 逆仃蝕刻炙濕式蝕刻形成開[ 了幸二易地加工成上層保護膜 開口部以非電、 $ 〕稱1猎由對此痛 明夕主遒 法形成哭起電極,可製造上述之本# 明愁+導體裝置。 、〈本金 、人達成上述",本發明之半導體裝置之製 万;表面形成有層狀之保確 法係 禾叹胰< 电極墊上之保護膜的開口部 85071 1225672 電極,來製造連接端予, 係以上層保護膜哿下層保 内’藉由非電解電鍍法形成突起 其特徵為··於製造連接端子時, ?隻膜突出之方式形成開口部。 ::述之說明,藉由以上層保護膜對下層保護膜突出之 ,形成開口邵,即使以非電解電鍍法形成㈣電柄 I以下層保護膜之大的開口部增加突起電極與電極塾之资 ::積’確保密著強度,並以上層保護膜之小的開口部: 制大起電極之上部寬度,提高突起電極之高度。 …因而,以此種製造方法製造半導體裝置:又’可獲得對應 於锨間距化及多端子化之半導體裝置,其係具備:為求對 應於微間距化及多端子化,即使縮小突起電極寬度,並提 向南度,仍可獲得在鄰接之凸塊間不致產生短路,亦可確 保哭起電極與電極墊之密著強度之連接端子。 本發明之其他目的、特徵及優點,藉由以下所示之内容 I7可充刀瞭解。此外,本發明之好處,藉由參照附圖之以 下說明即可明除。 【實施方式】 依據圖1 土圖7說明本發明一種實施形態如下。 依據圖1說明本發明之一種實施形態於下。 、圖Ua)顯示本實施形態之半導體裝置之連接端子部分的 J面構&圖1中之1係半導體基板,2係電極墊,3係第-保護膜,4係第二保護膜,5係凸塊(突起電極)。 圖()斤示,半導體基板1上依序形成有:絕緣膜及主 動兀件(均無圖式)、電極塾2、第-保護膜3、及第二保護膜 85071 -12- 1225672 。而此等形成於第一保護膜3之開口部3a、及形成於第二保 =膜4之開口部“内分別形成有凸塊5。凸塊5包含:凸塊本 险。卩5 a與復盖凸塊本體部5 a表面之表面膜5 b。 上述第一保謾膜3及第二保護膜4係保護半導體基板1上 、I主動元件及將一知作為上述電極塾2之配線,避免受 到外力及水分影響者。再者,第一保護膜3及第二保護膜4 為长私極墊2與凸塊5電性連接良好,於凸塊5形成部位被除 去。 丄此時1點在於此等第—保護膜3及第二㈣膜4係形成 位於下層之第一保護膜3之開口部3&大於位於上層之第二保 護膜4之開口部4a所形成之突出構造,凸塊5底部,詳細而言 係底部之外周部係以進入第二保護膜4之下的方式形成。 =1(b)顯示自上面側觀察圖1(a)時之形成於第一保護膜) 及第二保護膜4之各開口部3a,4a、凸塊5及電極墊2之位置 關係。 採用此種構造,與電解電鍍處理比較,即使以設備投資 費用少’且製造成本亦低之非電解電鍍處理形成凸塊5,仍 可以下層之第一保護膜3之大的開口部3a,在凸塊5與電極墊 2,間確保充分的密著面積,可•是高凸塊5與電極墊2之密著 強度。再者,由於上層之第二保護膜4的開口部^小,因此 可抑制凸塊5之上部寬度,提高凸塊5之高度。 亦P凸塊5與私極墊2之密著強度係依凸塊5與電極墊2 之益著面%而定,密著面積小則密著強度亦小。但是,由 於形成於電極墊2上之保護膜至少有兩層,以下層之第一保 85071 -13- 1225672 二騰3之開口那3 a與上® 土楚-过沒尬 功能,因此可消除,門Γ 7 之開口部4a來分離 5與電極墊2之4:: 口部3讀為求增力心塊 ^面知而徹底擴大形成,以阻止密著強度 使卜夕’上_層《第二保護膜4之開口部4a形成較有,即 成:::塊5之高度,凸塊5之寬度仍不致擴大。藉此可形 :見度小且具有高度之凸塊5,因此可對應於微間距化 及夕端子化。 而為求發揮此種功能,第一保護膜3之開口心,亦包各 電極墊2,間距不同# ’只須形成在電極墊2之尺寸以下, 且大於第二保護膜4之開口部“的尺寸即可。再者,宜以凸 塊5之密著強度大於〇·1Ν之方式形成開口部。此因影響雖 依安裝形態及電極墊而改變,但是凸塊之密著強度在UN 以下時,發生凸塊剝離等問題的機率大。 另外,所謂密著強度’係指在凸塊上施加機械性壓力時 之斷裂強度,此處係使用剪切強度作為密著強度。剪切強 度之測定係使用凸塊剪切測試器進行,於凸塊之側面設置 與凸塊同寬之工具,自凸塊之侧面側,在凸塊上施加負荷 ,來測定凸塊斷裂時之負荷。 ' 此外,將第 之尺寸以下, 剥落等。 一保護膜3之開口部3a的大小設定在電極墊2 係因凸塊5可能自電極墊2擠出而引起電極墊2 此外,第二保護膜4之開口部4a之開口寬,兼顧電極墊2 之間距與必要之凸塊5高度,以避免凸塊5.5間之空間小於 5 v m之方式來決定即可。此時,以避免凸塊5.5間之空間小 85071 -14 - 凸:广式來決定開口寬,係因以非電解電鍵反應形成 境::·,凸塊間之空間若小於一’因相互作用,形成凸 塊本體邵之金屬於凸塊間析出,等致各凸塊連接。 上迷凸塊5之形成凸塊本體部h之材質,可使用如錄、鋼 、^金、錫或包含此等之化合物等。此外,形成表面膜 炚材質,可使用如金、鈀、或錫等。 —此外,上層之第二保護膜4可使用如氮化矽膜,下層之第 保硬膜3可使用如氧化矽膜。 而後’以乾式餘刻形成第二保護膜4之開口部^後,以濕 式餘刻形成下層之第一保確 、 、 叹膜3 <開口邵3 a,可輕易地形成 大出構造。 (實施例) 以下,列舉實施例具體說明本發明。 (第一種實施例) 圖2顯示本實施例之半導雕 、 干’岐I置 < 連接端子部分的構造 。其基本構造與實施形能中、 心中說明惑圖1之連接端子部分的構 k相同。亦即,在丰壤;ι ’ 基板1上依序形成有:絕緣膜及支 動元件(均無圖式)、電極孰9 ^ 土 2、弟一保謾膜3、及第二保護月莫 4。形成於電極墊2上之第_仅> &, 一 弟保謾膜3之3 a、及形成於第一保 護膜3上之第二保護膜*夕鬥 、 二 吳開口邵4a内形成有包含凸塊本體 邯5a與表面膜5b之凸塊5。
本實施例將上述第—仅> A
保瘦膜3之開口部3a設為25 a m X 70 V m,將第二保護膜4之鬥〇、, 段4〈開口邵4a設為15// mX 60“ m。此 外’就凸塊5,係以高;#, 门及為10// m之磷化鎳層(磷含量為 85071 -15- 1225672 7〜11%)形成凸塊本體部5a,以厚度為1 # m之金層形成表面 膜5b。因此,凸塊5之全高為11 // m。此外,電極塾2.2間之 間距為50 // m,凸塊5.5間之間距PB亦為50 // m。而包含磷化 鎳層之凸塊本體部5a與包含金層之表面膜5b係藉由非電解 電鐘方式形成。 上述構造因第二保護膜4之開口部4a之寬度尺寸為I5am ,因此凸塊5之高度HB為11/zm時,凸塊寬度WB則為37//m ’凸塊5 ·5間空間Sb標準上可確保1 3 // m。此外,凸塊5與電 極墊2之密著強度,自第一保護膜3之開口部3&的尺寸(密著 面積)求,可確保約0.137N(14g)。 其次,使用圖3、圖4,說明一種電極墊2及凸塊5之形成 方法。圖3 (a)〜(d)及圖4(a)〜(d)係在電極墊2上以非電解鎳電 鍍形成鎳凸塊5之步驟剖面圖。 圖3(a)〜(d)及圖4(a)〜(d)中,1表示半導體基板,2表示電極 塾’ 3表示第一保護膜,4表示第二保護膜,5表示凸塊,5a 表示包含磷化鎳層之凸塊本體部,5b表示包含金層之表面 膜,7表示光阻,8表示鋅層。 首先,如圖3(a)所示,在形成第一保護膜3與第二保護膜4 之半導體基板1上塗敷光阻7,以第二保護膜4之開口部4&的 尺寸在光阻7上開口。 此時,使用氧化矽膜作為第一保護膜3,使用氮化秒膜作 為第二保護膜4。此外,第一保護膜3亦可使用聚醯亞胺膜 等有機膜,第二保護膜4亦可使用無機膜。此外,第一保護 膜3亦可使用無機膜(氧化矽、psG(摻雜磷之氧化矽)等),第 85071 -16· 1225672 —保謾膜4亦可使用聚醯亞胺膜等有機膜。 /、/入,如圖3(b)所示,蝕刻除去開口部分之第二保護膜4 形成開口 # 4a。第二保護膜4之餘刻除去,係使用氣系氣 體(四氟化碳、六氟化硫等)進行乾式蝕刻。 另外,在第二保護膜4上使用無機膜時亦與氮化矽膜同樣 地’可使用系氣體進行乾式餘亥j。另夕卜,第二保護膜4使 :聚酸亞胺膜等有機膜時,係使用氬氣進行乾式姓刻,或 疋使用感光性之聚酿亞胺及有機物,經曝光、顯像後,除 去不需要部分之聚醯亞胺膜及有機膜。 其次,如圖3(c)所示,蝕刻除去光阻7之開口部分之第一 保護膜3。第一保護膜3之蝕刻除去,係使用氟化銨及氟化 铵氟化虱混合溶液等進行濕式钱刻。
濕式蝕刻時’因係進行等方性蝕刻,所以第二保護膜4之 下部之第一保護膜3亦被蝕刻。導致下層之第一保護膜3之 開口部3a大於上層之第二保護膜4之開口部乜,可形成上層 之第二保護膜4突出的構造。 H 另外’於形成上層之第二保護膜4突出之構造時,亦可濕 式蝕刻構成第一保護膜3及第二保護膜4兩者。 其次’剝離光阻7後,如圖3⑷所示,藉由將半導體基板ι 浸潰於硫酸、磷酸或氫氧化鈉等水溶液中,蝕刻除去形成 於電極塾2表面上之銘氧化膜及域化物。另外,銘氣^物 係於㈣第-保護膜3步驟中所形成者。此外,銘氧化膜除 該步驟之外,亦藉由其他步驟中之熱及空氣中之氧而形成 者。 85071 -17- 1225672 水洗後,如圖4(a)所示,使防止電極墊2表面再氧化,且 發揮典電解鎳電鍍之反應起點功能之鋅層8在電極墊2上析 出。 鋅層8係將除去鋁氧化膜及鋁氟化物之半導體基板丨浸潰 於以氧化鋅與氫氧化鈉為主要成分之鋅酸鹽溶液中,替換 私極塾2表面之鋁與溶液中之鋅而形成。 鋅替換後,將半導體基板丨浸潰於約5〜3〇%之硝酸水溶液 中除去鋅,經水洗後,再度藉由浸潰於鋅酸鹽溶液中:形 成比最初替換之鋅更緻密之鋅層,因此亦可使用兩次此種 鋅酸鹽法。 水洗後,如圖4⑻所示,在電極塾2上形成鱗化錄層來構 成凸塊本體部5a。該磷化鎳層係藉由將形成鋅層8之半導體 基板1浸潰於以硫酸鎳與次亞磷酸納為主要成分之非 鎳電鍍液中而形成。 ^ 册平導體基板1浸潰 •一 μ〜1叮,百无開始杳 換反應’繼續藉由經替換之鎳成為觸媒之自觸弟 反應’而進行非電解鎳電鍍反應。 水洗後’如圖4⑷所示,在包含磷化鎳層之凸塊本體部5 ^成金層來構成凸塊5之表面_。金層係藉由將形成劣 弘解鎳電鍍《半導體基板i浸潰於以亞硫 分之替換金電鍍液中而形成。 内為王要居 將半導體基板i浸料替換金電鍍液中時,開始鎳與金々 曰換反應,於鎳表面被金覆蓋時停止替換反應。實際上, 鎳表面很少全部被金覆蓋,鎳自金之針孔持續溶解二 85071 -18-
LZZDO/Z 如此形成之金層5b之厚 電鍍時間以1 〇分鐘〜3〇分鐘為宜 度為 0.05〜0.25 // m。 水洗後,如圖4(d)所示,辦^ # a _ 、 曰 已ϋ磷化鎳層之凸塊本體部 a上之包含金層之表面膜外的隨戸 〇 衣回膜〇的腠厗。金層厚膜化係藉由將替 換至笔鍛完成之半導體基板1 、 子L丞扳1 π /貝於以亞硫酸金鈉與還原 劑為主要成分之非電解金電鍍液中來進行。 以上’在電極塾2上藉由非電解雷拉# 、、 相uv开私醉私鍍形成鎳/金凸塊的步騾 完成。 間距50/zm,凸塊5之高度為 凸塊5.5間之空間為13 “ m 裂模式時鋁(電極墊2)之凝 所形成之凸塊5對於電極墊2之 11 /z m(鎳:lo^m,金: ,凸塊剪切強度為〇.35N/凸塊(斷 聚破壞),可形成所需之凸塊5。 、而本貫施例之半導體裝置如圖5所示,係以接合部 γ共晶接合電鍍於輸送膠帶(丁cp)之内部引線9之鋅層與 釦凸塊5上 < 表面膜5b之金層,並藉由樹脂封裝可搭載於 TCP 上。 ' 搭載於TCP上〈本半導體裝置即使在可靠性評估中,仍可 獲得溫度循環試驗(試驗條件:一40t〜125°c,汽相、各溫 度30刀1里)時為1000猶環,壓力鍋試驗(試驗條件:110。〇, 85RH)時為清洗3〇〇小時之高品質者。 此外本貫知例之半導體裝置,即使經由異方性導電膜 及/、方丨生導私糊膠安裝在形成於玻璃基板上之配線焊塾上 及印刷基板之配線焊墊上,亦不致發生任何問題。 (第一種比較例) 85071 -19- 1225672 如圖6所示,除將第二保護膜4之開口部耗形成與第一保護 膜3之開口部3&相同之25#!1^70//111之大小外,與第一種實 施例之半導體裝置之連接端子的構造完全相同,製造程序 亦完全相同地在半導體裝置上形成連接端子,作為第一種 實施例之第一種比較例。 ' 、該第-種比較例之連接端子之構造,凸塊12與電極塾之 密著強度,與第-種實施例相同,可確#G 35n,但是凸塊 12·12間空間,標準上僅可確保3#m。 ▲ 如前所述,以非電解電鍍反應形成凸塊時,凸塊間空間 若在―以下’則因相互作用,在凸塊間?丨起形成罐 體部(金屬’如鎳、銅、麵、金、錫或包含此等之化合物 的析出。導致各凸塊連接而發生凸塊間短路。 (第二種比較例) 如圖7所示’除將第一保護膜3之開口部3a形成與第二保護 膜4之開口部4a相同之15"mX6〇"m之大小外,與第一種^ 施例之半導體裝置之連接端子的構造完全相同,製造程序 亦完全相同地在何體裝置上形成連接端子,料第—種 實施例之第二種比較例。 該第二種比較例之連接端予之構造,凸塊a·之空間 ’與種實施例相同,可確保13_,但是凸塊η與電二 塾之密著強度僅可確保0 07N。 凸塊之密著強度在〇,1N以下時,影響雖依安裝形態及電 極墊而改變,但是發生凸塊剝落等問題的機率大。 如以上所述’本發明之連接端子係包含:電極塾,其係 85071 -20- 1225672 在表面形成有層狀之數個保護膜;及突起電極,其係形成 於該電極墊上之保護膜之開口部;下層保護膜之開口部形 成大於上層保護膜之開口部,上述突起電極之底部進入^ 層之保護膜之下者。‘ 本發明之連接端子進一步可使用鎳、銅、鈀、金、錫或 包含此等之化合物之任何一種作為上述突起電極。 $ 尤其因鎳及銅價廉,因此可有效删減形成有連接端子之 元件的成本。 本發明之連接端子進1步可將突起電極表面形成包含金 、免、錫之任何一種之構造。 藉由將突起電極表面形成包含金或錫之任何一種之構造 ,可在與接合該突起電極之另一方電極之間共晶接合。^ 此外,藉由形成包含金或鈀之任何一種之構造,可在盥 該突起電極接合之另一方電極之間藉由焊劑進行接合。〃 本發明之連接端子進-步如可將上層保護膜形成口包含& 化矽膜,將下層保護膜形成包含氧化矽膜之構造。 人 藉由以氮切膜形成上層保護膜,以氧切膜形成下層 保護膜,可對上廣保護膜以乾式蝕刻形成開口部,對下^ 保護膜以等方性進行#刻之濕式餘刻形成開口冑。因^ 輕易地加工成上層保護膜突出之構造。 此外,本發明之上述連接端子宜形成下層㈣膜之開口 部與電極墊相同尺寸或比其小之構造。 由:下層保護膜之開口部係決定突起電極之底部與電梓 整之密著面積’且攸關密著強度,因此宜儘可能較寬。但 85071 -21 - 1225672 是,下層保護膜之開口部超過電極墊尺寸而形成時,突起 電極可能自電極墊擠出,而引起電極墊之剥落等,因此下 層保護膜之開口部宜以在電極墊之尺寸内可確保密著強度 之方式設定。 本發明之連接端子之上述下層保護膜之開口部亦可形成 具有上述突起電極之密著強度大於1N之開口寬。 下層保護膜之開口部以上述開口寬形成時,不易發生凸 塊剝落等問題,可製造品質高之連接端子。 本發明之連接端子進<步可形成數個上述突起電極,上 述上層保護膜之開口部形成具有相鄰突起電極間在5 V m以 上之開口寬。 +上層保護膜之開口部為上述之開口寬時,即使以非電解 電鍍法形成突起電極,仍可防止形成凸塊本體部之金屬在 凸塊間析出,導致各凸塊連接。 此外,本發明之連接端子亦可包含:電極墊,Α係於表 :形成有層狀之數個保護膜;及突起電極,其係形成於該 =塾上之保護膜之開口部;以上層保護膜對下層保護膜 二方式,在此等保護膜上形成開口部,以爽著該突出 4刀<方式形成有上述突起電極。 藉由形成上述構造,即使以非電解泰 ,〜, % %屯鐘法形成突起電極 犬起電極之底邵的一部分進入突 卞以十— 大出 <上層保護膜之下, 並以夾耆該突出部分之方式形成。 哈打教、——、 W此可提高突起電極與 兒a 土 <岔著強度。此外,由於突 3,,., 大起电極又上部超過突出 义上層保謾膜後開始撗方向生長, Ώ此可抑制突起電極寬 85071 -22- 度而提高高度。因而可對應於微間距化及多端子化。 此外,本發明亦可採用如下之構造。 亦即纟發明〈連接端子亦可採用於電極塾上之 數個保護膜之開口部 闹口 4,形成哭起電極之連接端子中, 保護膜開口部大於卜JB &淡泌 曰 、㈢保&膜開口部,突起電極之底部Μ 入保謾膜開口部之上層之下的構造。 、此外纟务明〈半導體裝置亦可採用於電極塾上之 之數個保護膜之開口部,形办 曰 一 ^ 形成大起電極之連接端子中,下 層保護膜開口部大於卜爲&、盆 I大&上層保謾膜開口部,突起電極之 進入保護膜開口部之上層之下的構造。 … 此種連接响子、半導體裝置之構造,其保護膜在兩 上,並以上層保十雈臌閱口 p 4 t 曰乂 、 、 叹膜開口尺寸小於下層保護膜開口尺寸之 方式構成電極塾之保罐险關 怵卩又膜開口部。因而可防止以非電解啦 鍍形成凸塊時之溆接几祕μ t ^ 、—κ鄰接凸塊間的μ路’並且可確保凸塊與泰 極塾之密著面積。此外 包 度降低。 *耆& 發明說明項中提及夕1麵昝% 、 及爻/、m貫她形態或實施例僅在說明太 發明心技街内容,不應狹義解釋成僅限定於此種具髀例, 只要符合本發明之精神及在以下申請專利範圍内
種變更來實施。 Q 【圖式簡單說明】 圖1 (a)係顯示本發明一種實 、 、 禋貝她形悲者.,其係半導體裝置 連接端子邵分之縱剖面圖。 圖1 (b)係顯示圖1 ( 本壤魯曲 口 牛等岐裝置<連接端子部分之各保 85071 -23 - 1隻膜之開口部、凸塊及電極墊之尺寸關係圖。 圖2係本發明一種實施例之半導體裝置之連接端子部分 的縱剖面圖。 圖3(a)係顯tf本發明一種實施例之半導體裝置之凸塊製 ^步驟用之連接端子部分的縱剖面圖。 圖3(b)係顯示本發明一種實施例之半導體裝置之凸塊製 ^步驟用之連接端子部分的縱剖面圖。 圖3(C)係顯TF本發明一種實施例之半導體裝置之凸塊製 造步驟用之連接端子部分的縱剖面圖。 圖3(d)係顯7F本發明一種實施例之半導體裝置之凸塊製 造步驟用之連接端子部分的縱剖面圖。 圖4(a)係顯7F本發明一種實施例之半導體裝置之凸塊製 造步驟用之連接端子部分的縱剖面圖。並顯示圖3(a)〜⑷之 後續的製造步騾。 圖4(b)係顯π本發明一種實施例之半導體裝置之凸塊製 造步騾用之連接端子部分的縱剖面圖。 圖4(c)係顯示本發 造步騾用之連接端子 圖4 (d)係顯示本發 造步騾用之連接端子 明一種實施例之半導體裝置之凸塊製 部分的縱剖面圖。 明一種實施例之半導體裝置之凸塊製 部分的縱剖面圖。 施例之半導體裝置之連接端 裝體時之接合部分的縱剖面 圖5係顯示將本發明一種實 子之凸塊安裝於輸送膠帶封 圖。
6係本發明第一 種比車父例之半導體裝置之連接端子部 85071 -24- 1225672 分之縱剖面圖。 圖7係本發明第二種比較例之半導體裝置之連接端子部 分之縱剖面圖。 【圖式代表符號說明】 1 半導體基板 2 電極墊 3 第一保護膜(下層保護膜) 3 a 第一保護膜之開口部 4 第二保護膜(上脣保護膜) 4a 第二保護膜之開口部 5 凸塊(突起電極) 5 a 凸塊本體部 5b 表面膜 7 光阻 8 鋅層 9 内部引線 10 接合部 12 凸塊 13 凸塊 85071 -25 -
Claims (1)
1225672 拾、申請專利範園: !•-種連接端予’其特徵為包含:電極蟄,其係在表面形 成有層狀之數個保護膜;及突起電極,其係形成於該電 極墊上之保護膜的開口部;形成下層之保護膜之開口部 大於上層<保護膜之開口部,上述突起電極之底部進入 上層保護膜之下。 2·如申請專利範圍第i項之連接端子,其中上述突起電極 包含鎳、H金、錫或包含此等之化合物之任何一 種。 3·如申請專利範圍第i項之連接端子,其中上述突起電極 之表面包含金、鈀、錫之任何一種。 4. 如申請專利範圍第1項之連接端子,其中上述上層保護 膜包含氮化矽膜,上述下層保護膜包含氧化矽膜。又 5. 如申請專利範圍第丨項之連接端子,其中上述下層保護 膜之開口部與上述電極墊相同尺寸或比其小。 申叫專利範圍弟1項之連接端子,其中上述下層保護 膜之開口邵形成具有上述突起電極之密著強度大於 0.1N之開口寬。 戈申明專利範圍第1項之連接端子,其中上述突起電極 形成數個,上述上層保護膜之開口部形成具有相鄰之突 起電極間為5 # m以上之開口寬。 、種連接端子,其特徵為包含:電極墊,其係於表面形 成有層狀之數個保護膜;及突起電極,其係形成於該電 極墊上之保謾膜之開口邵;以上層保護膜對下層保護膜 85071 9·1225672 一種連接端子之製造方 、万凌其特徵為孩連接端子包含: :極塾,其㈣表面形成有層狀之數個保護膜;及突起 %極’其係形成於該電極塾上之保護膜之開口部;形成 下層保護膜之開口部大於上層保護膜之開口部,上述突 起電極之底部進人上層保護膜之下;該製造方法係以乾
式触刻形成上述上層保護膜之開口部後,以濕式餘刻形 成上述下層保護膜之.開口部,並藉由非電解電鍍法形成 上述突起電極。 1〇· y種連接端子之製造方法,其特徵為於表面形成有層狀 〈數個保護膜之電極塾上之保護膜的開口部,藉由非電 解電鍍法形成突起電極,並以上層保護膜對下層保護: 突出之方式形成開口部。
11. 一種半導體裝置,其特徵為具備連接端子,該連接端子 包含:電極墊,其係於表面形成有層狀之數個保護膜; 及突起電極,其係形成於該電極墊上之保護膜之開口部 ,形成下層保護膜之開口部大於上層保護膜之開口部, 上述突起電極之底部進入上層保護膜之下。 12. —種半導體裝置之製造方法,其特徵為該半導體裝置具 備連接端子,該連接端子包含··電極墊,其係於表面形 成有層狀之數個保護膜;及突起電極,其係形成於該電 極墊上之保?隻膜之開口邵;形成下層保護膜之開口部大 於上層保護膜之開口部,上述突起電極之底部進入上層 85071 1225672 保護膜之下;該製裨+、+ μ 護膜之開口部後,…以乾式蚀刻形成上述上層保 13. 口部,並藉由非電解:;法:::上述τ層保護腹之開 鮮包鍍法形成上述突起電極。。 一種半導體裝置之製 甘灶观、、 。 法,,、特被為於表面形成有声 狀之數個保護膜凌兩打 曰 昊 < 私極墊上 < 保護膜的開口部,藉由非 私解電鍍法形成突起電極來製作連接端子,製作連接端 子時’以上層保護膜對下層保護膜突出之 保護膜上形成開口部。 、 85071
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JP2002127573A JP3949505B2 (ja) | 2002-04-26 | 2002-04-26 | 接続端子及びその製造方法並びに半導体装置及びその製造方法 |
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JP (1) | JP3949505B2 (zh) |
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KR100601493B1 (ko) * | 2004-12-30 | 2006-07-18 | 삼성전기주식회사 | 하프에칭된 본딩 패드 및 절단된 도금 라인을 구비한bga 패키지 및 그 제조 방법 |
JP2006330021A (ja) * | 2005-05-23 | 2006-12-07 | Mitsubishi Electric Corp | 液晶表示装置 |
JP5165190B2 (ja) * | 2005-06-15 | 2013-03-21 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP4061506B2 (ja) * | 2005-06-21 | 2008-03-19 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100699892B1 (ko) * | 2006-01-20 | 2007-03-28 | 삼성전자주식회사 | 솔더접합신뢰도 개선을 위한 락킹 구조를 갖는 반도체 소자및 인쇄회로기판 |
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US20030203661A1 (en) | 2003-10-30 |
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TW200404344A (en) | 2004-03-16 |
CN1283002C (zh) | 2006-11-01 |
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