TW201604994A - 具有晶圓級底部塡料之晶圓的隱形切割 - Google Patents
具有晶圓級底部塡料之晶圓的隱形切割 Download PDFInfo
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- TW201604994A TW201604994A TW104118366A TW104118366A TW201604994A TW 201604994 A TW201604994 A TW 201604994A TW 104118366 A TW104118366 A TW 104118366A TW 104118366 A TW104118366 A TW 104118366A TW 201604994 A TW201604994 A TW 201604994A
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- wafer
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Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
本發明描述切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。在一實例中,切割晶圓之方法涉及提供前側上具有積體電路且積體電路上安置有晶圓級底部填料材料層之半導體晶圓。該方法亦涉及自半導體晶圓之背側雷射輻射半導體晶圓以沿半導體晶圓之切割劃道產生缺陷,該等切割劃道經定向處於積體電路之間。方法亦涉及在雷射輻射後沿切割劃道機械切單積體電路。
Description
本發明之實施例係關於半導體處理領域,且更特定言之,係關於切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。
在半導體晶圓處理中,在由矽或其他半導體材料所構成的晶圓(亦稱為基板)上形成積體電路。大體而言,利用各種材料層形成積體電路,該等材料為半導體、導體或者絕緣體。使用各種熟知製程摻雜、沉積及蝕刻該等材料以形成積體電路。每一晶圓經處理形成眾多含有被稱為晶粒之積體電路的個別區域。
在積體電路形成製程之後,「切割」晶圓以使個別晶粒彼此分離以便封裝或以未封裝形式用於較大電路內。用於晶圓切割的兩種主要技術為劃線及鋸切。在使用劃線情況中,沿預形成之劃割線跨越晶圓表面移動金剛石鑲頭劃線器。該等劃割線沿晶粒之間的空間延伸。該等空間通常被稱為「劃道(streets)」。金剛石劃線器沿劃道在晶圓表面中形成淺劃痕。在諸如利用滾軸施加壓力後,沿劃割線分離晶圓。晶圓的斷裂遵循晶圓基板之晶格結構。劃線
可用於約10密耳(千分之一吋)或更小厚度的晶圓。對於較厚晶圓,鋸切係目前較佳之切割方法。
在使用鋸切情況中,以高速每分鐘轉數旋轉的金剛石鑲頭鋸接觸晶圓表面,並沿劃道鋸切晶圓。將晶圓安裝在支撐構件上,該支撐構件為諸如跨越薄膜框拉伸的黏合薄膜,並將鋸反復應用於垂直與水平劃道兩者。劃線或鋸切的一個問題在於可沿晶粒之斷裂邊緣形成卷屑及槽。另外,可形成裂紋,且該等裂紋可自晶粒邊緣傳播至基板內,並導致積體電路損壞。卷屑及開裂尤其是劃線所具有的問題,因為僅可對正方形或矩形晶粒之一側按結晶結構之<110>方向劃線。因此,晶粒之另一側之斷裂產生鋸齒狀分離線。由於卷屑及開裂,晶圓上的晶粒之間需要額外間距,以防止損傷積體電路(例如,使卷屑及裂紋與實際積體電路保持一定距離)。由於間隔要求,所以在標準尺寸之晶圓上形成的晶粒不多,且浪費了本可用於電路系統之晶圓使用面積。使用鋸加劇了半導體晶圓上的使用面積浪費。鋸刃之厚度約為15微米。因此,為確保由鋸產生的切口周圍之開裂及其他損傷不損害積體電路,通常必須將每一晶粒之電路系統分離三百至五百微米。此外,在切割後,需要大量清潔每一晶粒以移除產生自鋸切製程的顆粒及其他污染物。
亦已經使用電漿切割,但電漿切割亦可具有限制。舉例而言,妨礙電漿切割實施的一個限制
可為成本。用於圖案化抗蝕劑的標準微影術操作可導致實施成本過高。可能妨礙電漿切割實施的另一限制在於在沿劃道切割常見金屬(例如,銅)時,對該等常見金屬之電漿處理可產生生產問題或產量限制。
本發明之實施例包括切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。
在一實施例中,切割晶圓之方法涉及提供前側上具有積體電路且積體電路上安置有晶圓級底部填料材料層之半導體晶圓。該方法亦涉及自半導體晶圓之背側雷射輻射半導體晶圓以沿半導體晶圓之切割劃道產生缺陷,該等切割劃道經定向處於積體電路之間。方法亦涉及在雷射輻射後沿切割劃道機械切單積體電路。
在另一實施例中,切割晶圓之方法涉及提供前側上具有積體電路且積體電路上安置有晶圓級底部填料材料層之矽晶圓。方法亦涉及在基板載體之切割膠帶上安裝矽晶圓之背側。該方法亦涉及自背側穿過切割膠帶雷射輻射矽晶圓以沿矽晶圓之切割劃道產生缺陷,該等切割劃道經定向處於積體電路之間。方法亦涉及在雷射輻射後沿切割劃道機械切單積體電路。
在另一實施例中,切割晶圓之方法涉及提供前側上具有積體電路且積體電路上安置有晶圓
級底部填料材料層之矽晶圓。該方法亦涉及經由晶圓級底部填料材料層在基板載體之切割膠帶上安裝矽晶圓。該方法亦涉及自矽晶圓之背側雷射輻射矽晶圓以沿矽晶圓之切割劃道產生缺陷,該等切割劃道經定向處於積體電路之間。方法亦涉及在雷射輻射後沿切割劃道機械切單積體電路。
120‧‧‧邏輯晶粒/記憶體晶粒混合3D堆疊結構
122‧‧‧第一記憶體晶粒
124‧‧‧第二記憶體晶粒
126‧‧‧邏輯晶粒
128‧‧‧封裝基板
130‧‧‧背側凸塊
132‧‧‧透矽通孔
199‧‧‧底部填料材料
200A‧‧‧基板載體
200B‧‧‧基板載體
202A‧‧‧切割膠帶
202B‧‧‧切割膠帶
204A‧‧‧金屬框架
204B‧‧‧金屬框架
206A‧‧‧晶圓
206B‧‧‧晶圓
208A‧‧‧基板
208B‧‧‧基板
210A‧‧‧裝置層
210B‧‧‧裝置層
212A‧‧‧WLUF材料層
212B‧‧‧WLUF材料層
300‧‧‧基板載體
302‧‧‧襯帶
304‧‧‧膠帶環/框架
306‧‧‧晶圓/基板
400‧‧‧雷射輻射
402‧‧‧雷射誘導缺陷
404‧‧‧拉伸應力
408‧‧‧晶粒
450‧‧‧雷射輻射
452‧‧‧雷射誘導缺陷
453‧‧‧切割道
454‧‧‧拉伸應力
456‧‧‧裂紋
458‧‧‧晶粒
500‧‧‧基板載體
502‧‧‧雷射誘導缺陷
504‧‧‧拉伸應力
506‧‧‧裂紋
508‧‧‧晶粒
550‧‧‧雷射輻射
552‧‧‧雷射誘導缺陷
553‧‧‧切割道
554‧‧‧拉伸應力
556‧‧‧裂紋
558‧‧‧晶粒
600‧‧‧電腦系統
602‧‧‧處理器
604‧‧‧主記憶體
606‧‧‧靜態記憶體
608‧‧‧網路介面裝置
610‧‧‧視訊顯示單元
612‧‧‧文數字輸入裝置
614‧‧‧游標控制裝置
616‧‧‧訊號產生裝置
618‧‧‧二級記憶體
620‧‧‧網路
622‧‧‧軟體
626‧‧‧處理邏輯
630‧‧‧匯流排
632‧‧‧機器可存取儲存媒體
第1圖圖示根據本發明之實施例的經耦接至封裝基板的晶粒堆疊之橫截面視圖。
第2A圖圖示根據本發明之實施例的在裝置側朝上排列中支撐具有晶圓級底部填料材料的晶圓之基板載體之橫截面視圖。
第2B圖圖示根據本發明之實施例的在裝置側朝下排列中支撐具有晶圓級底部填料材料的晶圓之基板載體之橫截面視圖。
第3圖圖示根據本發明之實施例的適合於在切單製程期間支撐晶圓之基板載體之平面圖。
第4圖圖示根據本發明之實施例的用於第2A圖之組件的兩種不同隱形切割方法之處理中的各個階段之橫截面視圖。
第5圖圖示根據本發明之實施例的用於第2B圖之組件的兩種不同隱形切割方法之處理中的各個階段之橫截面視圖。
第6圖圖示根據本發明之實施例的示例性電腦系統之方塊圖。
本發明描述切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。在以下描述中,闡述眾多特定細節,諸如隱形切割方法及材料範圍,以便提供本發明之實施例之透徹理解。對熟習此項技術者將顯而易見的是,可在無該等特定細節的情況下實施本發明之實施例。在其他情形中,並未詳細描述諸如積體電路製造之熟知的態樣,以免不必要地模糊本發明之實施例。此外,應理解,圖式中所示之各個實施例為說明性表示,且不一定按比例繪製。
可實施涉及雷射輻射及後續機械分離之隱形晶圓或基板切割製程用於晶粒切單。雷射輻射製程用於沿切割道在晶圓或基板中產生雷射誘導缺陷。在雷射誘導缺陷輔助下,基於施加拉伸應力之機械分離可隨後用於沿切割道***晶圓或基板。在一實施例中,包括晶圓級底部填料材料的晶圓經歷此隱形切割製程。在一個此類實施例中,首先藉由雷射劃線製程在切割道中對晶圓劃線。雷射劃線製程可用於清潔地移除晶圓級底部填料材料及/或存在於切割道中的裝置層。
本文所描述之一或更多個實施例係針對內部包括有晶圓級底部填料材料的晶圓之隱形切
割。一些實施例係針對半導體晶圓上的晶粒之切單或切割,為裝置封裝作準備。更特定言之,特定實施例可關於包括有晶圓級底部填料的薄晶圓之晶粒切單,用於三維(3D)堆疊/封裝應用。
為提供情境,作為裝置封裝製程的一部分,將已切單晶粒置放至印刷電路板(printed circuit board;PCB)上,且在多個晶粒封裝中於彼此頂部上堆疊。為了耗散晶粒與基板之間的熱機械不匹配,在PCB至晶粒及晶粒至晶粒縫隙中置放「底部填料」材料。當前,將底部填料材料應用於每一個別晶粒堆疊。然而,晶圓級底部填料(wafer-level underfill;WLUF)最近變得經濟上及技術上可行,以替代底部填料材料之習知晶粒級分配。顧名思義,在單次應用(例如,藉由疊層、塗覆或絲網印刷)中將底部填料應用於整個晶圓,且因此在晶粒堆疊之前應用,而非在晶粒堆疊之後應用。然而,到目前為止,尚未採用已證明技術用於具有晶圓級底部填料的晶圓之切割。
應瞭解,本文所描述之製程可用於適應各種3D架構之製造。在一實例中,第1圖圖示根據本發明之實施例經耦接至封裝基板的晶粒堆疊之橫截面視圖。參看第1圖,邏輯晶粒/記憶體晶粒混合3D堆疊結構120包括第一記憶體晶粒122,該第一記憶體晶粒經耦接至第二記憶體晶粒124。將第二記憶體
晶粒124耦接至邏輯晶粒126。將邏輯晶粒126耦接至封裝基板128。如第1圖中所描繪,耦接可由背側凸塊130及透矽通孔(through-silicon-via;TSV)132之使用而實現。亦如第1圖中所描繪,可在最終產品中的基板/晶粒或晶粒/晶粒對之間包括底部填料材料199作為鈍化層。
根據本發明之一實施例,為晶粒切單作準備,將晶圓(通常經薄化,但可為完整厚度)安裝至撓性切割膠帶上,並藉由剛性框架支撐。當使用完整晶圓級底部填料(WLUF)時,在獨立操作系列中應用此層。隨後將具有WLUF的晶圓安裝至切割膠帶上,其中使WLUF向上面朝膠帶或向下面朝膠帶,如下文關聯第2A圖與第2B圖更詳細地描述。隨後切單晶圓。
傳統上已使用機械鋸切割切單晶圓。然而,在實施進階介電材料及封裝技術(需要薄化晶圓)下,已開發了新的切單技術,諸如雷射開槽加鋸切、雷射剝蝕雙翻式(full cut)切割、雷射隱形切割、微影圖案化加電漿切割及雷射剝蝕加電漿切割。概念上,隱形切割(stealth dicing;SD)包括兩個操作。首先,將雷射光束聚焦於晶圓內部以沿切割道之中心軸產生局部化缺陷。接著,在切割膠帶上施加拉伸應力以沿SD層中的局部化缺陷之線(例如,沿隱形切割方向)傳播裂紋來切單晶粒。
在最新開發之WLUF技術下,其中在晶圓切割之前於整個晶圓表面之裝置側上應用底部填料層,習知刀刃切割及/或完整厚度雷射剝蝕切割難以清潔地切割晶圓。然而,根據本文所描述之一或更多個實施例,類似隱形切割的方法用於在已形成WLUF的情況下切單晶圓。又,如下文關聯第2A圖及第2B圖所描述,存在兩種選擇,藉由該等選擇可準備好晶圓進行隱形切割。詳言之,必須取決於WLUF是否面朝上或面朝下抵靠切割膠帶作出考慮。
如下文進一步描述,在一實施例中,在WLUF面朝上或面朝下抵靠切割膠帶之每種選擇中,存在兩種子選擇:(i)並未移除WLUF(及劃道中的裝置層)或(ii)在隱形切割雷射輻射之前,藉由機械鋸切及/或雷射剝蝕僅移除WLUF或將WLUF與劃道中的裝置層一起移除。關於下文所描述之至少一些實施例,若WLUF為不透明,則可移除或應移除WLUF材料。舉例而言,在不透明WLUF材料情況中,在隱形切割期間為沿切割溝槽切割或精確分離WLUF而防止晶圓不對準可變得困難。關於下文所描述之至少一些實施例,可移除或應移除WLUF層下方的裝置層,以便更精確地控制按導引使用雷射劃線切口沿切割方向的隱形切割產生嵌入裂紋之裂紋傳播。當溝槽中存在TSV時,此可特別有用。
下文所描述之第2A圖與第2B圖圖示基板載體(例如,帶框)所支撐之晶圓的兩種可能排列,該晶圓上具有WLUF材料。
在第一實例中,第2A圖圖示根據本發明之實施例的在裝置側朝上排列中支撐具有晶圓級底部填料材料的晶圓之基板載體之橫截面視圖。參看第2A圖,基板載體200A包括金屬框架204A所支撐之切割膠帶202A。晶圓206A包括晶圓基板208A,其中在前側上具有裝置層210A。在裝置層210A上安置WLUF材料層212A。在第2A圖之排列中,相對於基板載體200A定向晶圓206A以使得WLUF層212A面朝上。亦即,WLUF層212A及裝置層210A位於切割膠帶202A上所安置之基板208A上方。
在第二實例中,第2B圖圖示根據本發明之實施例的在裝置側朝下排列中支撐具有晶圓級底部填料材料的晶圓之基板載體之橫截面視圖。參看第2B圖,基板載體200B包括金屬框架204B所支撐之切割膠帶202B。晶圓206B包括晶圓基板208B,其中在前側上具有裝置層210B。在裝置層210B上安置WLUF材料層212B。在第2B圖之排列中,相對於基板載體200B定向晶圓206B以使得WLUF層212B面朝下。亦即,WLUF層212B及裝置層210B位於基板208B下方。在切割膠帶202B上安置WLUF材料層212B。
應瞭解,晶圓基板及基板載體尺寸可隨應用而變化。作為一個此類實例,第3圖圖示根據本發明之實施例的適合於在切單製程期間支撐晶圓之基板載體之平面圖。參看第3圖,基板載體300包括由膠帶環或框架304圍繞之襯帶層302。藉由基板載體500之襯帶302支撐晶圓或基板306。在一個實施例中,藉由晶粒黏著薄膜使晶圓或基板306黏著至襯帶302。在一個實施例中,膠帶環或框架304由不銹鋼構成。
在一實施例中,可在單個系統(例如,群集工具)中或在複數個獨立系統中容納切單製程,該等系統經定尺寸以接收基板載體,諸如基板載體300。在一個此類實施例中,此系統可容納晶圓框架,而不影響系統佔用面積,該系統佔用面積經其他方式定尺寸以容納未被基板載體所支撐之基板或晶圓。在一個實施例中,此處理系統經定尺寸以容納300毫米直徑之晶圓或基板。相同系統可容納約380毫米寬乘以380毫米長的晶圓載體,如第3圖所描繪。然而,應瞭解,系統可經設計以處置200或450毫米晶圓或基板,或更特定言之,基板載體經定尺寸以支撐200或450毫米晶圓或基板。
在一實施例中,半導體晶圓或基板208A、208B或306由一材料構成,該材料適合於經受製造製程,且半導體處理層可適宜地安置在該材
料之上。舉例而言,在一個實施例中,半導體晶圓或基板208A、208B或306由基於IV族之材料構成,該材料諸如但不限於結晶矽、鍺或矽/鍺。在一特定實施例中,提供半導體晶圓或基板208A、208B或306包括提供單晶矽基板。在一特定實施例中,單晶矽基板摻雜有雜質原子。在另一實施例中,半導體晶圓或基板208A、208B或306由III-V族材料構成,諸如例如在發光二極體(light emitting diode;LED)之製造中使用的III-V族材料基板。
在一實施例中,在半導體晶圓或基板208A、208B或306上或中安置有作為所包括之積體電路之一部分的半導體裝置之陣列,亦即,裝置層210A或210B中所製造的半導體裝置之陣列。此類半導體裝置之實例包括但不限於製造在矽基板中且封裝在介電層中的記憶體裝置或互補金屬氧化物半導體(complimentary metal-oxide-semiconductor;CMOS)電晶體。複數個金屬互連可在該等裝置或電晶體上方及在周圍的介電層中形成,並可用於電性耦接該等裝置或電晶體以形成積體電路。組成積體電路之間的劃道或切割道之材料可與用於形成積體電路之彼等材料類似或相同。舉例而言,劃道或切割道可由介電材料層、半導體材料層及金屬化材料層構成。在一個實施
例中,劃道或切割道中的一或更多者包括類似於積體電路之實際裝置之測試裝置。
晶圓級底部填料(WLUF)材料層可由一材料構成,該材料適合於包括在晶片堆疊中的晶片(裝置側)之頂部上,以產生熱短路且亦提供堆疊晶片之間的機械穩定連接。此底部填料應大體上具有(1)非常低的電導率,(2)高熱導率,(3)與晶片塊狀材料(例如,矽)密切匹配之熱膨脹係數,(4)與各個鈍化層及模製化合物的良好黏著性,該等化合物(例如,氮化矽、氧化物、聚醯亞胺)用於晶片之頂部及底部上,及(5)有利流變性質,允許圍繞晶片之裝置側上所發現之柱及凸塊之形態的可成形性而不留下孔隙。底部填料層之適宜市售材料之實例包括:B階段環氧化物,諸如InterviaTM或CycloteneTM,兩者皆由Dow Chemical製造;聚醯亞胺,諸如PimelTM,可購自Asahi KASEI;聚苯并噁唑,諸如SumiresinTM,可購自Sumitomo Bakelite。許多其他材料亦可用。
提供進一步情境,用於應用底部填料層之先前方法已包括:(1)已組裝堆疊之兩個晶片之間的底部填料可固化液體之毛細作用流動;(2)在堆疊之前將「熱熔」材料應用於晶片之頂部或底部,該材料在加熱時流動;及(3)在堆疊之前將乾式疊層應用於成品晶片之頂部。然而,毛細作用流動方法常在平
衡晶片/流動材料介面之所需可濕性與毛細作用施加在薄化且非常精密的晶片之力方面遭到困難。同時,熱熔方法仍處於研究中且尚未被最佳化。習知乾式疊層方法涉及在堆疊之前但在切單之後將乾膜應用於成品晶片之頂部。WLUF材料之使用可克服常見於底部填料材料之後切單應用中的上文所列問題中的至少一些。
相比之下,根據本文所描述之一或更多個實施例,藉由在切割之前將雙層膠帶實體滾動至晶圓表面上實現「晶圓級底部填料」,藉此雙層膠帶之底層圍繞銅凸塊及柱流動且頂層充當載體並被剝離。可在切單製程之前或之後執行顯露製程,在該顯露製程中自頂部例如藉由電漿灰化薄化疊層以顯露凸塊之接觸區域。在其他實施例中,在切單製程之前或之後應用並凹陷單層WLUF材料。
在本文所描述之方法之第一實例中,第4圖圖示根據本發明之實施例的用於第2A圖之組件的兩種不同隱形切割方法之處理中的各個階段之橫截面視圖。大體參看第4圖,在一實施例中,在裝置側朝上排列中提供支撐具有晶圓級底部填料材料的晶圓之基板載體。亦即,提供使晶圓背側安裝在切割膠帶上之晶圓。利用來自切割膠帶側之雷射輻射執行晶圓之隱形切割。在此情況中,實施雷射透明切割膠帶。在隱形切割之後,擴展切割膠帶以在雷射輻射後
分離晶粒。對於下文將更詳細描述之第4圖之路徑1與路徑2兩者,基板至基板載體之起始定向(a)為面朝上,如關聯第2A圖所描述。
第4圖之路徑1表示一種處理方案,其中採用隱形切割雷射輻射,而不移除/圖案化WLUF 212A及/或裝置層210A。參看第4圖之部分(b1),執行雷射輻射400穿過基板載體200A之切割膠帶202A。在晶圓基板208A內部沿切割道產生雷射誘導缺陷402。參看第4圖之部分(c1),沿切割膠帶202A施加拉伸應力404。沿缺陷402的裂紋406傳播切單晶粒。亦即,裂紋406穿過WLUF 212A、裝置層210A及基板208A以提供切單晶粒408。
第4圖之路徑2表示一種處理方案,其中採用隱形切割雷射輻射,首先移除/圖案化WLUF 212A及/或裝置層210A。參看第4圖之部分(b2),沿切割道453移除晶圓級底部填料212A及裝置層210A。如下文將更詳細描述,可藉由刀刃切割或較佳地藉由雷射劃線製程執行此移除或劃線。執行雷射輻射450穿過基板載體200A之切割膠帶202A。在晶圓基板208A內部沿切割道453產生雷射誘導缺陷452。參看第4圖之部分(c2),沿切割膠帶202A施加拉伸應力454。沿缺陷452的裂紋456傳播切單晶粒。亦即,裂紋456穿過基板208A且與劃線切割道453對準以提供切單晶粒458。
因此,根據本發明之一實施例,第4圖圖示用於面朝上地安裝在帶框上的晶圓之製程流程。用於隱形切割之雷射波長不能穿透劃道內的測試元件群組(test element group;TEG)中含有金屬的裝置層。因此,必須如圖所示自背側穿過切割膠帶輻射晶圓。路徑1對應於在隱形切割雷射輻射之前並未移除劃道中的WLUF與TEG/裝置層的情況,且路徑2對應於在隱形切割之前已移除WLUF與TEG/裝置層的情況。對於兩種情況,在隱形切割後施加拉伸應力以便切單晶粒。
在本文所描述之方法之第二實例中,第5圖圖示根據本發明之實施例的用於第2B圖之組件的兩種不同隱形切割方法之處理中的各個階段之橫截面視圖。大體參看第5圖,在一實施例中,在裝置側朝下排列中提供支撐具有晶圓級底部填料材料的晶圓之基板載體。亦即,提供使晶圓之WLUF側安裝在切割膠帶上之晶圓。利用來自晶圓背側之雷射輻射執行晶圓之隱形切割。在隱形切割之後,擴展切割膠帶以在雷射輻射後分離晶粒。對於下文將更詳細描述之第5圖之路徑3與路徑4兩者,基板至基板載體之起始定向(a)為面朝下,如關聯第2B圖所描述。
第5圖之路徑3表示一種處理方案,其中採用隱形切割雷射輻射,而不移除/圖案化WLUF 212B及/或裝置層210B。參看第5圖之部分(b1),
自基板208B之曝露背側上方執行雷射輻射500。在晶圓基板208B內部沿切割道產生雷射誘導缺陷502。參看第5圖之部分(c1),沿切割、膠帶202B施加拉伸應力504。沿缺陷502的裂紋506傳播切單晶粒。亦即,裂紋506穿過WLUF 212B、裝置層210B及基板208B以提供切單晶粒508。
第5圖之路徑4表示一種處理方案,其中採用隱形切割雷射輻射,首先移除/圖案化WLUF 212B及/或裝置層210B。參看第5圖之部分(b2),沿切割道553移除晶圓級底部填料212B及裝置層210B。如下文將更詳細描述,可藉由刀刃切割或較佳地藉由雷射劃線製程執行此移除或劃線。自基板208B之曝露背側上方執行雷射輻射550。在晶圓基板208B內部沿切割道553產生雷射誘導缺陷552。參看第5圖之部分(c2),沿切割膠帶202B施加拉伸應力554。沿缺陷552的裂紋556傳播切單晶粒。亦即,裂紋556穿過基板208B且與劃線切割道553對準以提供切單晶粒558。
因此,根據本發明之一實施例,第5圖圖示用於面朝下地安裝在帶框上的晶圓之製程流程,例如其中在切割膠帶上安裝WLUF材料。對於該等製程流程,隱形切割雷射輻射必須仍來自晶圓之背側。然而,由於WLUF面朝下,輻射來自帶框頂部且不需要通過切割膠帶。在該等方法中,解除隱形切割雷射與
切割膠帶之相互作用上的限制。然而,應瞭解,此處理引入額外製程流程複雜性,原因在於切單後晶粒定向為面朝下。路徑3對應於在隱形切割雷射輻射之前並未移除劃道中的WLUF與TEG/裝置層的情況,且路徑4對應於在隱形切割之前已移除WLUF與TEG/裝置層的情況。對於兩種情況,在隱形切割後施加拉伸應力以便切單晶粒。
在一實施例中,對於關聯第4圖及第5圖所描述之所有處理可能性,在隱形切割雷射輻射後施加拉伸應力以便切單晶粒。此切單可更加清潔,亦即機械刀刃切割或雷射剝蝕切割可各自具有針對包括WLUF材料的晶圓之製造清潔切割問題。此外,電漿切割可不具有成本效益,且通常用於許多類型底部填料材料(包括WLUF)中的填充劑可存在電漿切割方法之額外整合挑戰。因此,根據本發明之一實施例,使用隱形切割提供清潔分解及所得側壁產生。
再次參看第4圖及第5圖,應瞭解,各種各樣的雷射選擇可用於處理方案之隱形切割(SD)部分期間的缺陷產生之雷射輻射。然而,在一個特定實施例中,使用聚焦於基板內部(例如,晶圓之塊狀矽部分的內部)之雷射光束執行缺陷產生之雷射輻射,其中用於提供雷射光束之雷射具有大於約1000奈米的波長及大於或等於約10皮秒的雷射脈衝寬度。
再次參看第4圖及第5圖之路徑2及路徑4,分別藉由雷射劃線製程執行晶圓劃道或切割道中的WLUF層與裝置層之首次移除/圖案化。在一實施例中,利用雷射劃線製程首次移除/圖案化晶圓劃道或切割道中的WLUF層與裝置層包括使用具有飛秒範圍內脈衝寬度的雷射,亦即,使用基於飛秒之雷射劃線製程。特定而言,可使用波長處於可見光譜加紫外線(ultra-violet;UV)及紅外線(infra-red;IR)範圍(總稱為寬頻帶光譜)內的雷射來提供基於飛秒之雷射,亦即脈衝寬度在飛秒(10-15秒)數量級之雷射。在一個實施例中,剝蝕並非或基本上並非依波長而定,且因此,剝蝕適合於複雜薄膜,該等薄膜諸如WLUF之薄膜、裝置層之薄膜,且在可能情況下的下層半導體晶圓或基板的一部分之薄膜。
在一實施例中,儘管此類材料之一般能量吸收特性在某些條件下可區別較大,但可選擇基於飛秒雷射之製程之參數以對WLUF與裝置層具有基本常見剝蝕效果。在一個此類實施例中,使用高強度且短脈衝寬度的基於飛秒之雷射製程。在一特定實施例中,在基於飛秒之雷射輻射製程中使用約小於或等於400飛秒之脈衝以移除晶圓劃道或切割道中的WLUF與裝置層。
相比之下,若在含有WLUF與裝置層的堆疊結構中選擇非最佳雷射參數,則雷射剝蝕製程可
引發分層問題。舉例而言,雷射穿透高帶隙能量介電質而無可量測之吸收。在一實施例中,儘管基於皮秒之雷射輻射製程導致複雜堆疊中的微開裂及分層,但基於飛秒之雷射輻射製程已經證實不會導致相同材料堆疊之微開裂或分層。
根據本發明之一實施例,晶圓劃道或切割道中的WLUF層與裝置層之首次移除/圖案化之適宜基於飛秒之雷射製程之特徵在於高峰值強度(輻射照度),該高峰值強度通常導致各種材料中的非線性相互作用。在一個此類實施例中,飛秒雷射源具有大約處於10飛秒至500飛秒範圍內之脈衝寬度,但較佳的脈衝寬度處於100飛秒至400飛秒範圍內。在一個實施例中,飛秒雷射源具有大約處於1570奈米至200奈米範圍內之波長,但較佳的波長處於540奈米至250奈米範圍內。在一個實施例中,雷射及相應的光學系統在工作表面提供大約處於3微米至15微米範圍內之焦點,但較佳的焦點大約處於5微米至10微米範圍內。
位於工作表面處之空間光束輪廓可為單模(高斯)或具有成型頂帽型輪廓。在一實施例中,雷射源具有大約處於200kHz至10MHz範圍內之脈衝重複率,但較佳的脈衝重複率大約處於500kHz至5MHz範圍內。在一實施例中,雷射源在工作表面處輸送大約處於0.5uJ至100uJ範圍內之脈衝
能,但較佳的脈衝能大約處於1uJ至5uJ範圍內。在一實施例中,晶圓劃道或切割道中的WLUF層與裝置層之首次移除/圖案化之雷射劃線製程以大約處於500毫米/秒至5公尺/秒範圍內之速度沿工作件表面執行,但較佳的速度大約處於600毫米/秒至2公尺/秒範圍內。
可僅以單次執行或以多次執行晶圓劃道,或切割道中的WLUF層與裝置層之首次移除/圖案化之劃線製程,但在一實施例中,較佳為執行1至2次。在一個實施例中,工件中的劃線深度處於約5微米至50微米深的範圍內,較佳地處於10微米至20微米深的範圍內。可按給定脈衝重複率以單脈衝串或脈衝叢發串應用雷射。在一實施例中,所產生之雷射光束切口寬度大約處於2微米至15微米範圍內,但在矽晶圓劃線/切割中較佳的切口寬度大約處於6微米至10微米範圍內,該等切口寬度在裝置/矽介面處測得。
可選擇參數以提供具有精確控制剝蝕寬度(例如,切口寬度)及深度之晶圓劃道或切割道中的WLUF層與裝置層之首次移除/圖案化之有意義的製程產量。如上所述,與基於皮秒及基於奈秒之雷射剝蝕製程相比,基於飛秒之雷射可更適合於提供此等優勢。然而,即使在基於飛秒之雷射剝蝕光譜中,某些波長可提供比其他波長更佳的效能。舉例而言,在一個實施例中,基於飛秒且具有更接近紫外線範圍或
處於紫外線範圍內的波長之雷射製程與基於飛秒且具有更接近紅外線範圍或處於紅外線範圍內的波長之雷射製程相比,提供更清潔的剝蝕製程。在一特定此類實施例中,適合於半導體晶圓或基板劃線的基於飛秒之雷射製程係基於具有約小於或約等於540奈米之波長的雷射。在一特定此類實施例中,使用具有約小於或約等於540奈米之波長之雷射的脈衝,該等脈衝約小於或約等於400飛秒。然而,在一替代實施例中,使用雙雷射波長(例如,紅外線雷射與紫外線雷射之組合)。
本發明之實施例可作為電腦程式產品或軟體而提供,該電腦程式產品或軟體可包括機器可讀取媒體,在該媒體上儲存有指令,該電腦程式產品或軟體可用於程式化電腦系統(或其他電子裝置)以執行根據本發明之實施例之製程。在一個實施例中,電腦系統與用於執行上述製程操作中的一或更多者之製程工具耦接。機器可讀取媒體包括任何以機器(例如,電腦)可讀取的形式儲存或傳輸資訊之機制。舉例而言,機器可讀取(例如,電腦可讀取)媒體包括機器(例如,電腦)可讀取儲存媒體(例如,唯讀記憶體(read only memory;「ROM」)、隨機存取記憶體(random access memory;「RAM」)、磁碟儲存媒體、光儲存媒體、快閃記憶體裝置等)、機器(例如,電腦)可讀取傳輸媒體(電訊號、光訊
號、聲訊號或其他形式之傳播訊號(例如,紅外線訊號、數位訊號等))等。
第6圖圖示電腦系統600之示例性形式之機器的圖解表示,可在該電腦系統中執行指令集以用於引發該機器執行本文所描述之方法中的任何一或更多者。在替代實施例中,可在區域網路(Local Area Network;LAN)、內部網路、外部網路或網際網路中將機器連接(例如,經網路連接)至其他機器。該機器可作為主從式網路環境中的伺服器或客戶端機器操作,或作為同級間(或分散式)網路環境中的同級機器操作。該機器可為個人電腦(personal computer;PC)、平板PC、機上盒(set-top box;STB)、個人數位助理(Personal Digital Assistant;PDA)、蜂巢式電話、網路設備、伺服器、網路路由器、交換機或橋接器,或任何能夠執行指令集(按順序或以其他方式)之機器,該指令集指定將由彼機器所採取的動作。進一步地,儘管僅圖示單個機器,但術語「機器」應亦被視為包括機器(例如,電腦)之任何集合,該等機器個別或共同執行一個指令集(或多個指令集)以執行本文所描述之方法中的任何一或更多者。
示例性電腦系統600包括處理器602、主記憶體604(例如,唯讀記憶體(ROM)、快閃記憶體、諸如同步DRAM(SDRAM)或Rambus
DRAM(RDRAM)之動態隨機存取記憶體(dynamic random access memory;DRAM)等)、靜態記憶體606(例如,快閃記憶體、靜態隨機存取記憶體(static random access memory;SRAM)等)及二級記憶體618(例如,資料儲存裝置),上述各者經由匯流排630與彼此通訊。
處理器602表示一或更多個通用處理裝置,諸如微處理器、中央處理單元或類似者。更特定言之,處理器602可為複雜指令集計算(complex instruction set computing;CISC)微處理器、精簡指令集計算(reduced instruction set computing;RISC)微處理器、超長指令字(very long instruction word;VLIW)微處理器、實施其他指令集的處理器或實施指令集組合的處理器。處理器602亦可為一或更多個專用處理裝置,諸如特殊應用積體電路(application specific integrated circuit;ASIC)、現場可程式化閘陣列(field programmable gate array;FPGA)、數位訊號處理器(digital signal processor;DSP)、網路處理器或類似者。處理器602經配置以執行處理邏輯626,該處理邏輯用於執行本文所描述之操作。
電腦系統600可進一步包括網路介面裝置608。電腦系統600亦可包括視訊顯示單元610(例如,液晶顯示器(liquid crystal display;LCD)、發光二極體顯示器(light emitting diode display;LED)或陰極射線管(cathode ray tube;CRT))、文數字輸入裝置612(例如,鍵盤)、游標控制裝置614(例如,滑鼠)及訊號產生裝置616(例如,揚聲器)。
二級記憶體618可包括機器可存取儲存媒體(或更特定言之,電腦可讀取儲存媒體)632,在該媒體上儲存有一或更多個指令集(例如,軟體622),該等指令集具體實現本文所描述之方法或功能中的任何一或更多者。軟體622亦可完全或至少部分位於主記憶體604內及/或在由電腦系統600執行該軟體期間位於處理器602內,主記憶體604及處理器602亦組成機器可讀取儲存媒體。可經由網路介面裝置608在網路620上進一步傳輸或接收軟體622。
儘管機器可存取儲存媒體632在一示例性實施例中展示為單個媒體,但術語「機器可讀取儲存媒體」應被視為包括儲存一或更多個指令集之單個媒體或多個媒體(例如,集中式或分散式資料庫,及/或關聯的快取記憶體及伺服器)。術語「機器可讀取儲存媒體」亦應被視為包括任何能夠儲存或編碼一指令集之媒體,該指令集由該機器執行,並引發該機
器執行本發明之方法中的任何一或更多者。因此,術語「機器可讀取儲存媒體」應被視為包括但不限定於固態記憶體及光學媒體與磁性媒體。
根據本發明之一實施例,機器可存取儲存媒體上儲存有指令,該等指令引發資料處理系統執行在晶圓廠或其他製造環境中切割晶圓或基板之上述方法或上述方法中的一部分。
因此,本發明已揭示切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。
200A‧‧‧基板載體
202A‧‧‧切割膠帶
204A‧‧‧金屬框架
206A‧‧‧晶圓
208A‧‧‧基板
210A‧‧‧裝置層
212A‧‧‧WLUF材料層
400‧‧‧雷射輻射
402‧‧‧雷射誘導缺陷
404‧‧‧拉伸應力
408‧‧‧晶粒
450‧‧‧雷射輻射
452‧‧‧雷射誘導缺陷
453‧‧‧切割道
454‧‧‧拉伸應力
456‧‧‧裂紋
458‧‧‧晶粒
Claims (20)
- 一種切割一晶圓之方法,該方法包含以下步驟:提供一前側上具有積體電路且該等積體電路上安置有一晶圓級底部填料材料層之一半導體晶圓;自該半導體晶圓之一背側雷射輻射該半導體晶圓以沿該半導體晶圓之切割劃道產生缺陷,該等切割劃道經定向處於該等積體電路之間;以及在該雷射輻射後,沿該等切割劃道機械切單該等積體電路。
- 如請求項1所述之方法,其中在該等已切單積體電路之各者上固持該晶圓級底部填料材料層中的一部分以便進行後續晶粒堆疊處理。
- 如請求項1所述之方法,其中提供該半導體晶圓之步驟包含以下步驟:提供一單個晶體矽基板。
- 如請求項1所述之方法,其中自該背側雷射輻射該半導體晶圓之步驟包含以下步驟:使用一雷射光束,該雷射光束具有大於約1000奈米之一波長及大於或等於約10皮秒之一雷射脈衝寬度。
- 如請求項1所述之方法,其中沿該等切 割劃道機械切單該等積體電路之步驟包含以下步驟:在該半導體晶圓上施加一拉伸應力。
- 如請求項1所述之方法,進一步包含以下步驟:在機械切單該等積體電路前,自該半導體晶圓之該前側對該晶圓級底部填料材料層雷射劃線,該雷射劃線與該等切割劃道對準。
- 如請求項6所述之方法,其中該雷射劃線進一步包含以下步驟:對該半導體晶圓與該晶圓級底部填料材料層之間所形成之裝置層劃線。
- 如請求項6所述之方法,其中在該雷射輻射前執行該雷射劃線。
- 如請求項6所述之方法,其中該雷射劃線之步驟包含以下步驟:使用一雷射,該雷射具有飛秒範圍內的一脈衝寬度。
- 一種切割一晶圓之方法,該方法包含以下步驟:提供一前側上具有積體電路且該等積體電路上安置有一晶圓級底部填料材料層之一矽晶圓;在一基板載體之一切割膠帶上安裝該矽晶圓之一背側;自該背側穿過該切割膠帶雷射輻射該矽晶圓以沿 該矽晶圓之切割劃道產生缺陷,該等切割劃道經定向處於該等積體電路之間;以及在該雷射輻射後,沿該等切割劃道機械切單該等積體電路。
- 如請求項10所述之方法,其中在該等已切單積體電路之各者上固持該晶圓級底部填料材料層中的一部分以便進行後續晶粒堆疊處理。
- 如請求項10所述之方法,其中該切割膠帶對該雷射輻射至少大部分透明。
- 如請求項10所述之方法,其中自該背側雷射輻射該矽晶圓之步驟包含以下步驟:使用一雷射光束,該雷射光束具有大於約1000奈米之一波長及大於或等於約10皮秒之一雷射脈衝寬度。
- 如請求項10所述之方法,其中沿該等切割劃道機械切單該等積體電路之步驟包含以下步驟:藉由拉伸該基板載體之該切割膠帶在該矽晶圓上施加一拉伸應力。
- 如請求項10所述之方法,進一步包含以下步驟:在雷射輻射該矽晶圓前,對該晶圓級底部填料材料層及該矽晶圓與該晶圓級底部填料材料層之間所形成之裝置層雷射劃線,自該矽晶圓之該前側執行 該雷射劃線,且該雷射劃線與該等切割劃道對準,其中該雷射劃線之步驟包含以下步驟:使用一雷射,該雷射具有飛秒範圍內的一脈衝寬度。
- 一種切割一晶圓之方法,該方法包含以下步驟:提供一前側上具有積體電路且該等積體電路上安置有一晶圓級底部填料材料層之一矽晶圓;經由該晶圓級底部填料材料層在一基板載體之一切割膠帶上安裝該矽晶圓;自該矽晶圓之一背側雷射輻射該矽晶圓以沿該矽晶圓之切割劃道產生缺陷,該等切割劃道經定向處於該等積體電路之間;以及在該雷射輻射後,沿該等切割劃道機械切單該等積體電路。
- 如請求項16所述之方法,其中在該等已切單積體電路之各者上固持該晶圓級底部填料材料層中的一部分以便進行後續晶粒堆疊處理。
- 如請求項16所述之方法,其中自該背側雷射輻射該矽晶圓之步驟包含以下步驟:使用一雷射光束,該雷射光束具有大於約1000奈米之一波長及大於或等於約10皮秒之一雷射脈衝寬度。
- 如請求項16所述之方法,其中沿該等切割劃道機械切單該等積體電路之步驟包含以下 步驟:藉由拉伸該基板載體之該切割膠帶在該矽晶圓上施加一拉伸應力。
- 如請求項16所述之方法,進一步包含以下步驟:在雷射輻射該矽晶圓前,對該晶圓級底部填料材料層及該矽晶圓與該晶圓級底部填料材料層之間所形成之裝置層雷射劃線,自該矽晶圓之該前側執行該雷射劃線,且該雷射劃線與該等切割劃道對準,其中該雷射劃線之步驟包含以下步驟:使用一雷射,該雷射具有飛秒範圍內的一脈衝寬度。
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-
2014
- 2014-06-30 US US14/320,390 patent/US9093518B1/en active Active
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2015
- 2015-06-03 WO PCT/US2015/034046 patent/WO2016003584A1/en active Application Filing
- 2015-06-05 TW TW104118366A patent/TWI657540B/zh active
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WO2016003584A1 (en) | 2016-01-07 |
TWI657540B (zh) | 2019-04-21 |
US9093518B1 (en) | 2015-07-28 |
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