TW201133795A - Semiconductor memory device comprising three dimensional memory cell array - Google Patents

Semiconductor memory device comprising three dimensional memory cell array Download PDF

Info

Publication number: TW201133795A
Authority: TW; Taiwan
Prior art keywords: substrate; disposed; insulating layer; region; string
Prior art date: 2009-08-26

Application number

TW099128658A

Other languages

English (en)

Chinese (zh)

Inventor

Byoung-Keun Son

Han-Soo Kim

Young-Soo An

Min-Gu Kim

Jin-Ho Kim

Jae-Hyoung Choi

Suk-Hun Choi

Jae-Joo Shim

Won-Seok Cho

Su-Nil Shim

Ju-Young Lim

Original Assignee

Samsung Electronics Co Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2009-08-26

Filing date

2010-08-26

Publication date

2011-10-01

2010-04-01 Priority claimed from US12/752,485 external-priority patent/US8284601B2/en

2010-08-26 Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd

2011-10-01 Publication of TW201133795A publication Critical patent/TW201133795A/zh

Links

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Classifications

- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Engineering & Computer Science (AREA)
Power Engineering (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Computer Hardware Design (AREA)
Microelectronics & Electronic Packaging (AREA)
Manufacturing & Machinery (AREA)
Semiconductor Memories (AREA)
Non-Volatile Memory (AREA)
Read Only Memory (AREA)
Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

TW099128658A 2009-08-26 2010-08-26 Semiconductor memory device comprising three dimensional memory cell array TW201133795A (en)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
KR1020090079243A KR101548674B1 (ko)	2009-08-26	2009-08-26	3차원 반도체 메모리 장치 및 그 제조 방법
US12/752,485 US8284601B2 (en)	2009-04-01	2010-04-01	Semiconductor memory device comprising three-dimensional memory cell array

Publications (1)

Publication Number	Publication Date
TW201133795A true TW201133795A (en)	2011-10-01

Family

ID=43812682

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
TW099128658A TW201133795A (en)	2009-08-26	2010-08-26	Semiconductor memory device comprising three dimensional memory cell array

Country Status (4)

Country	Link
JP (1)	JP2011049561A (ko)
KR (1)	KR101548674B1 (ko)
CN (1)	CN102005456B (ko)
TW (1)	TW201133795A (ko)

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TWI681547B (zh) *	2017-11-23	2020-01-01	大陸商長江存儲科技有限責任公司	三維記憶結構以及其製作方法
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US10700083B1 (en)	2009-04-24	2020-06-30	Longitude Flash Memory Solutions Ltd.	Method of ONO integration into logic CMOS flow
US10756102B2 (en)	2017-11-23	2020-08-25	Yangtze Memory Technologies Co., Ltd.	Three-dimensional memory structure and manufacturing method thereof
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Publication number	Publication date
CN102005456A (zh)	2011-04-06
KR101548674B1 (ko)	2015-09-01
CN102005456B (zh)	2014-10-22
JP2011049561A (ja)	2011-03-10
KR20110021444A (ko)	2011-03-04

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