KR920702545A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법

Info

Publication number
KR920702545A
KR920702545A KR1019920700418A KR920700418A KR920702545A KR 920702545 A KR920702545 A KR 920702545A KR 1019920700418 A KR1019920700418 A KR 1019920700418A KR 920700418 A KR920700418 A KR 920700418A KR 920702545 A KR920702545 A KR 920702545A
Authority
KR
South Korea
Prior art keywords
semiconductor device
semiconductor
conductive
substrate
pattern portion
Prior art date
Application number
KR1019920700418A
Other languages
English (en)
Inventor
히사노부 이시야마
Original Assignee
아이자와 스스무
세이꼬 엡슨 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아이자와 스스무, 세이꼬 엡슨 가부시끼가이샤 filed Critical 아이자와 스스무
Publication of KR920702545A publication Critical patent/KR920702545A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

내용 없음

Description

반도체 장치 및 그 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1에 따르는 반도체 장치의 개요를 도시하는 외형도, 제2도는 제1도에 도시하는 반도체 장치의 Ⅱ-Ⅱ단면도, 제3도는 제1도에 도시하는 반도체 장치의 Ⅲ-Ⅲ단면도.

Claims (14)

  1. 적어도 1개의 반도체 집적 기판과 이 반도체 기판에 장착된 도전층을 구비한 도전 패턴부를 갖는 반도체 장치이며, 상기 도전 패턴부는 적어도 1층의 절연층을 구비한 복수층 구조이며 상기 도전층의 적어도 1부에는 일단이 상기 반도체 집적 기판의 전극과 접속되며 타단이 외부로 연장하는 배선 패턴이 형성되고 있는 것을 특징으로 하는 반도체 장치.
  2. 디바이스 호울을 구비한 필름상의 플레시블 기판과, 상기 디바이스 호울에 장착된 적어도 1개의 반도체 집적 기판과, 이 반도체 기판에 장착된 도전층을 구비한 도전 패턴부를 갖는 반도체 장치이며, 상기 도전 패턴부는 적어도 1층의 절연층을 구비한 복수층 구조이며, 상기 도전층의 적어도 1부에는 일단이 상기 반도체 집적 기판의 전극과 접속되며 타단이 외부로 연장하는 배선 패턴이 형성되어 있는 것을 특징으로 하는 반도체 장치.
  3. 제1항 또는 2항에 있어서, 복수의 상기 도전층에 형성되어 있는 상기 배선 패턴이 동 형상의 마스크 패턴을 써서 형성가능하다는 것을 특징으로 하는 반도체 장치.
  4. 제1내지 3항중 어느 한 항에 있어서, 복수의 상기 도전층에 형성되고 있는 상기 배선 패턴의 상기 타단에 의해서 단일층의 전극열이 형성되고 있는 것을 특징으로 하는 반도체 장치.
  5. 제1 내지 4항중 어느 한항에 있어서, 상기 도통 패턴부는 그 두께 방향에 형성된 유전로를 구비하고 있는 것을 특징으로 하는 반도체 장치.
  6. 제5항에 있어서, 상기 통전로에 의해서 상기 전극과 상기 배선 패턴의 상기 일단이 접속되어 있는 것을 특징으로 하는 반도체 장치.
  7. 제5항 또는 6항에 있어서, 상기 통전로는 관통공인 것을 특징으로 하는 반도체 장치.
  8. 제5항 또는 6항에 있어서, 상기 통전로는 범프인 것을 특징으로 하는 반도체 장치.
  9. 제1 내지 8항중 어느 한 항에 있어서, 상기 도전 패턴부에 상기 배선 패턴의 상기 일단의 위치와 상기 반도체 기판의 상기 전극의 위치를 일치하기 위한 마크홀이 형성되고 있는 것을 특징으로 하는 반도체 장치.
  10. 제1 내지 9항중 어느 한 항에 있어서, 상기 절연층은 폴리이미드층인 것을 특징으로 하는 반도체 장치.
  11. 제2 내지 10항중 어느 한 항에 있어서, 상기 플렉시블 기판은 폴리이미드 테이프인 것을 특징으로 하는 반도체 장치.
  12. 제1 내지 11항중 어느 한 항에 기재인 반도체 장치의 제조 방법이며, 상기 도체 패턴부를 플렉시블 기판상에 포토리토그래피법에 의해 형성하는 도체 패턴 형성 공정에 이어서 상기 절연층을 롤 코트법에 의해 형성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
  13. 제12항에 있어서, 상기 절연층은 폴리이미드로 형성되어 있는 것을 특징으로 하는 반도체 장치의 제조 방법.
  14. 제12항 또는 13항에 있어서, 상기 플렉시블 기판은 폴리이미드 테이프인 것을 특징으로 하는 반도체장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920700418A 1990-06-26 1991-06-11 반도체 장치 및 그 제조 방법 KR920702545A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16737190 1990-06-26
JP90-167371 1990-06-26
PCT/JP1991/000786 WO1992000603A1 (en) 1990-06-26 1991-06-11 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
KR920702545A true KR920702545A (ko) 1992-09-04

Family

ID=15848475

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920700418A KR920702545A (ko) 1990-06-26 1991-06-11 반도체 장치 및 그 제조 방법

Country Status (4)

Country Link
US (1) US5313367A (ko)
EP (1) EP0489177A4 (ko)
KR (1) KR920702545A (ko)
WO (1) WO1992000603A1 (ko)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5678301A (en) * 1991-06-04 1997-10-21 Micron Technology, Inc. Method for forming an interconnect for testing unpackaged semiconductor dice
US5355019A (en) * 1992-03-04 1994-10-11 At&T Bell Laboratories Devices with tape automated bonding
JP3151219B2 (ja) 1992-07-24 2001-04-03 テツセラ，インコーポレイテッド 取り外し自在のリード支持体を備えた半導体接続構成体およびその製造方法
US5977618A (en) 1992-07-24 1999-11-02 Tessera, Inc. Semiconductor connection components and methods with releasable lead support
US5596171A (en) * 1993-05-21 1997-01-21 Harris; James M. Package for a high frequency semiconductor device and methods for fabricating and connecting the same to an external circuit
US5418687A (en) * 1994-02-01 1995-05-23 Hewlett-Packard Company Wafer scale multi-chip module
JP3014029B2 (ja) * 1995-06-16 2000-02-28 日本電気株式会社 半導体素子の実装方法
US6239384B1 (en) 1995-09-18 2001-05-29 Tessera, Inc. Microelectric lead structures with plural conductors
WO1997011588A1 (en) 1995-09-18 1997-03-27 Tessera, Inc. Microelectronic lead structures with dielectric layers
JP2859194B2 (ja) * 1996-01-30 1999-02-17 九州日本電気株式会社 プラスチックパッケージ型半導体集積回路及びその製造 方法
DE19617055C1 (de) * 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
US6795120B2 (en) * 1996-05-17 2004-09-21 Sony Corporation Solid-state imaging apparatus and camera using the same
JPH10116861A (ja) * 1996-10-09 1998-05-06 Texas Instr Japan Ltd キャリアテープ、及びキャリアテープ製造方法
US6687842B1 (en) 1997-04-02 2004-02-03 Tessera, Inc. Off-chip signal routing between multiply-connected on-chip electronic elements via external multiconductor transmission line on a dielectric element
WO1998044564A1 (en) 1997-04-02 1998-10-08 Tessera, Inc. Chip with internal signal routing in external element
US6175509B1 (en) * 1997-05-14 2001-01-16 Hewlett-Packard Company Space efficient local regulator for a microprocessor
US6024589A (en) * 1997-05-14 2000-02-15 Hewlett-Packard Company Power bus bar for providing a low impedance connection between a first and second printed circuit board
JP2002064224A (ja) * 2000-08-18 2002-02-28 Agilent Technologies Japan Ltd 発光ダイオード及びその製造方法
DE10228328A1 (de) * 2002-06-25 2004-01-22 Epcos Ag Elektronisches Bauelement mit einem Mehrlagensubstrat und Herstellungsverfahren
DE102004018468A1 (de) * 2004-04-16 2006-02-16 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Verfahren zum strukturierten Aufbringen einer laminierbaren Folie auf ein Substrat für ein Halbleitermodul
JP4708214B2 (ja) * 2006-02-23 2011-06-22 浜松ホトニクス株式会社 光送受信デバイス
US9535094B2 (en) * 2013-10-17 2017-01-03 Research & Business Foundation Sungkyunkwan University Vertical/horizontal probe system and calibration kit for the probe system
JP6689691B2 (ja) * 2016-07-12 2020-04-28 新光電気工業株式会社 配線基板及びその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051274A (en) * 1975-04-03 1977-09-27 Dainippon Screen Seizo Kabushiki-Kaisha Method for coating the photoresist onto a belt-like material comprising a perforated carrier and metallic foil
JPS5284969A (en) * 1976-01-07 1977-07-14 Hitachi Ltd Electrode connection method and lead tape used for the same
JPS556852A (en) * 1978-06-28 1980-01-18 Mitsubishi Electric Corp Semiconductor device
JPS58159361A (ja) * 1982-03-17 1983-09-21 Sanyo Electric Co Ltd 多層混成集積回路装置
JPS6046040A (ja) * 1983-08-24 1985-03-12 Nec Corp 半導体装置
JPS6080232A (ja) * 1983-10-11 1985-05-08 Nippon Telegr & Teleph Corp <Ntt> Ｌｓｉチツプ実装用カ−ド
JPS61225825A (ja) * 1985-03-29 1986-10-07 Seiko Epson Corp Ｉｃ実装構造
JPS6267828A (ja) * 1985-09-20 1987-03-27 Sharp Corp 半導体デバイスの実装構造
JPS62158339A (ja) * 1985-12-28 1987-07-14 Tanaka Denshi Kogyo Kk 半導体装置におけるｉｃチツプへのボンデイングリ−ドの接着方法
JPS6352461A (ja) * 1986-08-22 1988-03-05 Olympus Optical Co Ltd 半導体装置
JPS63164229A (ja) * 1986-12-25 1988-07-07 Mitsubishi Electric Corp 半導体装置
JP2507476B2 (ja) * 1987-09-28 1996-06-12 株式会社東芝 半導体集積回路装置
JPH01108934A (ja) * 1987-10-20 1989-04-26 Yohei Yamashita 生鮮食品の貯蔵庫
JPH01108934U (ko) * 1988-01-18 1989-07-24
US4937707A (en) * 1988-05-26 1990-06-26 International Business Machines Corporation Flexible carrier for an electronic device
JPH01303730A (ja) * 1988-06-01 1989-12-07 Hitachi Ltd 半導体素子の実装構造とその製造方法
JPH02142151A (ja) * 1988-11-22 1990-05-31 Nec Corp 集積回路装置
US4912547A (en) * 1989-01-30 1990-03-27 International Business Machines Corporation Tape bonded semiconductor device
JP2816239B2 (ja) * 1990-06-15 1998-10-27 株式会社日立製作所 樹脂封止型半導体装置
JP2505308B2 (ja) * 1990-09-06 1996-06-05 株式会社日立製作所 半導体装置

Also Published As

Publication number Publication date
WO1992000603A1 (en) 1992-01-09
EP0489177A1 (en) 1992-06-10
US5313367A (en) 1994-05-17
EP0489177A4 (en) 1993-06-09

Similar Documents

Publication Publication Date Title
KR920702545A (ko) 반도체 장치 및 그 제조 방법
KR960035835A (ko) 반도체장치와 그 제조방법
KR970067822A (ko) 반도체장치의 제조방법 및 반도체장치의 패키지
KR930011781A (ko) 배선판의 제조법
KR900005576A (ko) 반도체 집적회로 장치
EP0782190A3 (en) Semiconductor device comprising an inductor element
KR870007568A (ko) 테이프 자동 접착용 금속 테이프 및 그 에칭방법
KR950004532A (ko) 고집적 반도체 배선구조 및 그 제조방법
KR930001361A (ko) 플립 칩 실장 및 결선 패키지 및 그 방법
KR920020618A (ko) 반도체 장치의 배선 접속 구조 및 그 제조방법
KR970024015A (ko) 다층 배선을 형성하는 방법(Method of Forming Multi-Layer Interconnection)
KR930003297A (ko) 반도체장치용 테이프 케리어 및 그 제조방법
KR930009052A (ko) 안티휴즈를 갖춘 반도체장치
KR920022456A (ko) 동 배선의 형성방법
KR950012628A (ko) 스크라이브라인영역을 위한 이중적 금속배선층들을 갖는 반도체장치
KR890015403A (ko) 반도체집적회로장치
KR960028723A (ko) 프린트 회로기판
KR870004519A (ko) 집적 반도체 회로
KR930006832A (ko) 다층 금속 상호 접속부를 갖는 반도체 장치
KR910017624A (ko) 반도체집적회로장치
KR910019194A (ko) 반도체장치 및 그 제조방법
KR920015520A (ko) 탭(TAB)의 필름캐리어테이프(Film carrier tape)
KR880700616A (ko) 다층 프린트 기판
KR870005460A (ko) 다층 혼성 집적회로 및 그 제조방법
KR930011168A (ko) 회로기판 및 그 제조방법

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid