KR970067822A - 반도체장치의 제조방법 및 반도체장치의 패키지 - Google Patents
반도체장치의 제조방법 및 반도체장치의 패키지 Download PDFInfo
- Publication number
- KR970067822A KR970067822A KR1019960071161A KR19960071161A KR970067822A KR 970067822 A KR970067822 A KR 970067822A KR 1019960071161 A KR1019960071161 A KR 1019960071161A KR 19960071161 A KR19960071161 A KR 19960071161A KR 970067822 A KR970067822 A KR 970067822A
- Authority
- KR
- South Korea
- Prior art keywords
- hole
- metal foil
- forming
- insulating substrate
- main surface
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 238000007747 plating Methods 0.000 claims abstract 4
- 239000011888 foil Substances 0.000 claims 24
- 239000002184 metal Substances 0.000 claims 24
- 239000000758 substrate Substances 0.000 claims 12
- 238000000059 patterning Methods 0.000 claims 3
- 238000007789 sealing Methods 0.000 claims 3
- 238000010030 laminating Methods 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
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- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
프린트기판형 BGA 패키지를 구비하는 반도체장치의 제조방법 및 반도체 장치의 패키지에 관한 것으로서, 프린트기판형 BGA의 프린트기판에 형성되는 배선의 간격을 좁게 하기 위해, 배선층(20a),(22a)는 도금이 실시되고 있지 않는 분만큼 종래보다 얇게 형성되고 있고, 배선층(19a)(23a)는 도금이 1층뿐이므로 종래보다 얇게 형성되어 있으며, 얇게 형성되어 있는 배선층 (19a)(20a)(22a)(23a)는 배선간격을 좁게 형성하기 쉽게 되어 있다. 이러한 것에 의해 얇은 도전체층을 패터닝할 수 있어 패터닝된 배선간의 피치를 좁게 할 수 있다는 등의 효과가 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제14도는 실시형태1의 반도체장치의 1제조공정을 도시한 단면도.
Claims (3)
- 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하는 반도체장치의 제조방법.
- 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하고, 상기 제1프린트기판(15a)를 준비하는 공정은 상기 절연기판(18)의 상기 제1주면에 상기 제1금속박(30)을 형성하는 공정, 상기 절연기판과 상기 제1금속박을 관통하는 상기 제1구멍(60)을 형성하는 공정 및 상기 절연기판의 상기 제2주면에 상기 제2금속박(31a)를 적층하는 공정을 구비하는 반도체장치의 제조방법.
- 절연기판(18,101), 이 절연기판의 제1주면에 형성된 제1금속박(30,103) 및 제2주면에 형성된 제2금속박(31a,102)을 갖고,상기 제1금속박을 관통해서 상기 제2금속박에 도달함과 동시에 이 제2금속박에 의해 덮혀진 제1구멍(60,104,147,150)이 형성되어 있는 제1프린트기판(15a,100)을 준비하는 공정, 상기 제1구멍을 덮고 있는 영역(61,105)를 남기고 상기 제2금속박을 패터닝하는 공정, 상기 제1구멍을 덮고 있는 영역에 면하고 또한 밀봉되어 있는 공동(39,108)을 형성하도록 소정의 부재(16a,90)을 상기 절연기판의 상기 제2주면에 접착하는 공정, 상기 제1구멍에 도금을 실시하고 상기 제1 및 제2금속박을 접속하는 제1도전경로(25a,111)를 형성하는 공정 및 상기 제1도전경로를 형성하는 공정후에 상기 제1프린트기판과 상기 소정의 부재를 포함하는 집합체에 대해 상기 공동에 도달하는 개구부(45,116,117)를 형성하는 공정을 구비하고, 상기 제1구멍을 슬릿형사의 구멍(147,`150)을 포함하고, 상기 개구부(45a)를 형성하는 공정은 상기 슬릿형상의 구멍(150)의 외벽을 남기고 그 내벽을 깍아서 그 슬릿형상의 구멍의 바닥부단면을 노출시키는 공정, 상기 슬릿형상의 구멍의 상기 외벽의 상부를 스폿페이싱가공에 의해서 깍아내는 공정 및 상기 슬릿형상의 구멍의 상기 바닥부상에 패드(69)를 형성하는 공정을 구비하는 반도체장치의 제조방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8074571A JPH09266268A (ja) | 1996-03-28 | 1996-03-28 | 半導体装置の製造方法および半導体装置のパッケージ |
JP96-074571 | 1996-03-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970067822A true KR970067822A (ko) | 1997-10-13 |
KR100213857B1 KR100213857B1 (ko) | 1999-08-02 |
Family
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Application Number | Title | Priority Date | Filing Date |
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KR1019960071161A KR100213857B1 (ko) | 1996-03-28 | 1996-12-24 | 반도체장치의 제조방법 및 반도체장치의 패키지 |
Country Status (6)
Country | Link |
---|---|
US (2) | US6005289A (ko) |
JP (1) | JPH09266268A (ko) |
KR (1) | KR100213857B1 (ko) |
CN (1) | CN1138302C (ko) |
DE (1) | DE19650296A1 (ko) |
TW (1) | TW332962B (ko) |
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AT515101B1 (de) | 2013-12-12 | 2015-06-15 | Austria Tech & System Tech | Verfahren zum Einbetten einer Komponente in eine Leiterplatte |
US11523520B2 (en) | 2014-02-27 | 2022-12-06 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for making contact with a component embedded in a printed circuit board |
AT515447B1 (de) | 2014-02-27 | 2019-10-15 | At & S Austria Tech & Systemtechnik Ag | Verfahren zum Kontaktieren eines in eine Leiterplatte eingebetteten Bauelements sowie Leiterplatte |
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-
1996
- 1996-03-28 JP JP8074571A patent/JPH09266268A/ja active Pending
- 1996-10-24 US US08/738,935 patent/US6005289A/en not_active Expired - Fee Related
- 1996-11-07 TW TW085113595A patent/TW332962B/zh active
- 1996-12-04 DE DE19650296A patent/DE19650296A1/de not_active Withdrawn
- 1996-12-23 CN CNB961179139A patent/CN1138302C/zh not_active Expired - Fee Related
- 1996-12-24 KR KR1019960071161A patent/KR100213857B1/ko not_active IP Right Cessation
-
1999
- 1999-09-22 US US09/400,912 patent/US6256875B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE19650296A1 (de) | 1997-10-02 |
JPH09266268A (ja) | 1997-10-07 |
TW332962B (en) | 1998-06-01 |
KR100213857B1 (ko) | 1999-08-02 |
US6005289A (en) | 1999-12-21 |
CN1138302C (zh) | 2004-02-11 |
CN1160984A (zh) | 1997-10-01 |
US6256875B1 (en) | 2001-07-10 |
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