KR930001361A - 플립 칩 실장 및 결선 패키지 및 그 방법 - Google Patents

플립 칩 실장 및 결선 패키지 및 그 방법 Download PDF

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KR930001361A
KR930001361A KR1019920011120A KR920011120A KR930001361A KR 930001361 A KR930001361 A KR 930001361A KR 1019920011120 A KR1019920011120 A KR 1019920011120A KR 920011120 A KR920011120 A KR 920011120A KR 930001361 A KR930001361 A KR 930001361A
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South Korea
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substrate
chip
circuit
circuit board
conductive
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KR1019920011120A
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KR960009092B1 (ko
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제이. 그릭 존
케이. 쇼다 크래이그
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원다 케이. 덴슨-로우
휴즈 에어크라프트 캄파니
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Publication of KR930001361A publication Critical patent/KR930001361A/ko
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Publication of KR960009092B1 publication Critical patent/KR960009092B1/ko

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Abstract

내용 없음

Description

플립 칩 실장 및 결선 패키지 및 그 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 전도체들의 레이 아웃을 포함하는 본 발명의 반도체 칩의 부착 및 실장을 예시하는 다층 회로 기판의 사시도.
제2도는 제1도에 도시된 회로 기판의 다층 구조를 예시하는 단면도.
제3도는 제2도의 단면도를 확대한 도면.

Claims (19)

  1. 용적체를 통하여 연장하는 전도성 트레이스와, 홀과 연관된 전도성 트레이스의 부분을 노출시키기에 충분한 길이로 회로 기판의 표면으로부터 상기 용적체내로 연장하는 일련의 상기 홀을 가지는 상기 회로기판과; 상기 일련의 각각의 홀내의 전도성 물질과; 상기 홀내로 연장하며, 상기 전도성 물질과 접촉하여 상기 트레이스와 전기적 접속을 형성하는 일련의 금속 기둥을 가지는 반도체 칩을 포함하는 회로.
  2. 제1항에 있어서, 상기 전도성 물질은 땜납인 회로.
  3. 제1항에 있어서, 상기 전도성 물질은 전도성 에폭시인 회로.
  4. 제1항에 있어서, 상기 금속 기둥은 전착된 금속 기둥인 회로.
  5. 제1항에 있어서, 상기 회로 기판은 상기 반도체 칩과 인접한 공동을 형성하는 회로.
  6. 제5항에 있어서, 유전체 부동성 층이 상기 반도체 칩과 상기 회로기판 사이에서 연장하는 회로.
  7. 제6항에 있어서, 상기 유전체 부동성 층은 유리로 이루어진 회로.
  8. 제1항에 있어서, 상기 회로 기판상에 다수의 반도체 칩을 더 포함하는 회로
  9. 제1항에 있어서, 상기 기판은 다층 회로 기판인 회로.
  10. 제5항에 있어서, 상기 공동은 상기 홀들 사이에서 상기 칩의 대부분의 영역 아래에서 연장하므로써 상기 칩의 주요 부분을 회로 기판으로부터 격리시키는 공기 간극을 제공하는 회로.
  11. 입력/출력 패드를 가지는 칩을 기판상에 실장하는 방법이:그 용적체를 통하여 연장하는 전도성 트레이스를 가지는 기판을 형성하는 단계와; 금속 기둥을 상기 칩의 입력/출력 패드상에 형성하는 단계와; 상기 기판에 상기 전도성 트레이스에 접근하는 일련의 홀을 상기 칩의 상기 금속 기둥에 조화하는 패턴으로 형성하는 단계와; 상기 기판의 홀에 상기 트레이스와 전기적으로 접촉하는 전도성 물질을 배치하는 단계와; 상기 칩의 상기 금속 기둥을 상기 기판의 상기 홀내에 정렬시킴으로써 상기 칩을 상기 기판상에 실장하는 단계를 포함하는 방법.
  12. 제11항에 있어서, 상기 금속 기둥은 전기 도금에 의해 형성되는 방법.
  13. 제11항에 있어서, 상기 기판은 다층 회로 기판인 방법.
  14. 제13항에 있어서, 상기 회로 기판은 다층으로 되어 있으며, 상기 전도성 트레이스는 상기 회로 기판의 상기 층들사이에서 연장하는 방법.
  15. 제11항에 있어서, 상기 전도성 물질은 전도성 에폭시인 방법.
  16. 제11항에 있어서, 상기 전도성 물질은 땜납인 방법.
  17. 제16항에 있어서, 상기 기판을 가열하여 상기 칩의 기둥과 상기 전도성 트레이스 사이에 땜납 접속을 형성하는 단계를 더 포함하는 방법.
  18. 제11항에 있어서, 상기 기판에서 상기 기판의 외부로 개방된 공동을 형성하는 단계를 더 포함하며, 상기 칩은 상기 기판상에서 상기 공동위에 실장되는 방법.
  19. 제11항에 있어서, 상기 실장 단계 이전에 상기 유전체 부동성 층을 상기 반도체 칩에 인접하게 배치하는 단계를 더 포함하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920011120A 1991-06-26 1992-06-25 집적된 소켓형 패키지 및 기판상의 칩 실장 방법 KR960009092B1 (ko)

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JPH0810718B2 (ja) 1996-01-31
IL102269A0 (en) 1993-01-14
JPH05275492A (ja) 1993-10-22
KR960009092B1 (ko) 1996-07-10
EP0520434A1 (en) 1992-12-30
AU1855092A (en) 1993-03-11
AU647632B2 (en) 1994-03-24
IL102269A (en) 1997-03-18

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