JP3014029B2 - 半導体素子の実装方法 - Google Patents

半導体素子の実装方法

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Publication number
JP3014029B2
JP3014029B2 JP7150467A JP15046795A JP3014029B2 JP 3014029 B2 JP3014029 B2 JP 3014029B2 JP 7150467 A JP7150467 A JP 7150467A JP 15046795 A JP15046795 A JP 15046795A JP 3014029 B2 JP3014029 B2 JP 3014029B2
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
multilayer wiring
bare chip
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7150467A
Other languages
English (en)
Other versions
JPH098213A (ja
Inventor
泰嗣 白川
靖則 田中
恒充 國府田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7150467A priority Critical patent/JP3014029B2/ja
Priority to US08/663,941 priority patent/US5801438A/en
Priority to AU55995/96A priority patent/AU714028B2/en
Priority to GB9924164A priority patent/GB2339337B/en
Priority to GB9612613A priority patent/GB2302451B/en
Publication of JPH098213A publication Critical patent/JPH098213A/ja
Application granted granted Critical
Publication of JP3014029B2 publication Critical patent/JP3014029B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体素子の実装方法に
関する。
【０００２】
【従来技術】従来、多層配線基板に凹部を設けた技術と
しては、次のようなものがある。 （１）実装部品の電極と基板の導体パターンとの接続を
最短にするため、該電極と導体パターンとを同一となる
ように凹部を設けた混成集積回路部品の実装構造が特開
昭６４−５７６５３に記載されている。 （２）厚膜基板に凹部を設け、その中にチップを実装す
る混成集積回路の多層厚膜基板が特開平１−２５８４４
６に記載されている。 （３）フラックスなどによる半導体素子の汚染や劣化を
防止するために凹部を設け、封止部材により密閉した混
成集積回路装置が特開平４−３５９４６２に記載されて
いる。 （４）高密度化・小型化のために凹部に半導体素子を多
層配線基板の中に実装し、さらにその上にパッケージン
グされた半導体素子を実装するマルチチップモジュール
が特開平７−３００５９などに記載されている。
【０００３】特に特開平７−３００５９に記載の従来技
術は基板の面積がパッケージングされた半導体素子に代
表される表面実装部品の面積と個数で決定されるため、
高集積化・小型化のために基板に凹部を設け、ベアチッ
プの半導体素子を埋め込む実装構造の提案であるが、具
体的な製造方法や薄型化のための工夫については記載さ
れていない。
【０００４】
【発明が解決しようとする課題】しかしながら、これら
の従来技術には次のような問題点が存在する。 （１）製品の薄型化に関する問題点 従来の技術においては、実装面積を削減するために凹部
を設け、その中へベアチップの半導体素子を多層配線基
盤の中へ実装するものであり、実際にこれらを実現する
ためには、凹部を封止するための絶縁性樹脂が基板面よ
り上にはみ出してはならない。そのためには基板の凹部
を深く設ける必要があり、基板の薄型化が困難であっ
た。 （２）凹部の大きさに関する問題点 封止した凹部をまたぐようにパッケージされた半導体素
子を実装するには凹部の面積の削減が必須であった。
【０００５】本発明は上述の問題点にかんがみてなされ
たもので、高集積化された薄型・軽量のマルチチップモ
ジュールおよびこれを製作するための半導体素子の実装
方法を提供することを目的とする。
【０００６】
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体素子の実装方法は、多層配線基板に
設けた凹部または穴部の面積を削減するために前記凹部
または穴部を二段構成にしてなる多層配線基板にベアチ
ップの半導体素子を実装し、封止する半導体素子の実装
方法において、多層配線基板とベアチップとの間を、可
能な限りの短距離・低ループワイヤボンディングを行う
工程と、開口率が高くメッシュ厚の薄いスクリーン印刷
を行うことにより、絶縁性樹脂が前記基板の表面からは
み出さないように封止する工程とを含むことを特徴とす
る。
【０００７】
【作用】絶縁性樹脂の封止工程において開口率が高くメ
ッシュ厚の薄いスクリーン印刷を行うことにより、基板
面から凹部を封止する絶縁性樹脂がはみ出さないのでマ
ルチチップモジュールは薄型になる。凹部を二段構成に
して可能な限りの短距離・低ループワイヤボンディング
を行うことによりマルチチップモジュールの凹部面積が
削減されて小型となり、且つ性能が向上する。
【０００８】
【実施例】以下本発明を図面に基づいて説明する。
【０００９】 図１は本発明の第１実施例の概略構成を説
明する縦断面図である。図１において、パッケージング
された半導体素子１が多層配線基板３の上面から上方に
離れた工程途中の状態で示されている。
【００１０】 多層配線基板３には二段構成の凹部８が複
数個形成されている。この二段構成の凹部８はベアチッ
プの半導体素子２を接着剤７で固定するための下層と、
ベアチップの半導体素子２上の電極と接続される多層配
線基板３側の電極５が配線された上層とから構成されて
いる。
【００１１】 ベアチップの半導体素子２上の電極と接続
される多層配線基板３上の電極５は無電解金めっき処理
が施されている。これは、電解金めっき処理が施されて
いると凹部８の側面から電極５が露出するので、この露
出した電極５とベアチップの半導体素子２の側面が接触
し、短絡してしまう危険が生ずるからである。また、短
絡防止のためベアチップの半導体素子２と凹部８の側面
との距離を十分に取ると、凹部８の面積が増えてしまう
結果となる。
【００１２】 本発明による半導体素子の実装方法の工程
は、まず凹部８の下層にベアチップの半導体素子２をマ
ウントし、ベアチップの半導体素子２の電極と上層にあ
る多層配線基板３上の電極５とを、金、銅またはアルミ
製のワイヤ６によるワイヤボンディングにより接続され
ている。
【００１３】 凹部８のベアチップの半導体素子２を実装
後に絶縁性樹脂４にて封止する。例えば、取り付け高さ
が１．２７ｍｍに抑えられたＴＳＯＰやＴＱＦＰパッケ
ージにおいては、パッケージングされた半導体素子１の
底部から多層配線基板３面までの距離が０．０５±０．
０５ｍｍの範囲（すなわち、０〜０．１ｍｍ）と規定さ
れているため、０に近い場合に多層配線基板３面に接触
する可能性が十分にある。
【００１４】 凹部８を封止した絶縁性樹脂４が多層配線
基板３面からはみ出すとパッケージングされた半導体素
子１の底部に接触し、リードが多層配線基板３のランド
から浮くために半田付け不良を起こしてしまう。そこで
少量の絶縁性樹脂４の定量供給のために、本発明ではス
クリーン印刷技術を用いる。絶縁性樹脂４の吐出性を良
くするために開口率を高くしたスクリーンメッシュを使
用する。また、５０μｍ以下の封止高さを実現するため
には極力メッシュ厚の薄いスクリーンを用いる。
【００１５】 多層配線基板３を有効活用するために、さ
らにこの上をまたぐようにして、パッケージングされた
半導体素子１のような大型部品を実装する。前記したよ
うに、凹部８をまたぐためには凹部８の面積が小さいこ
とが望ましい。凹部８の面積はベアチップの半導体素子
２の面積以下にはならないので、いかにして短距離・低
ループボンディングを実現するかが重要である。本発明
では多層配線基板３の電極５が形成される層をベアチッ
プの半導体素子２の電極面よりも１０μｍ程度高く設定
し、より接続長を短くしている。
【００１６】 図３は本発明の第３実施例の概略構成を説
明する縦断面図である。
【００１７】 図３に示すように、現在のボンディング技
術ではベアチップの半導体素子２の電極面を高くしたほ
うが低ループボンディングを実現することができる。こ
の点以外は第１実施例の説明と同一である。
【００１８】 図２は本発明の第２実施例の概略構成を説
明する縦断面図である。
【００１９】 この第２実施例において、多層配線基板３
が薄いため第１実施例や第３実施例のような二段構成の
凹部を形成することが困難な場合、凹部の代わりに貫通
した穴部９を形成したものである。穴部９とした場合に
はベアチップの半導体素子２をワイヤボンディングする
際に固定する方法として接着剤７の代わりにベアチップ
の半導体素子２の下面より真空吸着を行う。穴部９以外
は第１実施例の説明と同一である。
【００２０】
【発明の効果】以上説明したように、本発明によれば多
層配線基板に二段構成の凹部を設け、ベアチップの半導
体素子上の電極と接続される多層配線基板上の電極は無
電解金めっき処理が施され、可能な限り短距離・低ルー
プワイヤボンディングを行うようにし、絶縁性樹脂の封
止工程において開口率が高くメッシュ厚の薄いスクリー
ン印刷を行うようにしたので、凹部の深さがチップの厚
さ＋２００μｍ程度、大きさがチップ寸法＋４ｍｍ程度
と、表面実装部品の中でも占有率の大きいパッケージン
グされた半導体素子を、ベアチップの半導体素子として
多層基板の中へと実装するために必要な寸法を限定する
ことができ、多層配線基板の小型化・薄型化を達成する
ことができる。
【図面の簡単な説明】
【図１】本発明の第１実施例の概略構成を説明する縦断
面図である。
【図２】本発明の第２実施例の概略構成を説明する縦断
面図である。
【図３】本発明の第３実施例の概略構成を説明する縦断
面図である。
【符号の説明】
１ パッケージングされた半導体素子
フロントページの続き (72)発明者 國府田 恒充 東京都港区芝五丁目７番１号 日本電気 株式会社内 (56)参考文献 特開 昭54−12270（ＪＰ，Ａ) 特開 平６−291246（ＪＰ，Ａ)

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】 多層配線基板に設けた凹部または穴部の
    面積を削減するために前記凹部または穴部を二段構成に
    してなる多層配線基板にベアチップの半導体素子を実装
    し、封止する半導体素子の実装方法において、 多層配線基板とベアチップとの間を、可能な限りの短距
    離・低ループワイヤボンディングを行う工程と、 開口率が高くメッシュ厚の薄いスクリーン印刷を行うこ
    とにより、絶縁性樹脂が前記基板の表面からはみ出さな
    いように封止する工程とを含むことを特徴とする半導体
    素子の実装方法。
JP7150467A 1995-06-16 1995-06-16 半導体素子の実装方法 Expired - Fee Related JP3014029B2 (ja)

Priority Applications (5)

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JP7150467A JP3014029B2 (ja) 1995-06-16 1995-06-16 半導体素子の実装方法
US08/663,941 US5801438A (en) 1995-06-16 1996-06-14 Semiconductor device mounting and multi-chip module
AU55995/96A AU714028B2 (en) 1995-06-16 1996-06-14 Semiconductor device mounting method and multi-chip module produced by the same
GB9924164A GB2339337B (en) 1995-06-16 1996-06-17 Semiconductor device mounting method and multi-chip module produced by the same
GB9612613A GB2302451B (en) 1995-06-16 1996-06-17 Semiconductor device mounting method and multi-chip module produced by the same

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Application Number Priority Date Filing Date Title
JP7150467A JP3014029B2 (ja) 1995-06-16 1995-06-16 半導体素子の実装方法

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JP3014029B2 true JP3014029B2 (ja) 2000-02-28

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US5801438A (en) 1998-09-01
AU5599596A (en) 1997-01-02
GB9612613D0 (en) 1996-08-21
GB2302451A (en) 1997-01-15
JPH098213A (ja) 1997-01-10
GB2302451B (en) 2000-01-26
AU714028B2 (en) 1999-12-16

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