KR100322891B1 - 복합반도체 소자의 게이트 전극 제조방법 - Google Patents
복합반도체 소자의 게이트 전극 제조방법 Download PDFInfo
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- KR100322891B1 KR100322891B1 KR1019990067268A KR19990067268A KR100322891B1 KR 100322891 B1 KR100322891 B1 KR 100322891B1 KR 1019990067268 A KR1019990067268 A KR 1019990067268A KR 19990067268 A KR19990067268 A KR 19990067268A KR 100322891 B1 KR100322891 B1 KR 100322891B1
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- South Korea
- Prior art keywords
- gate electrode
- forming
- layer
- polycrystalline silicon
- etching
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002131 composite material Substances 0.000 claims abstract description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 8
- 150000004767 nitrides Chemical class 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (8)
- 메모리영역과 로직영역을 단일 웨이퍼에 구현하는 복합반도체 소자에 있어서,반도체 기판에 제 1 게이트 산화막을 형성하는 단계와,상기 제 1 게이트 산화막 위에 게이트 전극용 제 1 다결정실리콘층을 형성하는 단계와,상기 로직영역을 제외한 메모리영역의 제 1 다결정실리콘층을 식각하는 단계와,상기 결과물의 전면에 제 2 게이트 산화막을 형성하는 단계와,상기 제 2 게이트 산화막 위에 게이트 전극용 제 2 다결정실리콘층을 형성하는 단계와,상기 제 2 다결정실리콘층을 식각하여 상기 로직영역의 제 2 다결정실리콘을 제거함과 동시에 상기 메모리 영역에 게이트 전극을 형성하는 단계와,상기 로직영역에 있는 제 1 다결정실리콘층을 식각하여 상기 로직영역의 게이트 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 복합반도체 소자의 게이트전극 제조방법.
- 제 1 항에 있어서, 상기 제 1 다결정실리콘층을 형성하는 단계와 상기 로직영역을 제외한 메모리영역의 제 1 다결정실리콘층을 식각하는 단계 사이에, 상기 제 2 다결정실리콘층의 식각으로부터 상기 제 1 다결정실리콘층을 보호하기 위한 식각저지막을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합반도체 소자의 게이트전극 제조방법.
- 제 2 항에 있어서, 상기 식각저지막은 산화막임을 특징으로 하는 복합반도체 소자의 게이트전극 제조방법.
- 제 1 항에 있어서, 상기 제 2 다결정실리콘층을 형성하는 단계와 상기 제 2 다결정실리콘층을 식각하는 단계 사이에, 상기 제 2 다결정실리콘층의 식각시 함께 식각되어 게이트 전극을 이루는 텅스텐 실리사이드막을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합 반도체소자의 게이트전극 제조방법.
- 제 4 항에 있어서, 상기 텅스텐 실리사이드막을 형성하는 단계 후 상기 제 2 다결정실리콘층과 상기 텅스텐 실리사이드막의 식각시 함께 식각되어 게이트 전극을 이루는 질화막을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합 반도체 소자의 게이트전극 제조방법.
- 제 1 항에 있어서, 상기 메모리 영역에 게이트 전극을 형성하는 단계와 상기 로직영역에 게이트 전극을 형성하는 단계 사이에, 마스크패턴 공정을 적용하여 상기 로직 영역의 제 1 다결정실리콘층 일부분을 제 1 도전형 불순물로 도핑하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합 반도체소자의 게이트전극 제조방법.
- 제 1 항에 있어서, 상기 메모리 영역의 게이트 전극을 형성하는 단계 후 마스크 패턴공정을 적용하여 제 1 도전형과 반대되는 제 2 도전형 불순물을 선택적으로 이온주입하여 상기 메모리 영역의 정션영역을 형성함과 동시에 로직영역의 제 1 도전형 불순물로 도핑되지 않은 게이트 전극을 도핑하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합반도체 소자의 게이트 전극 제조방법.
- 제 7 항에 있어서, 상기 제 2 도전형 불순물을 이온주입하는 단계 후 상기 로직영역의 게이트 전극 및 정션에 살리사이드막을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 복합 반도체 소자의 게이트 전극 제조방법.
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KR1019990067268A KR100322891B1 (ko) | 1999-12-30 | 1999-12-30 | 복합반도체 소자의 게이트 전극 제조방법 |
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KR1019990067268A KR100322891B1 (ko) | 1999-12-30 | 1999-12-30 | 복합반도체 소자의 게이트 전극 제조방법 |
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KR20010059740A KR20010059740A (ko) | 2001-07-06 |
KR100322891B1 true KR100322891B1 (ko) | 2002-02-08 |
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KR1019990067268A KR100322891B1 (ko) | 1999-12-30 | 1999-12-30 | 복합반도체 소자의 게이트 전극 제조방법 |
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KR100418928B1 (ko) * | 2001-10-24 | 2004-02-14 | 주식회사 하이닉스반도체 | 엠디엘 반도체 소자의 제조 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980073173A (ko) * | 1997-03-12 | 1998-11-05 | 문정환 | 반도체 소자의 제조방법 |
KR19990002276A (ko) * | 1997-06-19 | 1999-01-15 | 문정환 | 반도체 소자의 제조방법 |
US5863820A (en) * | 1998-02-02 | 1999-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of sac and salicide processes on a chip having embedded memory |
KR19990026903A (ko) * | 1997-09-26 | 1999-04-15 | 구본준 | 반도체 소자의 제조방법 |
JPH11177065A (ja) * | 1997-12-08 | 1999-07-02 | Nec Corp | 半導体装置およびその製造方法 |
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1999
- 1999-12-30 KR KR1019990067268A patent/KR100322891B1/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980073173A (ko) * | 1997-03-12 | 1998-11-05 | 문정환 | 반도체 소자의 제조방법 |
KR19990002276A (ko) * | 1997-06-19 | 1999-01-15 | 문정환 | 반도체 소자의 제조방법 |
KR19990026903A (ko) * | 1997-09-26 | 1999-04-15 | 구본준 | 반도체 소자의 제조방법 |
JPH11177065A (ja) * | 1997-12-08 | 1999-07-02 | Nec Corp | 半導体装置およびその製造方法 |
US5863820A (en) * | 1998-02-02 | 1999-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of sac and salicide processes on a chip having embedded memory |
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