JPH0448767A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPH0448767A
JPH0448767A JP2155167A JP15516790A JPH0448767A JP H0448767 A JPH0448767 A JP H0448767A JP 2155167 A JP2155167 A JP 2155167A JP 15516790 A JP15516790 A JP 15516790A JP H0448767 A JPH0448767 A JP H0448767A
Authority
JP
Japan
Prior art keywords
wiring pattern
semiconductor
semiconductor device
lead frame
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2155167A
Other languages
English (en)
Other versions
JP2816239B2 (ja
Inventor
Makoto Kitano
誠 北野
Asao Nishimura
西村　朝雄
Akihiro Yaguchi
昭弘 矢口
Ryuji Kono
竜治 河野
Nae Yoneda
米田　奈柄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2155167A priority Critical patent/JP2816239B2/ja
Priority to KR1019910008853A priority patent/KR950005446B1/ko
Priority to US07/713,100 priority patent/US5539250A/en
Priority to EP91109654A priority patent/EP0461639B1/en
Priority to DE69127587T priority patent/DE69127587T2/de
Publication of JPH0448767A publication Critical patent/JPH0448767A/ja
Application granted granted Critical
Publication of JP2816239B2 publication Critical patent/JP2816239B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高集積化に適した樹脂封止型半導体装置のパ
ッケージ構造に関する。
〔従来の技術〕
一つの半導体パッケージに二枚以上の半導体素子を搭載
することは、半導体装置の高集積化する上で非常に有効
である。さらに、半導体素子の歩留が低い場合は、良品
の素子を組合わせて用いることにより、同じ面積の一枚
の素子を用いる場合に比べて、半導体装置全体の歩留り
が格段に向上する効果もある。
一つの半導体パッケージに二枚の半導体素子を搭載する
方法は、タブと呼ばれるリードフレームの一部の金属板
の両側に素子を接着し、それぞれの素子の電極とリード
をワイヤで接続する構造が特開昭６２−１３１５５５号
あるいは同６２−８５２９号公報に開示されている。ま
た、特開昭６２−１１９９５２号公報に記載のように、
パッケージ内部でリードフレームどおしを接合する方法
、特開昭６３−１２４４５０号公報に記載のように、二
段のリードフレームを樹脂封止する方法が公知である。
さらに一つのパッケージとは言い難いが、二つのパッケ
ージをコンパクトに接合し、実質的に一つのパッケージ
とする方法が特開昭６２−１６５５２号公報に開示され
ている。
〔発明が解決しようとする課題〕
上記従来技術は、それぞれ以下に示すような欠点がある
ため、実用化には至っていない。
タブの両側に素子を搭載する構造では、片面の素子電極
とリードフレームのワイヤ接続を終えた後、反対面のワ
イヤ接続を行う必要があるが、最初に接続したワイヤに
ダメージを与えないで反対面のワイヤ接続を行うことが
非常に困難である。
パッケージ内部でリードフレーム同士を接合する方法は
、パッケージが大きくなるという欠点がある。
二段のリードフレームを樹脂封止することは、非常に困
難であり、通常用いられているトランスファモールドで
量産的にこれを達成する技術は開発されていない。
二つのパンケージを接合する方法は、容易に達成できる
が、パッケージが厚くなるため、高積層化という点から
は、あまり意味がない。
以上の従来技術は、素子側面の近傍に配置されたリード
と素子電極をワイヤにより接続するため、素子上の電極
の位置が素子の周辺近付に限定される。このため、第１
６図に示すように、リードが素子上面まで延長されたパ
ッケージ（以下、リードオンチップ構造、略してＬＯＧ
構造と呼ぶ）′ｒ：用いる素子、すなわち、電極が素子
の中央付近に設けられた素子二枚を一つのパッケージに
搭載する場合には用いることができない。
さらに、素子側面近傍のリードと素子電極をワイヤによ
り接続するため、素子側面とパッケージ側面の間にある
程度の寸法が必要であり、大きな素子を搭載することが
できなかった。また、これらの公知例では、パッケージ
を薄くする場合の考慮がされていなかった。
本発明の目的は、電極が中央付近に設けられた大形の素
子二枚を薄形のパッケージに搭載するのに適し、さらに
量産性の良好なパッケージ構造を提供することにある。
［課題を解決するための手段〕 本発明は、上記目的を達成するため、パッケージを以下
のように構成した。
まず、金属の配線パターンを設けた絶縁フィルムを素子
の回路形成面に接着する。
次に、配線パターンと素子の電極をワイヤ等により電気
的に接続する。
次に、このように構成された素子を二枚用意し。
配線パターンが設けられた面を対向させ、リードフレー
ムを挾む。
次に、配線パターンとリードフレームをはんだ等で電気
的に接続する。
最後に、リードフレームの一部と半導体素子を樹脂封止
し、リードフレームのアウタリードを成形する。
〔作用〕
本発明のパッケージでは、形状が任意に設計できる配線
パターンを用いるので、素子の電極とリードフレームを
任意の位置で電気的に接続できる。
例えば、ＬＯＧパッケージ用の素子のように、素子の中
心線付近に電極が配置された素子を用いても、二枚の素
子を一つのパッケージに搭載することができる。
また、素子の側面とパッケージの側面との間に、電気的
接続部分がないので、素子をパッケージ外形近傍まで大
きくすることができ、高集積化が達成される。
従来のパッケージに対する本発明のパッケージの厚さの
増加は、基本的には素子−枚の厚さに留まるので、二枚
の素子を搭載するパンケージとしては、薄形化に好適で
ある。
さらに１本発明によるパッケージは、ＬＯＧパッケージ
の製造技術、テープオートメイテッドボンディング技術
など、従来技術をそのまま適用できるため、量産性が良
好である。
【実施例〕
以下、本発明の実施例を図を用いて説明する。
本発明の第一の実施例による半導体装置の断面図を第１
図に示す。また、第１図の中央部分の拡大図を第２図、
端部付近の拡大図を第３図に示す。
本実施例では、一つのパッケージに二枚の半導体素子１
ａ、ｌｂが対向して搭載されている。素子ｌａ、ｌｂの
回路形成面に、接着層８ｂ（第１図では省略）により絶
縁フィルム３が接合され、接着層８ａ（第１図では省略
）により配線パターン４が絶縁フィルム３に接合されて
いる。素子１ａ。
１ｂの中央部に設けられた電極７（第１図では省略）と
配線パターン４がワイヤ５により電気的に接続されてい
る。パッケージの端部では、配線パターン４とリードフ
レーム２が導電接着層９　（第１図では省略）を介して
電気的に接続されている。
これらの部材は、封止樹脂６により封止されている。
第４図に本実施例による半導体装置の製造方法を示す、
まず、搭載する二枚の半導体素子１ａ。
１ｂを用意しく４０１）、素子の回路形成面に絶縁フィ
ルム３を接着する（４０２）、フィルムの材質は、例え
ば、ポリイミドが好適であり、接着剤は。
例えば、エポキシ系樹脂を用いる０次に、既にパターン
成形された配線パターン４を絶縁フィルム３に接着する
（４０３）、本実施例の場合、配線パターン４の厚さは
、リードフレームと同等である。
次に、素子の電極（図では省略）と配線パターン４をワ
イヤ５により電気的に接続する（４０４）。
この後、配線パターン４の素子からはみ出た部分を切断
する（４０５）、なお、（４０６）の工程と（４０５）
の工程は順序を入れ換えて行っても良い。
このように構成した二組の部材を対向させてり−ドフレ
ーム２を挾み、配線パターン４とリードフレーム２を導
電接着層により電気的に接続する（４０６）、この接着
の方法には、例えば、はんだを用いる。このような半導
体装置では、リードをプリント基板に実装するのにはん
だが用いられ、パッケージが２５０”Ｃ程度に加熱され
る場合がある。従って、配線パターン４とリードフレー
ム２の接着に用いるはんだは、融点が２５０℃以上であ
ることが望ましい。また、この部分の接着には、銀ペー
ストなどの導電性樹脂を用いても良い。最後にこれらの
部材を樹脂６で封止しく４０７）。
リードフレーム２を成形すると、第１図に示した半導体
装置が得られる。
このように、本実施例による半導体装置は、従来の技術
を用いて中央部に電極が設けられた半導体素子二枚を一
つのパッケージに搭載することができる。また、素子の
側面とパッケージの側面との間に、電気的接続部分を設
ける必要がないので、この部分の寸法（第３図に示した
フレ寸法）を樹脂が破壊しない程度の寸法（通常０．８
ｍｓ程度）にまで短くすることができ、従って、大形の
素子の搭載が可能になる。
第１図の実施例では、配線パターン４の端部と素子側面
がそろっているが、配線パターン４の切断の都合で、第
５図に示すように、素子側面からはみ出していても良い
し、逆に、第６図に示すように、内側で切断されていて
も良い。
また、第１図の実施例では、素子１ａ、ｌｂの電極７は
素子中央部に設けられているが、電極の位置は第７図に
示すように片寄っていても良いし、また、第８図に示す
ように素子周辺に設けられていても良い。
絶縁フレーム３は、第９図に示すように分割されていて
も良い。さらに、配線パターン間の距離が短く、ワイヤ
とおしが接触する恐れがある場合は、第１０図に示すよ
うに、ワイヤ５ａ、５ｂを交互に配置すれば良い。
本発明の第二の実施例による半導体装置の断面の電極付
近の拡大図を第１１図に示す。本実施例では、第一の実
施例の構成に加え、電極７とワイヤ５の一部が第一の樹
脂１０ａ、１０ｂで覆われている。この第一の樹脂１０
ａ、１０ｂは、第４図の工程（４０４）もしくは（４０
５）において設けられる。このように電極７を樹脂で覆
うことにより、配線パターンとリードフレームをはんだ
接合する際に用いるフラックスによって電極７が腐食さ
れるのを防ぐことができる。
この第一の樹脂１０ａ、１０ｂは、電極のみではなく、
第１２図に示すように、ワイヤ５全体を覆っても良い。
第一の樹脂１０ａ、１０ｂの材質は、全体の封止に用い
る第二の樹脂６と同質のものでも良いし、またはシリコ
ンゲルのように軟らかい樹脂であっても良い。しかし、
素子１ａ、ｌｂの回路形成面と密着性の良い材料を用い
なければ意味がない。
本発明の第三の実施例による半導体装置の断面の一部分
を第１３図に示す。本実施例では、接着層８ｃ、８ｄが
絶縁フィルムの機能を兼ねている。
このようにパッケージを構成することにより、フィルム
厚さの二倍だけパッケージを薄くすることができる６本
実施例は、特に、素子の表面にポリイミド等の保護膜が
形成されている場合に、素子上の回路と配線パターンの
電気的絶縁が確実にとれるので有効である。
本発明の第四の実施例による半導体装置の断面の一部分
を第１４図に示す０本実施例では、配線パターンとして
、金属箔１１が用いられているので、パッケージを薄く
することができる。絶縁フィルム３にパターン形成され
た金属箔を接着するのは困難であるので、既にテープオ
ートメイテッドボンディング技術で用いられているよう
に、フィルムに金属箔を接着した後、エツチングにより
パターン形成を行う方法が有効である。本実施例では、
このようにパターン形成されたフィルムを素子１ａ、ｌ
ｂに接着した後、第４図の（４０４）工程以降の工程を
経て製造することができる。金属箔の材質としては１例
えば、銅が挙げられる。
本発明の第五の実施例による半導体装置の断面の一部分
を第１５図に示す。本実施例では、配線パターンとして
金属箔１２を用い、金属箔１２が素子電極７の近傍で絶
縁フィルム３からはみ出ており、金属箔１２のはみ出た
部分１３が、はんだ。
金シリコン共晶合金等を介し、電極７に熱圧着されて、
電気的に接続されている。このようにパッケージを構成
することで、ワイヤが不要になり、ワイヤ高さを確保す
る必要がなくなり、従って。
第四の実施例に比べても、さらに、パッケージの薄形化
を達成することができる。現状のパッケージ組立技術を
用いた場合の本実施例のパッケージ厚さを試算すると、
１．１閣まで薄くすることが可能である。なお、金属箔
１３と電極７の接合は。
テープオートメイテッドボンディングの技術を用いれば
、容易に行うことができる。
〔発明の効果〕 本発明は、以下説明したように構成されているので、以
下に記載されるような効果を奏する。
素子の上に配線パターンが設けられているので、電極が
中央部にある素子二枚を一つのパッケージに搭載するこ
とができる。
また、素子の側面とパッケージの側面との間に電気的接
続部分を設ける必要がないので、大形の素子を搭載する
ことができる。
また、本発明による半導体装置は、１．１■まで薄くす
ることができる。
【図面の簡単な説明】
第１図は本発明の第一の実施例による半導体装置の断面
図、第２図は第一の実施例の電極付近の拡大断面図、第
３図は第一の実施例のパッケージ側面付近の拡大断面図
、第４図は第一の実施例の製造方法を示す説明図、第５
図から第１０図までは第一の実施例を部分的に変更した
半導体装置の断面図、第１１図は第二の実施例による半
導体装置の部分拡大断面図、第１２図は第二の実施例を
部分的に変更した半導体装置の部分拡大断面図、第１３
図は第三の実施例の部分拡大断面図、第１４図は第四の
実施例の部分拡大断面図、第１５図は第五の実施例の部
分拡大断面図、第１６図は従来のリードオンチップ構造
の内部を示す斜視図である。 １・・・半導体素子、２・・・リードフレーム、３・・
・絶縁フィルム、４・・・配線パターン、５・・・ワイ
ヤ、６・・・封止樹脂、７・・・電極、８・・・接着層
、９・・・導電性接着層、１０・・・樹脂、１１・・・
金属箔配線パターン、１２・・・金属箔配線パターンの
電極接合部。

Claims (1)

  1. 【特許請求の範囲】 １、半導体素子と、リードの集合体から成るリードフレ
    ームと、前記半導体素子と前記リードフレームとを電気
    的に接続する手段を設け、前記リードフレームの一部と
    前記半導体素子と電気的接続部分とを樹脂で封止するこ
    とによりパッケージを形成した半導体装置において、 前記半導体素子を二枚用い、前記二枚の半導体素子の回
    路形成面が対向しており、それぞれの前記半導体素子の
    回路形成面上の電極を除く部分の少なくとも一部分に絶
    縁フィルムを設け、それぞれの前記半導体素子の前記絶
    縁フィルム上に金属の配線パターンを形成し、前記配線
    パターンとそれぞれの前記半導体素子の前記電極とを電
    気的に接続し、二枚の前記半導体素子の間に前記リード
    フレームを挿入し、前記配線パターンと前記リードフレ
    ームを電気的に接続したことを特徴とする樹脂封止型半
    導体装置。 ２、請求項１において、前記半導体素子の電極と前記配
    線パターンをワイヤにより電気的に接続した半導体装置
    。 ３、請求項１において、前記配線パターンの金属の一部
    分を前記絶縁フィルムからはみ出させ、この部分の金属
    と前記半導体素子の電極を熱圧着により電気的に接続し
    た半導体装置。 ４、請求項１において、前記配線パターンとリードフレ
    ームをはんだにより電気的に接続した半導体装置。 ５、請求項４において、前記はんだの融点が２５０℃以
    上である半導体装置。 ６、請求項１において、前記配線パターンと前記リード
    フレームを導電性樹脂により電気的に接続した半導体装
    置。 ７、請求項１において、前記配線パターンと前記半導体
    素子を電気的に接続する部分及び前記半導体素子の回路
    形成面でフィルムで覆われていない部分の少なくとも一
    部を第一の封止樹脂で覆い、前記リードフレームの一部
    とこれらの構成部材を第二の樹脂で封止した半導体装置
    。 ８、請求項１において、前記半導体素子が長方形であり
    、前記半導体素子の電極が前記半導体素子の二つの中心
    線のうち少なくとも一つの中心線の近傍に配置されてい
    る半導体装置。 ９、請求項１において、前記半導体素子がメモリＬＳＩ
    である半導体装置。 １０、請求項１において、前記配線パターンが金属箔で
    ある半導体装置。
JP2155167A 1990-06-15 1990-06-15 樹脂封止型半導体装置 Expired - Fee Related JP2816239B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2155167A JP2816239B2 (ja) 1990-06-15 1990-06-15 樹脂封止型半導体装置
KR1019910008853A KR950005446B1 (ko) 1990-06-15 1991-05-30 수지봉지형 반도체장치
US07/713,100 US5539250A (en) 1990-06-15 1991-06-11 Plastic-molded-type semiconductor device
EP91109654A EP0461639B1 (en) 1990-06-15 1991-06-12 Plastic-molded-type semiconductor device
DE69127587T DE69127587T2 (de) 1990-06-15 1991-06-12 In Kunststoff eingeformte Halbleiteranordnung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2155167A JP2816239B2 (ja) 1990-06-15 1990-06-15 樹脂封止型半導体装置

Publications (2)

Publication Number Publication Date
JPH0448767A true JPH0448767A (ja) 1992-02-18
JP2816239B2 JP2816239B2 (ja) 1998-10-27

Family

ID=15599977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2155167A Expired - Fee Related JP2816239B2 (ja) 1990-06-15 1990-06-15 樹脂封止型半導体装置

Country Status (5)

Country Link
US (1) US5539250A (ja)
EP (1) EP0461639B1 (ja)
JP (1) JP2816239B2 (ja)
KR (1) KR950005446B1 (ja)
DE (1) DE69127587T2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5582568A (en) * 1993-02-11 1996-12-10 Valmet Corporation Method for coating a roll and a coated roll for a paper machine
US6175149B1 (en) * 1998-02-13 2001-01-16 Micron Technology, Inc. Mounting multiple semiconductor dies in a package
US6297547B1 (en) * 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2708191B2 (ja) * 1988-09-20 1998-02-04 株式会社日立製作所 半導体装置
KR920702545A (ko) * 1990-06-26 1992-09-04 아이자와 스스무 반도체 장치 및 그 제조 방법
US5086018A (en) * 1991-05-02 1992-02-04 International Business Machines Corporation Method of making a planarized thin film covered wire bonded semiconductor package
KR940003560B1 (ko) * 1991-05-11 1994-04-23 금성일렉트론 주식회사 적층형 반도체 패키지 및 그 제조방법.
DE4214102C2 (de) * 1991-06-01 1997-01-23 Gold Star Electronics Multichip-Halbleiterbaustein
JPH0661289A (ja) * 1992-08-07 1994-03-04 Mitsubishi Electric Corp 半導体パッケージ及びこれを用いた半導体モジュール
JP2856642B2 (ja) * 1993-07-16 1999-02-10 株式会社東芝 半導体装置及びその製造方法
JP3150253B2 (ja) * 1994-07-22 2001-03-26 三菱電機株式会社 半導体装置およびその製造方法並びに実装方法
KR0147259B1 (ko) * 1994-10-27 1998-08-01 김광호 적층형 패키지 및 그 제조방법
GB2296992A (en) * 1995-01-05 1996-07-17 Int Rectifier Co Ltd Electrode configurations in surface-mounted devices
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
KR100204753B1 (ko) * 1996-03-08 1999-06-15 윤종용 엘오씨 유형의 적층 칩 패키지
US5907184A (en) * 1998-03-25 1999-05-25 Micron Technology, Inc. Integrated circuit package electrical enhancement
US5763945A (en) * 1996-09-13 1998-06-09 Micron Technology, Inc. Integrated circuit package electrical enhancement with improved lead frame design
JP2908350B2 (ja) * 1996-10-09 1999-06-21 九州日本電気株式会社 半導体装置
KR100226737B1 (ko) * 1996-12-27 1999-10-15 구본준 반도체소자 적층형 반도체 패키지
US5780923A (en) 1997-06-10 1998-07-14 Micron Technology, Inc. Modified bus bar with Kapton™ tape or insulative material on LOC packaged part
US6580157B2 (en) * 1997-06-10 2003-06-17 Micron Technology, Inc. Assembly and method for modified bus bar with Kapton™ tape or insulative material in LOC packaged part
JP2000100814A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd 半導体装置
KR100333388B1 (ko) * 1999-06-29 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조 방법
JP3406270B2 (ja) * 2000-02-17 2003-05-12 沖電気工業株式会社 半導体装置及びその製造方法
DE10023823A1 (de) * 2000-05-15 2001-12-06 Infineon Technologies Ag Multichip-Gehäuse
DE10114897A1 (de) * 2001-03-26 2002-10-24 Infineon Technologies Ag Elektronisches Bauteil
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
DE10255289A1 (de) * 2002-11-26 2004-06-17 Infineon Technologies Ag Elektronisches Bauteil mit gestapelten Halbleiterchips in paralleler Anordnung und Verfahren zu dessen Herstellung
DE10259221B4 (de) * 2002-12-17 2007-01-25 Infineon Technologies Ag Elektronisches Bauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
DE102006026023A1 (de) * 2006-06-01 2007-12-06 Infineon Technologies Ag Halbleiterbauteil mit Halbleiterchipstapel und Kunststoffgehäuse sowie Verfahren zur Herstellung des Halbleiterbauteils
CN101933139B (zh) * 2007-12-20 2012-11-07 爱信艾达株式会社 半导体装置及其制造方法
JP5018909B2 (ja) * 2009-06-30 2012-09-05 株式会社デンソー 半導体装置
JP6598740B2 (ja) * 2016-07-15 2019-10-30 三菱電機株式会社 半導体装置
JP2018049942A (ja) * 2016-09-21 2018-03-29 アイシン精機株式会社 変位センサ

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3893158A (en) * 1972-03-15 1975-07-01 Motorola Inc Lead frame for the manufacture of electric devices having semiconductor chips placed in a face to face relation
DE2409312C3 (de) * 1974-02-27 1981-01-08 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Halbleiteranordnung mit einer auf der Halbleiteroberfläche angeordneten Metallschicht und Verfahren zu ihrer Herstellung
JPS5588356A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Semiconductor device
EP0076856A4 (en) * 1981-04-21 1984-03-01 Seiichiro Aigoo METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A PLATED HIGHLIGHT ELECTRODE.
JPS59229850A (ja) * 1983-05-16 1984-12-24 Rohm Co Ltd 半導体装置
JPS6224650A (ja) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp 半導体装置
JPS6477135A (en) * 1987-09-18 1989-03-23 Hitachi Maxell Semiconductor device
US5068712A (en) * 1988-09-20 1991-11-26 Hitachi, Ltd. Semiconductor device
JP2702219B2 (ja) * 1989-03-20 1998-01-21 株式会社日立製作所 半導体装置及びその製造方法
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
US4965654A (en) * 1989-10-30 1990-10-23 International Business Machines Corporation Semiconductor package with ground plane
EP0454447A3 (en) * 1990-04-26 1993-12-08 Hitachi Ltd Semiconductor device assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5582568A (en) * 1993-02-11 1996-12-10 Valmet Corporation Method for coating a roll and a coated roll for a paper machine
US6175149B1 (en) * 1998-02-13 2001-01-16 Micron Technology, Inc. Mounting multiple semiconductor dies in a package
US6297547B1 (en) * 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package

Also Published As

Publication number Publication date
EP0461639B1 (en) 1997-09-10
KR920001690A (ko) 1992-01-30
JP2816239B2 (ja) 1998-10-27
KR950005446B1 (ko) 1995-05-24
US5539250A (en) 1996-07-23
DE69127587D1 (de) 1997-10-16
DE69127587T2 (de) 1998-04-23
EP0461639A2 (en) 1991-12-18
EP0461639A3 (en) 1993-09-22

Similar Documents

Publication Publication Date Title
JPH0448767A (ja) 樹脂封止型半導体装置
JP3481444B2 (ja) 半導体装置及びその製造方法
KR970010678B1 (ko) 리드 프레임 및 이를 이용한 반도체 패키지
US4835120A (en) Method of making a multilayer molded plastic IC package
US6528353B2 (en) Chip stack-type semiconductor package and method for fabricating the same
JP2547697B2 (ja) 多層リードフレームアセンブリを作る方法および多層集積回路ダイパッケージ
US6153924A (en) Multilayered lead frame for semiconductor package
JP2001036000A (ja) チップサイズスタックパッケージ及びメモリモジュールとその製造方法
JP2001024135A (ja) 半導体装置の製造方法
JPH08148603A (ja) ボールグリッドアレイ型半導体装置およびその製造方法
JPH06302653A (ja) 半導体装置
JPS62232948A (ja) リ−ドフレ−ム
JP2001332580A (ja) 半導体装置及びその製造方法
JP2569400B2 (ja) 樹脂封止型半導体装置の製造方法
JP2003023133A (ja) リードフレームおよびそれを用いた樹脂封止型半導体装置ならびにその製造方法
JPH0917910A (ja) 半導体装置及びその製造方法、検査方法、実装基板
JPH0817870A (ja) 半導体装置
EP0474224B1 (en) Semiconductor device comprising a plurality of semiconductor chips
JP3490601B2 (ja) フィルムキャリアおよびそれを用いた積層型実装体
JP3466354B2 (ja) 半導体装置
JPH0878599A (ja) 集積回路パッケージ及びその製造方法
JP2954108B2 (ja) 半導体装置およびその製造方法
JP2006066551A5 (ja)
JP2986661B2 (ja) 半導体装置の製造方法
JP2944586B2 (ja) Ｂｇａ型半導体装置及びその製造方法

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees