JP2954108B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

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Publication number
JP2954108B2
JP2954108B2 JP9256988A JP25698897A JP2954108B2 JP 2954108 B2 JP2954108 B2 JP 2954108B2 JP 9256988 A JP9256988 A JP 9256988A JP 25698897 A JP25698897 A JP 25698897A JP 2954108 B2 JP2954108 B2 JP 2954108B2
Authority
JP
Japan
Prior art keywords
conductive
semiconductor device
semiconductor chip
insulating tape
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9256988A
Other languages
English (en)
Other versions
JPH1197472A (ja
Inventor
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP9256988A priority Critical patent/JP2954108B2/ja
Priority to US09/157,474 priority patent/US6011306A/en
Priority to CN98120024A priority patent/CN1213176A/zh
Publication of JPH1197472A publication Critical patent/JPH1197472A/ja
Application granted granted Critical
Publication of JP2954108B2 publication Critical patent/JP2954108B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)

Description

【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は半導体装置およびそ
の製造方法に関し、特にリードオンチィップ(LOC)
型のモールド・ボールグリッドアレイ(BGA)半導体
装置およびその製造方法に関する。
【0002】
【従来の技術】一般的な従来のLOC構造のBGA半導
体装置は、図7の斜視図に示すように、半導体チップ1
上に絶縁接着テープ22によりリード19を接合し、半
導体チップ1上のパッド2からポンディングワイヤ3を
リード19の端部にポンディングしている。このポンデ
ィングワイヤ3を含む半導体チップ1は、モールド樹脂
4により樹脂封入された後、リード19上に半田ボール
10を搭載して半導体装置を完成している。この場合、
ポンディングはパッド10からリード19の隙間の外側
斜め上方から行われることになる。
【0003】
【発明が解決しようとする課題】上述した従来例の半導
体装置では、半導体チップ1が小さくなった時、または
多ピンとなった時に、リード19は支持のためのリード
フレーム20と接続する必要があり、リード19どうし
の間隔が極めて狭くなり、ポンディングワイヤ3をポン
ディングする際に用いられるワイヤボンディング装置の
キャピラリの挿入が困難になり、ワイヤボンディングが
不可能となるという問題がある。
【0004】本発明の目的は、このような問題を解決
し、半導体チップの小型化、多ピン化に対応してリード
を不要とした接続構造をもった半導体装置およびその製
造方法を提供することにある。
【0005】
【課題を解決するための手段】本発明の半導体装置の構
成は、半導体チップ上に部分的に導電部を形成した絶縁
性樹脂シャフトが接合され、前記半導体チップのパッド
から前記樹脂シャフトの導電部にボンディングワイヤが
接続され、この導電部に外部接続端子が接続されたこと
特徴とし、また半導体チップ上に部分的に導電パッド部
を形成した絶縁性テープが接合され、前記半導体チップ
のパッドから前記絶縁性テープの導電パッド部にボンデ
ィングワイヤが接続され、この導電パッド部に外部接続
端子が接続されたことを徴とする。
【0006】本発明において、絶縁性テープの導電パッ
ド部が導電ピンを介して外部接続端子に接続されること
もでき、また外部接続端子を半田ボールとしてボールグ
リッドアレイ構造とすることもできる。
【0007】さらに本発明の半導体装置の製造方法は、
半導体チップ上に部分的に導電部が形成された絶縁性樹
脂シャフトまたは絶縁性テープを接合し、前記半導体チ
ップのパッドから前記樹脂シャフトまたは絶縁性テープ
の導電部にワイヤボンディングによりワイヤを接続し、
この導電部に外部接続端子を接続することを特徴とし、
また本発明において、ワイヤを接続した半導体チップを
樹脂封入した後、樹脂シャフトまたは絶縁性テープの導
電部表面に半田ボールを接合してボールグリッドアレイ
構造とすることもできる。
【0008】本発明の構成によれば、半導体チップから
リードの隙間を通ることなく、最短距離でパッドとリー
ドとを接続することができ、半導体装置を小型化するこ
とが可能となる。
【0009】
【発明の実施の形態】次に本発明の実施の形態を図面に
より説明する。図1(a)(b)は、本発明の一実施形
態のリードの代りとなる絶縁樹脂シャフトを用いた半導
体装置の部分破砕平面図およびその断面図である。本実
施形態は、従来例のリードの代りに、半田めっき部8等
の低融点金属による導電部を設けた絶縁樹脂シャフト7
を用いている。すなわち図1(a)において、半導体チ
ップ1はリードフレーム(20)のアイランド5上に銀
ペースト6を接着剤にして接合され搭載される。この半
導体チップ1上のパッド2からボンディングワイヤ3に
より絶縁樹脂シャフト7の半田めっき部8に接合され、
この接合の終了した半導体チップ1全体は封止樹脂4に
より封止された後、絶縁樹脂シャフト7の半田めっき部
8の配置に対応する個所に半田ボール10を搭載し接合
する。
【0010】この絶縁樹脂シャフト7は、図2の工程順
断面図のように製造される。まず図2(a)のように、
絶縁性の樹脂材料で円柱状のシャフト7を形成するが、
このシャフト形状は四角柱でもよい。次に図2(b)の
ように、半田めっきを付けない個所にレジスト11を塗
布する。次に図2(c)のように、めっきのベース金属
となるパラジウム等の金属を蒸着や薬液によりベース金
属蒸着部12に被着させる。次に図2(d)のように、
無電解めっき法によりシャフト半田めっき13を付着さ
せ、図2(e)のように、最初のレジスト11を除去
し、半田めっき部13を残す。
【0011】本実施形態の製造方法を、図3,図4によ
り説明する。まず図3(a)(b)の平面図および断面
図に示すように、このリードフレーム20には1つのア
イランド5の両側(左右)の吊りリード14部分に支持
板15が垂直に配設されている。このアイランド5上に
半導体チップ1が銀ペースト6を接着剤にして接合し搭
載される。
【0012】次に図4(a)に示すように、半導体チッ
プ1上に、図2で製造した絶縁樹脂シャフト7を絶縁性
接着剤9により接着する。さらに図4(b)に示すよう
に、半導体チップ1上のパッド2から支持板15に向っ
てボンディングワイヤ3を張り、パッド2およびシャフ
ト半田めっき部13をワイヤボンディングして接合す
る。次に図4(c)に示すように、シャフト半田めっき
部13の端部でワイヤ3を切り離し、支持板15を取り
外す。そして図4(d)に示すように、ワイヤ3の接続
された半導体チップ1を封止樹脂4により封止し、シャ
フト半田めっき部13に対応する個所に半田ボール10
を搭載し接合する。
【0013】本実施形態のように、シャフト半田めっき
部13を設けた絶縁樹脂シャフト7を介在させることに
より、リード19を用いずにパッド2から半田めっき部
13を介してワイヤ3を外部端子の半田ボール10への
接続が可能となり、半導体装置を小形化することができ
る。
【0014】図5(a)(b)は、本発明の第2の実施
形態のリードの代りとなる絶縁テープを用いた半導体装
置の斜視図およびその断面図である。本実施形態では、
図1の絶縁樹脂シャフト7の代りに、導電性テープパッ
ド18を載置しピン16を付加した絶縁テープ17を用
いたものである。このような絶縁テープ17は、図5
(a)に示すように、半導体チップ1上に接合し、この
絶縁テープ17上のテープパッド18からワイヤ3にワ
イヤボンディンフを行なう。この際テープパッド18に
はワイヤ3から延長したピン16が、テープパッド18
とほぼ垂直に配設される。この状態から、図5(b)に
示すように、ピン16、ワイヤ3の接続された半導体チ
ップ1を封止樹脂4により封止し、各ピン16の個所を
樹脂封止せずに、各ピン16に対応する個所に半田ボー
ル10を搭載し接合する。
【0015】図6は、本発明の第3の実施形態のリード
の代りとなる絶縁テープを用いた半導体装置の斜視図お
よびその断面図である。本実施形態では、図5のピン1
6を用いずに、絶縁テープ17上のテープパッド18に
直接半田ボール10を搭載し接合したものである。
【0016】これら第2、第3の実施形態においても、
テープパッド18をもつ絶縁テープ17を介在させるこ
とにより、リード19を用いずにワイヤ3を外部端子の
半田ボール10へ直接接続することが可能となり、同様
に半導体装置を小形化することができる。
【0017】
【発明の効果】以上説明したように、本発明の構成によ
れば、従来問題であったリードを用いずに、半導体チッ
プのパッドから外部端子の半田ボールへの接続が可能と
なるため、ワイヤボンディングの自由度が向上し、半導
体装置自体を小形化することができるという効果があ
る。
【図面の簡単な説明】
【図1】本発明の一実施形態の半導体装置の部分破砕平
面図およびその断面図。
【図2】図1の半導体装置の絶縁樹脂シャフトの処理方
法を説明する部分側面図。
【図3】図1の製造工程の半導体チップ搭載時の平面図
および側面図。
【図4】図1の製造工程の絶縁樹脂シャフト組立て時の
工程順の断面図。
【図5】本発明の第2の実施形態を示す斜視図および断
面図。
【図6】本発明の第3の実施形態を示す断面図。
【図7】従来例の半導体装置の構造を示す透視斜視図。
【符号の説明】
1 半導体チップ 2 パッド 3 ボンディングワイヤ 4 モールド樹脂 5 リードフレームのアイランド 6 銀ペースト 7 絶縁樹脂シャフト 8 半田めっき 9 接着剤 10 半田ボール 11 レジスト 12 ベース金属蒸着部 13 シャフト半田めっき 14 吊りリード 15 支持板 16 ピン 17 絶縁テープ 18 テープパッド 19 リード 20 リードフレーム 22 接着テープ

Claims (8)

    (57)【特許請求の範囲】
  1. 【請求項1】 半導体チップ上に部分的に導電部を形成
    した絶縁性樹脂シャフトが接合され、前記半導体チップ
    のパッドから前記樹脂シャフトの導電部にボンディング
    ワイヤが接続され、この導電部に外部接続端子が接続さ
    れたことを特徴とする半導体装置。
  2. 【請求項2】 半導体チップ上に部分的に導電パッド部
    を形成した絶縁性テープが接合され、前記半導体チップ
    のパッドから前記絶縁性テープの導電パッド部にボンデ
    ィングワイヤが接続され、この導電パッド部に外部接続
    端子が接続されたことを特徴とする半導体装置。
  3. 【請求項3】 絶縁性テープの導電パッド部が導電ピン
    を介して外部接続端子に接続された請求項2記載の半導
    体装置。
  4. 【請求項4】 外部接続端子を半田ボールとしてボール
    グリッドアレイ構造とした請求項1,2または3記載の
    半導体装置。
  5. 【請求項5】 樹脂シャフトの導電部または絶縁性テー
    プの導電パッド部が半田めっきからなり、この部分が外
    部接続端子となる請求項1乃至4記載の半導体装置。
  6. 【請求項6】 半導体チップ上に部分的に導電部が形成
    された絶縁性樹脂シャフトまたは絶縁性テープを接合
    し、前記半導体チップのパッドから前記樹脂シャフトま
    たは絶縁性テープの導電部にワイヤボンディングにより
    ワイヤを接続し、この導電部に外部接続端子を接続する
    ことを特徴とする半導体装置の製造方法。
  7. 【請求項7】 絶縁性テープの導電部がワイヤ接続され
    た後、その導電部から前記ワイヤを延長して導電ピンを
    形成し、この導電ピンを外部接続端子に接続する請求項
    6記載の半導体装置の製造方法。
  8. 【請求項8】 ワイヤを接続した半導体チップを樹脂封
    入した後、樹脂シャフトまたは絶縁性テープの導電部表
    面に半田ボールを接合してボールグリッドアレイ構造と
    する請求項6または7記載の半導体装置の製造方法。
JP9256988A 1997-09-22 1997-09-22 半導体装置およびその製造方法 Expired - Fee Related JP2954108B2 (ja)

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US09/157,474 US6011306A (en) 1997-09-22 1998-09-21 Semiconductor device and method for fabricating same
CN98120024A CN1213176A (zh) 1997-09-22 1998-09-22 半导体器件及其制造方法

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US6303992B1 (en) * 1999-07-06 2001-10-16 Visteon Global Technologies, Inc. Interposer for mounting semiconductor dice on substrates
US6888256B2 (en) * 2001-10-31 2005-05-03 Infineon Technologies Ag Compliant relief wafer level packaging
US7071421B2 (en) 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods

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US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US5834339A (en) * 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US5659952A (en) * 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
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